JP7501981B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7501981B2 JP7501981B2 JP2021005071A JP2021005071A JP7501981B2 JP 7501981 B2 JP7501981 B2 JP 7501981B2 JP 2021005071 A JP2021005071 A JP 2021005071A JP 2021005071 A JP2021005071 A JP 2021005071A JP 7501981 B2 JP7501981 B2 JP 7501981B2
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 78
- 229910052751 metal Inorganic materials 0.000 claims description 123
- 239000002184 metal Substances 0.000 claims description 123
- 239000000758 substrate Substances 0.000 claims description 53
- 230000008878 coupling Effects 0.000 claims description 45
- 238000010168 coupling process Methods 0.000 claims description 45
- 238000005859 coupling reaction Methods 0.000 claims description 45
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 238000004088 simulation Methods 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 5
- 230000005496 eutectics Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000001902 propagating effect Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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Description
一実施形態に係る半導体装置は、トランジスタ素子と、複数の入力ワイヤと、複数の出力ワイヤと、を備える。トランジスタ素子は、一辺に沿って複数配置された入力パッドと、一辺に対向する他辺に沿って複数配置された出力パッドとを有する。複数の入力ワイヤは、入力パッドそれぞれに接続されている。複数の出力ワイヤは、出力パッドそれぞれに接続され、複数の入力ワイヤより長いワイヤの長さを有する。隣接する入力ワイヤは互いに平行に配置され、隣接する出力ワイヤは互いに非平行に配置される。
[本発明の実施形態の詳細]
(変形例)
2a,2b,2c,2d,2e,2f,2g,2h…ワイヤ
3…パッケージ
5…トランジスタ素子
5a…上面
5b…長辺
5c…短辺
5d…一辺
6,7…入力分岐回路基板
8…入力回路基板
9…出力回路基板
9a…上面
9b…長辺
9c…短辺
10,11…出力結合回路基板
21…金属
22…AuSn共晶はんだ
31…ベース
31a,31b…端辺
31c…ネジ受け
31d…板面
32…枠体
32a,32b,32c,32d…部分
33…リッド
34…入力端子
35…出力端子
36…空間
50…ゲートパッド
51,511,512…ドレインパッド
61,71,81,91,101,111…誘電体基板
62,72…分岐回路
63,73…分岐パターン
73a,103a…金属パッド
74,104…膜抵抗
82,92…金属パターン
102,112…合波回路
103,113…結合パターン
D1,D2…方向
J…電流経路
Q…軸線
Claims (15)
- 一辺に沿って複数配置された入力パッドと、前記一辺に対向する他辺に沿って複数配置された出力パッドとを有するトランジスタ素子と、
前記入力パッドそれぞれに接続された複数の入力ワイヤと、
前記出力パッドそれぞれに接続され、前記複数の入力ワイヤより長いワイヤの長さを有する複数の出力ワイヤと、を備え、
隣接する前記入力ワイヤは互いに平行に配置され、隣接する前記出力ワイヤは互いに非平行に配置される、半導体装置。 - 金属パターンを有する出力回路基板をさらに備え、
金属パターンは、少なくとも二つの前記出力パッドに前記出力ワイヤを介して接続されており、
前記少なくとも二つの出力パッドに前記金属パターンを接続する隣接する前記出力ワイヤ同士の間隔は、前記出力パッド側よりも前記金属パターン側で小さい、請求項1に記載の半導体装置。 - 前記少なくとも二つの出力パッドから延びる前記出力ワイヤの一端同士は、前記金属パターンと接続する接続ポイントにおいて互いに接触している、請求項2に記載の半導体装置。
- 前記少なくとも二つの出力パッドから延びる前記出力ワイヤ同士の成す角が45°以上55°以下である、請求項2又は請求項3に記載の半導体装置。
- 別の金属パターンを有する入力回路基板をさらに備え、
前記別の金属パターンは、少なくとも二つの前記入力パッドに前記入力ワイヤを介して接続されている、請求項1から請求項4のいずれか一項に記載の半導体装置。 - 複数の別の金属パターンを有する入力回路基板と、
前記トランジスタ素子と、前記入力回路基板と、前記出力回路基板と、を搭載するベースと、
前記ベース上に設けられ、前記トランジスタ素子と、前記入力回路基板と、前記出力回路基板とを囲む枠体と、
前記枠体に設けられ、前記入力回路基板と接続する入力端子と、
前記枠体に設けられ、前記出力回路基板と接続する出力端子と、
をさらに備え、
前記入力回路基板の前記別の金属パターンそれぞれは、少なくとも二つの前記入力パッドに前記入力ワイヤを介して接続されている、請求項2に記載の半導体装置。 - 前記トランジスタ素子と、前記入力回路基板と、前記出力回路基板とは、それぞれ複数設けられている、請求項6に記載の半導体装置。
- 一端が前記入力端子と接続され、他端が複数の前記入力回路基板と接続されている分岐パターンを有する入力分岐回路基板と、
一端が複数の前記出力回路基板と接続され、他端が前記出力端子と接続されている結合パターンを有する出力結合回路基板と、をさらに備える、請求項7に記載の半導体装置。 - 前記トランジスタ素子と、前記出力回路基板と、が搭載されるベースをさらに備え、
前記出力回路基板は、誘電体基板の上面に前記金属パターンを有し、前記誘電体基板の裏面が前記ベースと接続され、前記金属パターンと前記ベースとの間に容量成分を有する、請求項2に記載の半導体装置。 - 前記トランジスタ素子と、前記入力回路基板と、が搭載されるベースをさらに備え、
前記入力回路基板は、誘電体基板の上面に前記別の金属パターンを有し、前記誘電体基板の裏面が前記ベースと接続され、前記別の金属パターンと前記ベースとの間に容量成分を有する、請求項5に記載の半導体装置。 - 前記入力分岐回路基板は、誘電体基板の上面に前記分岐パターンを有し、前記誘電体基板の裏面が前記ベースと接続され、前記分岐パターンと前記ベースとの間に容量成分を有する、請求項8に記載の半導体装置。
- 前記出力結合回路基板は、誘電体基板の上面に前記結合パターンを有し、前記誘電体基板の裏面が前記ベースと接続され、前記結合パターンと前記ベースとの間に容量成分を有する、請求項8に記載の半導体装置。
- 前記出力パッドはドレインパッドである、請求項1から請求項12のいずれか一項に記載の半導体装置。
- 前記入力パッドはゲートパッドである、請求項1から請求項13のいずれか一項に記載の半導体装置。
- 前記トランジスタ素子の半導体部分は、窒化ガリウム系半導体からなる、請求項1から請求項14のいずれか一項に記載の半導体装置。
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