JP7430425B2 - 双安定回路および電子回路 - Google Patents

双安定回路および電子回路 Download PDF

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Publication number
JP7430425B2
JP7430425B2 JP2022500317A JP2022500317A JP7430425B2 JP 7430425 B2 JP7430425 B2 JP 7430425B2 JP 2022500317 A JP2022500317 A JP 2022500317A JP 2022500317 A JP2022500317 A JP 2022500317A JP 7430425 B2 JP7430425 B2 JP 7430425B2
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voltage
circuit
line
fet
node
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JP2022500317A
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English (en)
Japanese (ja)
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JPWO2021161808A5 (ja
JPWO2021161808A1 (https=
Inventor
聡 菅原
勇作 塩津
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Japan Science and Technology Agency
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Japan Science and Technology Agency
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Publication of JPWO2021161808A1 publication Critical patent/JPWO2021161808A1/ja
Publication of JPWO2021161808A5 publication Critical patent/JPWO2021161808A5/ja
Priority to JP2024008592A priority Critical patent/JP7639247B2/ja
Application granted granted Critical
Publication of JP7430425B2 publication Critical patent/JP7430425B2/ja
Priority to JP2024096368A priority patent/JP7735620B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Physics & Mathematics (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Neurology (AREA)
  • Biophysics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Semiconductor Memories (AREA)
JP2022500317A 2020-02-10 2021-01-29 双安定回路および電子回路 Active JP7430425B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2024008592A JP7639247B2 (ja) 2020-02-10 2024-01-24 記憶回路
JP2024096368A JP7735620B2 (ja) 2020-02-10 2024-06-14 処理装置

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2020020954 2020-02-10
JP2020020954 2020-02-10
JP2020178364 2020-10-23
JP2020178364 2020-10-23
PCT/JP2021/003224 WO2021161808A1 (ja) 2020-02-10 2021-01-29 双安定回路、電子回路、記憶回路および処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2024008592A Division JP7639247B2 (ja) 2020-02-10 2024-01-24 記憶回路

Publications (3)

Publication Number Publication Date
JPWO2021161808A1 JPWO2021161808A1 (https=) 2021-08-19
JPWO2021161808A5 JPWO2021161808A5 (ja) 2022-10-19
JP7430425B2 true JP7430425B2 (ja) 2024-02-13

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JP2022500317A Active JP7430425B2 (ja) 2020-02-10 2021-01-29 双安定回路および電子回路
JP2024008592A Active JP7639247B2 (ja) 2020-02-10 2024-01-24 記憶回路
JP2024096368A Active JP7735620B2 (ja) 2020-02-10 2024-06-14 処理装置

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JP2024008592A Active JP7639247B2 (ja) 2020-02-10 2024-01-24 記憶回路
JP2024096368A Active JP7735620B2 (ja) 2020-02-10 2024-06-14 処理装置

Country Status (6)

Country Link
US (2) US12183392B2 (https=)
EP (1) EP4105932A4 (https=)
JP (3) JP7430425B2 (https=)
CN (1) CN115053293A (https=)
TW (2) TWI891723B (https=)
WO (1) WO2021161808A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3128570B1 (fr) * 2021-10-25 2023-10-27 Commissariat Energie Atomique Sram a initialisation reconfigurable
US12224034B2 (en) 2022-05-11 2025-02-11 Macronix International Co., Ltd. Memory device and data approximation search method thereof
US12073883B2 (en) 2022-05-11 2024-08-27 Macronix International Co., Ltd. Ternary content addressable memory
WO2025253953A1 (ja) * 2024-06-07 2025-12-11 ソニーセミコンダクタソリューションズ株式会社 メモリ装置及び電子機器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059043A (ja) 2005-07-29 2007-03-08 Semiconductor Energy Lab Co Ltd 半導体装置及びその駆動方法
JP2013525936A (ja) 2010-04-21 2013-06-20 日本テキサス・インスツルメンツ株式会社 高性能スタティックメモリのリテイン・ティル・アクセスド（ｒｔａ）省電力モード
WO2020070830A1 (ja) 2018-10-03 2020-04-09 株式会社ソシオネクスト 半導体記憶装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3260357B2 (ja) * 1990-01-24 2002-02-25 株式会社日立製作所 情報処理装置
JP2002109875A (ja) 2000-09-29 2002-04-12 Nec Corp 強誘電体容量を用いたシャドーｒａｍセル及び不揮発性メモリ装置並びにその制御方法
JP4459696B2 (ja) 2004-04-20 2010-04-28 旭化成エレクトロニクス株式会社 半導体記憶装置及びデジタルフィルタ
US7164608B2 (en) * 2004-07-28 2007-01-16 Aplus Flash Technology, Inc. NVRAM memory cell architecture that integrates conventional SRAM and flash cells
DE602006017777D1 (de) 2005-07-29 2010-12-09 Semiconductor Energy Lab Halbleiterspeicher und dessen Betriebsverfahren
US20070242498A1 (en) * 2006-04-13 2007-10-18 Anantha Chandrakasan Sub-threshold static random access memory
JP5170706B2 (ja) 2007-08-31 2013-03-27 国立大学法人東京工業大学 スピン注入磁化反転ｍｔｊを用いた不揮発性ｓｒａｍ／ラッチ回路
US20110205787A1 (en) * 2008-10-22 2011-08-25 Nxp B.V. Dual-rail sram with independent read and write ports
FR2956516B1 (fr) * 2010-02-15 2012-12-07 St Microelectronics Sa Cellule de memoire vive sram a dix transistors
WO2013018156A1 (ja) * 2011-07-29 2013-02-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5312715B1 (ja) 2012-05-18 2013-10-09 独立行政法人科学技術振興機構 双安定回路と不揮発性素子とを備える記憶回路
US20150294991A1 (en) 2014-04-10 2015-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device
EP3182414B1 (en) 2014-08-12 2021-01-13 Japan Science and Technology Agency Memory circuit
CN107408939B (zh) * 2015-04-01 2020-09-25 国立研究开发法人科学技术振兴机构 电子电路
JP7033507B2 (ja) 2018-07-31 2022-03-10 株式会社メガチップス ニューラルネットワーク用プロセッサ、ニューラルネットワーク用処理方法、および、プログラム
CN121122351A (zh) * 2019-05-30 2025-12-12 国立研究开发法人科学技术振兴机构 电子电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059043A (ja) 2005-07-29 2007-03-08 Semiconductor Energy Lab Co Ltd 半導体装置及びその駆動方法
JP2013525936A (ja) 2010-04-21 2013-06-20 日本テキサス・インスツルメンツ株式会社 高性能スタティックメモリのリテイン・ティル・アクセスド（ｒｔａ）省電力モード
WO2020070830A1 (ja) 2018-10-03 2020-04-09 株式会社ソシオネクスト 半導体記憶装置

Also Published As

Publication number Publication date
US20250069651A1 (en) 2025-02-27
TW202549269A (zh) 2025-12-16
WO2021161808A1 (ja) 2021-08-19
JP7639247B2 (ja) 2025-03-05
CN115053293A (zh) 2022-09-13
JP2024111064A (ja) 2024-08-16
US20220406370A1 (en) 2022-12-22
JP2024032850A (ja) 2024-03-12
JP7735620B2 (ja) 2025-09-09
TW202137704A (zh) 2021-10-01
JPWO2021161808A1 (https=) 2021-08-19
US12183392B2 (en) 2024-12-31
EP4105932A1 (en) 2022-12-21
EP4105932A4 (en) 2023-06-21
TWI891723B (zh) 2025-08-01

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