WO2021161808A1 - 双安定回路、電子回路、記憶回路および処理装置 - Google Patents

双安定回路、電子回路、記憶回路および処理装置 Download PDF

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Publication number
WO2021161808A1
WO2021161808A1 PCT/JP2021/003224 JP2021003224W WO2021161808A1 WO 2021161808 A1 WO2021161808 A1 WO 2021161808A1 JP 2021003224 W JP2021003224 W JP 2021003224W WO 2021161808 A1 WO2021161808 A1 WO 2021161808A1
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Prior art keywords
data
voltage
circuit
line
fet
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PCT/JP2021/003224
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English (en)
French (fr)
Japanese (ja)
Inventor
菅原聡
塩津勇作
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Japan Science and Technology Agency
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Japan Science and Technology Agency
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Priority to JP2022500317A priority Critical patent/JP7430425B2/ja
Priority to EP21753980.8A priority patent/EP4105932A4/en
Priority to CN202180012857.3A priority patent/CN115053293A/zh
Publication of WO2021161808A1 publication Critical patent/WO2021161808A1/ja
Priority to US17/877,452 priority patent/US12183392B2/en
Anticipated expiration legal-status Critical
Priority to JP2024008592A priority patent/JP7639247B2/ja
Priority to JP2024096368A priority patent/JP7735620B2/ja
Priority to US18/947,451 priority patent/US20250069651A1/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a bistable circuit, an electronic circuit, a storage circuit and a processing device.
  • VNR-SRAM Ultra-low voltage
  • ULV Ultra-low voltage
  • CMOS Complementary Metal Oxide Semiconductor
  • BI boosted inverter
  • NV-SRAM memory cell having a bistable circuit and a non-volatile storage element
  • Patent Document 2 a storage circuit using a memory cell (NV-SRAM) having a bistable circuit and a non-volatile storage element
  • NV-SRAM the data of the bistable circuit is stored in the non-volatile storage element, and while reducing the power consumption, the data of the non-volatile storage element is restored to the bistable circuit when necessary, and the data is put into a usable state.
  • VNR-SRAM In the VNR-SRAM of Patent Document 1, by retaining ULV, the standby power can be reduced without losing the stored contents of the cell.
  • 14 or 10 transistors are used in one memory cell (hereinafter, referred to as 14T cell and 10T cell, respectively). Therefore, there is a first problem that the memory cell becomes large or the cell area increases. Further, when the number of transistors is reduced as in the case of a 10T cell, the stability (noise margin) of ULV retention is lowered.
  • the power supply of the memory cell can be cut off during standby by using the non-volatile storage element in the memory cell, so that the standby power can be reduced.
  • eight transistors are used in one memory cell in addition to the non-volatile memory element. Therefore, there is a second problem that it is difficult to miniaturize the memory cell or the cell area increases.
  • Non-Patent Document 1 has a high effect of speeding up the processing of the neural network, but there is a third problem that there is room for further speeding up.
  • the larger the processing of the neural network the larger the capacity of SRAM for storing coefficients such as the weighting coefficient of the network.
  • the power consumption of the SRAM becomes large because it is required, and the processing power of the neural network becomes large.
  • the first invention of the present application has been made in view of the first or second problem described above, and it is an object of the present invention to provide a bistable circuit and an electronic circuit capable of miniaturization or reduction in the number of transistors.
  • a second object of the second invention of the present application is to provide a storage circuit capable of downsizing or reducing the number of transistors in view of the first or second problem described above.
  • the third invention of the present application provides a processing device capable of speeding up the processing of the neural network.
  • the third purpose is to do.
  • the fourth invention of the present application has a fourth object of reducing the power consumption of the processing of the neural network. ..
  • the first FET of the first conductive type channel in which the source is connected to the power supply line, the drain is connected to the intermediate node, and the gate is connected to the input node, and the source is connected to the intermediate node.
  • the second FET of the first conductive type channel connected and the drain was connected to the output node, one of the source and the drain was connected to the intermediate node, and the other of the source and the drain was connected to the bias node.
  • a second storage node to which an input node of the second inverter circuit is connected is provided, and the gates of the first inverter circuit and the fourth FET of the second inverter circuit are connected to a word line to form the first inverter circuit.
  • the gate of the third FET is connected to any one of the input node and the output node of the first inverter circuit and the input node and the output node of the second inverter circuit, and the gate of the third FET of the second inverter circuit is ,
  • the bistable circuit connected to any one of the input node and the output node of the second inverter circuit, and the input node and the output node of the first inverter circuit.
  • the third FET has the second conductive type channel
  • the gate of the third FET of the first inverter circuit is an input node of the first inverter circuit or an output node of the second inverter circuit.
  • the gate of the third FET of the second inverter circuit may be connected to the input node of the second inverter circuit or the output node of the first inverter circuit.
  • the third FET has the first conductive type channel, and the gate of the third FET of the first inverter circuit is at the output node of the first inverter circuit or the input node of the second inverter circuit.
  • the gate of the third FET of the second inverter circuit may be connected to the output node of the second inverter circuit or the input node of the first inverter circuit.
  • a first alternative invention of the present application is to obtain the bistable circuit and the first voltage between the power supply line and the control line in the first state in which the bistable circuit holds data. It is an electronic circuit including a control circuit for reading data from the circuit or writing data to the bistable circuit to be lower than the second voltage between the first storage node and the second storage node in the second state. ..
  • control circuit may be configured to set the control line as a bit line for reading data from the bistable circuit or writing data to the bistable circuit in the second state. ..
  • the voltage of the word line in the second state, when the first conductive type is N type, the voltage of the word line is made higher than the voltage of the power supply line, and when the first conductive type is P type.
  • the voltage of the word line may be lower than the voltage of the power supply line.
  • control circuit may have a configuration in which the voltage between the word line and the power supply line is lower than the first voltage or the first voltage in the first state.
  • the control circuit uses the voltage between the word line and the power supply line as the second voltage. It can be configured to be lower.
  • a constant bias can be supplied to the bias node in both the first state and the second state.
  • the constant bias can be configured to be between the voltage of the first storage node and the voltage of the second storage node in the second state.
  • the other of the source and drain of the fourth FET is connected to the first control line, the gate of the fourth FET is connected to the first word line, and in the first inverter circuit, the fourth FET is connected.
  • the other of the source and drain is connected to the second control line, the gate of the fourth FET is connected to the second word line, and in the first inverter circuit, one of the source and drain is connected to the first storage node.
  • the source and the other of the drain are connected to the third control line, the gate is connected to the third word line, and the fifth FET of the second conductive type channel is provided, and the control circuit connects the first word line.
  • the 4th FET of the 2nd inverter circuit is turned on, the data is written to the bistable circuit using the 1st control line, and the 4th FET of the 1st inverter circuit is turned on using the 2nd word line.
  • the second control line is used to read data from the bistable circuit
  • the third word line is used to turn on the fifth FET of the first inverter circuit
  • the third control line is used to read data from the bistable circuit. It can be configured to be.
  • the control circuit when the first conductive type is N type, the control circuit writes the voltage of the first word line when reading data from the bistable circuit to the bistable circuit.
  • the voltage of the first word line is higher than the voltage of the first word line, and the voltage of the second word line and the voltage of the third word line when reading data from the bistable circuit is lower than the higher voltage.
  • the first conductive type is P type
  • the voltage of the first word line when reading data from the bistable circuit is lower than the voltage of the first word line when writing data to the bistable circuit.
  • the voltage may be higher than the lower voltage of the second word line voltage and the third word line voltage when reading data from the bistable circuit.
  • the other of the source and drain of the fourth FET is connected to the first control line, the gate of the fourth FET is connected to the first word line, and in the second inverter circuit, the fourth FET is connected.
  • the other of the source and drain is connected to the second control line, the gate of the fourth FET is connected to the first word line, and in the first inverter circuit, one of the source and drain is connected to the first storage node.
  • the source and the other of the drain are connected to the third control line, the gate is connected to the second word line, the fifth FET of the second conductive type channel is provided, and the second inverter circuit is the source and drain.
  • the control circuit uses the first word line to turn on the fourth FET of the first inverter circuit and the second inverter circuit, and uses the first control line and the second control line to input data to the bistable circuit. And read the data from the bistable circuit, turn on the 5th and 6th FETs using the 2nd word line, and use the 3rd control line and the 4th control line to enter the bistable circuit.
  • the configuration can be such that the data is written and the data is read from the bistable circuit.
  • the source is connected to the power supply line
  • the drain is connected to the first storage node
  • the gate is connected to the second storage node
  • the first FET of the first conductive type channel and the source are connected.
  • the second FET of the first conductive channel, which is connected to the power line, the drain is connected to the second storage node, and the gate is connected to the first storage node, and one of the source and drain is connected to the first storage node.
  • the third FET of the second conductive type channel opposite to the first conductive type, which is connected, the other of the source and the drain is connected to the first control line, and the gate is connected to the ward line, and the source and drain.
  • One is connected to the second storage node, the other of the source and the drain is connected to the second control line, and the gate is connected to the word line, and the fourth FET of the second conductive type channel is provided.
  • a bistable circuit a first switch having one end connected to the first storage node, a second switch having one end connected to the second storage node, and one end connected to the other end of the first storage node.
  • a first non-volatile storage element whose other end is connected to the third control line and a second non-volatile storage element whose one end is connected to the other end of the second switch and the other end is connected to the third control line. It is a memory circuit including.
  • the first switch and the second switch are turned off at the time of the write operation of volatilely writing data to the bistable circuit and the read operation of reading from the bistable circuit, and the bistable circuit to the first switch. 1
  • the configuration may include a control circuit for turning on the first switch and the second switch during the restore operation.
  • the control circuit uses the word line as the first voltage, the first control line and the second control line as the second voltage, and the third control line as the second voltage.
  • the first store operation with three voltages
  • the second store with the word line as the fourth voltage
  • the first control line and the second control line as the fifth voltage
  • the third control line as the sixth voltage.
  • the first conductive type is N type
  • the first voltage is lower than the fourth voltage
  • the second voltage and the fifth voltage are higher than the voltage of the power supply line
  • the first voltage is higher than the voltage of the power supply line.
  • the third voltage is lower than the sixth voltage, and when the first conductive type is P type, the first voltage is higher than the fourth voltage, and the second voltage and the fifth voltage are lower than the voltage of the power supply line. ,
  • the third voltage can be configured to be higher than the sixth voltage.
  • the fourth voltage when the first conductive type is N type, the fourth voltage is lower than the fifth voltage, and when the first conductive type is P type, the fourth voltage is higher than the fifth voltage. Can be.
  • the control circuit when executing the restore operation, raises the voltage of the word line higher than the lower voltage of the first storage node and the second storage node during the write operation.
  • the voltage may be lower than the higher voltage of the first storage node and the second storage node.
  • the gate of the third FET is connected to the first word line
  • the gate of the fourth FET is connected to the second word line
  • one of the source and drain of the storage circuit is connected to the second storage node.
  • the source and the other of the drain are connected to the fourth control line
  • the gate is connected to the third word line
  • the fifth FET of the second conductive type channel is provided, and the control circuit is the first word.
  • the control circuit when the first conductive type is N type, the control circuit writes the voltage of the first word line when reading data from the bistable circuit to the bistable circuit.
  • the voltage of the first word line is higher than the voltage of the first word line, and the voltage of the second word line and the voltage of the third word line when reading data from the bistable circuit is lower than the higher voltage.
  • the first conductive type is P type
  • the voltage of the first word line when reading data from the bistable circuit is lower than the voltage of the first word line when writing data to the bistable circuit.
  • the voltage may be higher than the lower voltage of the second word line voltage and the third word line voltage when reading data from the bistable circuit.
  • the gate of the third FET is connected to the first word line
  • the gate of the fourth FET is connected to the first word line
  • one of the source and the drain is connected to the second storage node.
  • the fifth FET of the second conductive channel which is connected, the other of the source and the drain is connected to the fourth control line
  • the gate is connected to the second word line
  • one of the source and drain is the first.
  • the control comprises a sixth FET of the second conductive channel connected to a storage node, the other of the source and the drain connected to a fifth control line, and a gate connected to the second word line.
  • the circuit uses the first word line to turn on the third FET and the fourth FET, writes data to the bistable circuit using the first control line and the second control line, and outputs data from the bistable circuit.
  • a plurality of first data in the first layer are weighted by a plurality of first weights and then added to the plurality of first data corresponding to the plurality of first nodes in the first layer.
  • a first processing unit that calculates the plurality of second data by performing a process of calculating one second data of the plurality of second data corresponding to the second node on the plurality of second data, and the above.
  • the plurality of third data are calculated by performing the operation on the plurality of second data and adding a part of the plurality of third data for each of the plurality of third data by the plurality of second data.
  • the first processing unit is provided with two processing units, and the first processing unit is in parallel with the plurality of second data. It is a processing device that executes the processing of the second data other than the two data.
  • the plurality of first data, the plurality of second data, the plurality of first weights, and the plurality of second weights can each be 1 bit.
  • the plurality of first weights are stored respectively, and the plurality of first weights corresponding to one second data are stored in the same row, and the plurality of first weights corresponding to different second data are stored in different rows.
  • a first memory including a plurality of first memory cells, a plurality of first memory cells connected to a plurality of first memory cells in the same row, and a plurality of first bit lines extending in the column direction, and the plurality of second weights.
  • a second memory cell that stores each and stores a plurality of second weights corresponding to one second data in the same row, and a plurality of second weights corresponding to different second data in different rows.
  • the first processing unit includes a second memory including a plurality of second bit lines each connected to a second memory cell and extending in the column direction, and the first processing unit is one of the plurality of second data.
  • the plurality of first weights are acquired from the first memory via the plurality of first bit lines
  • the second processing unit is the first of the plurality of second data.
  • the configuration may be such that the plurality of second weights are acquired from the second memory via the plurality of second bit lines.
  • the first processing unit processes at least two second data of the plurality of second data in parallel
  • the second processing unit processes at least two of the plurality of second data.
  • the processing of the two second data can be processed in parallel.
  • the plurality of first weights are stored respectively, and the plurality of first weights corresponding to one second data are stored in the same row, and the plurality of first weights corresponding to different second data are stored in different rows.
  • a first memory having a plurality of first memory cells is provided, the plurality of first memory cells each have a pair of complementary storage nodes, and at least one storage node of the pair of storage nodes is in parallel. It is connected to the first bit line and the second bit line extending in the column direction, and when the first processing unit performs one of the processing of at least two second data, the first memory is used as described.
  • the plurality of first weights are acquired via the first bit line and another one of the processes of the at least two second data is performed, the plurality of first weights are obtained from the first memory via the second bit line. It can be configured to acquire the first weight of.
  • the plurality of second weights are stored respectively, and the plurality of second weights corresponding to one second data are stored in the same row, and the plurality of second weights corresponding to different second data are stored in different rows.
  • a second memory having a second memory cell is provided, the plurality of second memory cells each have a pair of complementary storage nodes, and at least one storage node of the pair of storage nodes is in parallel in a column direction.
  • the second processing unit is connected to the third bit line and the fourth bit line extending to the above, and when performing one of the processes of the at least two second data, the third from the second memory.
  • the plurality of second weights are acquired via the bit line and another one of the processes of the at least two second data is performed, the plurality of second weights are obtained from the second memory via the fourth bit line. It can be configured to acquire two weights.
  • the plurality of first weights are stored respectively, and the plurality of first weights corresponding to one second data are stored in the same row, and the plurality of first weights corresponding to different second data are stored in different rows.
  • a first memory having a plurality of first memory cells each of the plurality of first memory cells has a pair of complementary storage nodes, and a part of the first memory of the plurality of first memory cells. At least one storage node of the pair of storage nodes in a cell is connected to a first bit line extending in parallel in the column direction, not to a second bit line, and is another of the plurality of first memory cells.
  • At least one storage node of the pair of storage nodes in some first memory cells is connected to a second bit line extending in parallel in the column direction, and is not connected to the first bit line, and the first
  • the processing unit acquires the plurality of first weights from the first memory via the first bit line
  • the processing unit acquires the plurality of first weights from the first memory and obtains the plurality of first weights from the first memory
  • the processing unit obtains the plurality of first weights from the first memory.
  • the plurality of first weights may be acquired from the first memory via the second bit line.
  • the plurality of second weights are stored respectively, and the plurality of second weights corresponding to one second data are stored in the same row, and the plurality of second weights corresponding to different second data are stored in different rows.
  • a second memory having a plurality of second memory cells is provided, the plurality of second memory cells each have a pair of complementary storage nodes, and a part of the second memory of the plurality of second memory cells. At least one storage node of the pair of storage nodes in a cell is connected to a third bit line extending in parallel in the column direction, not to a fourth bit line, and is another of the plurality of second memory cells.
  • At least one storage node of the pair of storage nodes in some second memory cells is connected to a fourth bit line extending in parallel in the column direction, not to the third bit line, and the second
  • the processing unit acquires the plurality of second weights from the second memory via the third bit line, and the processing unit obtains the plurality of second weights from the second memory, and the processing unit obtains the plurality of second weights from the second memory.
  • the plurality of second weights may be acquired from the second memory via the fourth bit line.
  • the first processing unit weights the plurality of first data by the first weight by XNORing the plurality of first data and the plurality of first weights, and the second processing.
  • the unit can be configured to weight the second data by the second weight by XNORing the second data and the plurality of second weights.
  • a plurality of first memory cells for storing the plurality of first weights
  • a plurality of second memory cells for storing the plurality of second weights, the plurality of first data
  • the plurality of first memory cells By XNORing the first weight, the plurality of first data are weighted by the first weight, and the plurality of first XNOR circuits provided corresponding to the plurality of first memory cells and the one second
  • the data and the plurality of second weights the one second data is weighted by the second weight, and a plurality of second XNOR circuits provided corresponding to the plurality of second memory cells are used. It can be configured to include a memory.
  • a plurality of memory cells each storing the plurality of first weights and the plurality of second weights and having a bistable circuit in which CMOS inverter circuits are connected in a loop, and 10 or less of each.
  • a first power switch that is connected to the virtual power supply line of the memory cell and supplies the first power supply voltage to the virtual power supply line, and a second power switch that supplies the virtual power supply line with a second power supply voltage higher than the first power supply voltage. It can be configured to include a power switch and a memory including the power switch.
  • a memory having a plurality of memory cells for storing the plurality of first weights and the plurality of second weights is provided, and the plurality of memory cells are bistable circuits according to claims 1 to 3, respectively.
  • the configuration may include the storage circuit according to any one of claims 13 to 19.
  • the fourth invention of the present application stores a processing unit that performs at least one of the n-to-1 connection processing and the 1-to-n connection processing of the neural network processing, and data used for the processing performed by the processing unit. Then, a memory having a plurality of rows and a row in which the data to be processed by the processing unit is stored are supplied with a first power supply voltage that enables data to be read, and the first power supply voltage is supplied to rows other than the row. It is a processing device including a power supply circuit that supplies a second power supply voltage or shuts down the power supply voltage, which is lower and capable of holding data.
  • the processing unit performs weighting by a plurality of weights on a plurality of first data corresponding to a plurality of first nodes of the first layer as the n-to-1 connection processing, and then adds the data.
  • the plurality of second data are calculated.
  • the memory stores the plurality of weights, respectively, and stores the plurality of weights corresponding to one second data in the same row, and stores the plurality of weights corresponding to different second data in different rows.
  • the power supply circuit supplies the first power supply voltage to the same row and supplies the second power supply voltage to at least one row other than the same row when performing the process of calculating the one second data. It can be configured to shut down the power supply voltage.
  • the processing unit weights one second data of the plurality of second data corresponding to the plurality of second nodes of the second layer by a plurality of weights.
  • a process of calculating a part of each of the plurality of third data corresponding to the plurality of third nodes of the third layer is performed for the plurality of second data, and for each of the plurality of third data, the plurality of said.
  • the plurality of third data are calculated by adding a part of the third data of the above to the plurality of second data, and the plurality of memories store the plurality of weights, respectively, and correspond to one second data.
  • the plurality of weights to be used are stored in the same line, and the plurality of weights corresponding to different second data are stored in different lines, and the power supply circuit is stored in the same line when performing the process of calculating the one second data.
  • the first power supply voltage may be supplied, and the second power supply voltage may be supplied to the memory cells in at least one row other than the same row, or the power supply voltage may be shut down.
  • the bistable circuit and an electronic circuit which can be miniaturized or the number of transistors can be reduced.
  • the power consumption of the processing of the neural network can be reduced.
  • FIG. 1 is a circuit diagram of a loop display of memory cells in Comparative Example 1.
  • FIG. 2 is a circuit diagram of a cross-coupled display of memory cells in Comparative Example 1.
  • FIG. 3 is a circuit diagram of a loop display of memory cells in Comparative Example 2.
  • FIG. 4 is a circuit diagram of a cross-coupled display of memory cells in Comparative Example 2.
  • FIG. 5 is a circuit diagram of a loop display of memory cells in the first embodiment.
  • FIG. 6 is a circuit diagram of a cross-coupled display of memory cells according to the first embodiment.
  • FIG. 7A is a block diagram of the memory array according to the first embodiment.
  • FIG. 7B is a diagram showing a power switch and a selection circuit according to the first embodiment.
  • FIG. 7C is a block diagram showing another example of the memory array according to the first embodiment.
  • 8 (a) and 8 (b) are diagrams showing SNM and standby power for WLP and WFB in the VDD retention state of Example 1.
  • 9 (a) and 9 (b) are diagrams showing SNM and standby power for VWL in the VDD retention state and read / write state leads of Example 1 and Comparative Example 3.
  • 10 (a) to 10 (c) are diagrams showing SNMs in the VDD retention state and read / write state of Examples 1, Comparative Examples 2 and 3.
  • FIG. 11 is a diagram showing the transmission characteristics of the inverter circuit in the ULV retention state of the first embodiment.
  • 12 (a) and 12 (b) are circuit diagrams of the bistable circuit according to the first embodiment.
  • FIG. 13 (a) and 13 (b) are diagrams showing the butterfly curves of the bistable circuit in the ULV retention state of Example 1, Comparative Examples 2 and 3.
  • 14 (a) is a diagram showing SNM in the ULV retention state of Example 1, Comparative Examples 2 and 3
  • FIG. 14 (b) is a diagram showing SNM and standby power with respect to V VDD in the ULV retention state of Example 1. Is.
  • FIG. 15 is a diagram showing standby power in Example 1 and Comparative Example 3.
  • FIG. 16 is a circuit diagram of a loop display of memory cells in the first modification of the first embodiment.
  • FIG. 17 is a circuit diagram of a cross-coupled display of memory cells in the first modification of the first embodiment.
  • FIG. 18 is a circuit diagram of a loop display of memory cells in the second modification of the first embodiment.
  • FIG. 19 is a circuit diagram of a cross-coupled display of memory cells in the second modification of the first embodiment.
  • FIG. 20 is a diagram showing a butterfly curve of the bistable circuit in the ULV retention state of Example 1 and its modified example 2.
  • 21 (a) and 21 (b) are diagrams showing the voltages of the header PS / PDFB / type 1 and the footer PS / PUFB / type 1, respectively.
  • FIG. 22 is a circuit diagram of a virtual power supply type memory cell according to the second embodiment.
  • FIG. 23 is a diagram showing a power switch and a selection circuit in the virtual power supply system of the second embodiment.
  • FIG. 24 is a circuit diagram of a virtual ground type memory cell according to the second embodiment.
  • FIG. 25 is a diagram showing a power switch and a selection circuit in the virtual grounding method of the second embodiment.
  • FIG. 26 is a block diagram of the memory array according to the second embodiment.
  • 27 (a) to 27 (c) are diagrams showing the operation of the memory cell in the second embodiment.
  • 28 (a) to 28 (c) are diagrams showing the operation of the memory cell in the second embodiment.
  • FIG. 29 is a diagram showing the operation of the memory cell in the second embodiment.
  • FIG. 30 is a diagram showing SNM and standby power for WLP in the hold state in simulation 3.
  • FIG. 31 is a diagram showing SNM for VWL in the read operation and hold state in simulation 3.
  • FIG. 32 (a) and 32 (b) are diagrams showing the currents Im1 and SNM with respect to the voltage VSR of the H-store operation in the simulation 3, respectively.
  • 33 (a) and 33 (b) are diagrams showing the currents Im2 and SNM with respect to the voltage Vc of the L-store operation in the simulation 3, respectively.
  • 34 (a) and 34 (b) are diagrams showing SNMs for voltage VSRs of FF and FS, respectively, of the restore operation in simulation 3.
  • FIG. 35 (a) is a diagram showing SNM in Example 2
  • FIG. 35 (b) is a diagram showing standby power of Example 2 and Comparative Example 3.
  • FIG. 36 is a circuit diagram of the memory cell according to the first modification of the second embodiment.
  • FIG. 37 is a diagram showing a BNN model in Example 3.
  • FIG. 38 is a block of an arithmetic circuit that calculates an n-to-1 connection according to the third embodiment.
  • FIG. 39 (a) is a block of an arithmetic circuit that performs an operation of a 1-to-n connection in the third embodiment, and
  • FIG. 39 (b) is a block diagram of an accumulator.
  • FIG. 40 is a block diagram of the BNN device according to the third embodiment.
  • FIG. 41 is a flowchart showing the processing of the n-to-1 connection performed by the processing unit 52 in the third embodiment.
  • FIG. 42 is a flowchart showing the processing of the 1-ton connection performed by the processing unit 62 in the third embodiment.
  • FIG. 43 is a diagram showing processing for time in Example 3.
  • FIG. 44 is a block diagram showing an example of the memory in the second embodiment.
  • FIG. 45 is a block diagram of the BNN device according to the first modification of the third embodiment.
  • FIG. 46 is a diagram showing an example of the memory in the first modification of the third embodiment.
  • FIG. 47 is a circuit diagram showing an example of a 2R1W type NV-RAM memory cell in the second modification of the third embodiment.
  • FIG. 48 is a circuit diagram showing an example of a 2R1W type ULVR-SRAM memory cell in the second modification of the third embodiment.
  • FIG. 49 (a) is a diagram showing SNM with respect to VWWL of the 2R1W type NV-RAM memory cell in the read operation of the modified example 2 of the third embodiment
  • FIG. 49 (b) is a diagram showing the 2R1W type ULVR-RAM memory cell in the read operation. It is a figure which shows the SNM for VWWL of.
  • FIG. 50 is a circuit diagram showing an example of a 2RW type NV-RAM memory cell in the second modification of the third embodiment.
  • FIG. 51 is a circuit diagram showing an example of a 2RW type ULVR-SRAM memory cell in the second modification of the third embodiment.
  • FIG. 52 is a diagram showing an example of the 2R1W type memory in the second modification of the third embodiment.
  • FIG. 53 is a diagram showing an example of the 2RW type memory in the second modification of the third embodiment.
  • FIG. 54 is a diagram showing processing for time in the modified example of Example 3.
  • FIGS. 55 (a) to 55 (c) are diagrams showing a standardized processing time with respect to the number of layers m.
  • FIG. 56 is a circuit diagram of an NV-RAM memory cell according to a modification 4 of the third embodiment.
  • FIG. 57 is a circuit diagram of the ULVR-SRAM memory cell according to the fourth modification of the third embodiment.
  • FIG. 58 is a block diagram of the BNN device according to the fourth modification of the third embodiment.
  • FIG. 60 is a circuit diagram of the 6T cell in the modified example 5 of the third embodiment.
  • 61 (a) and 61 (b) are diagrams showing SNM and standby power with respect to VDDL in Comparative Example 4 and Modification 5 of Example 3, respectively.
  • FIGS. 1 to 2 Comparative Example 1 FIGS. 3 to 4: Comparative Example 2 5 to 7C: Example 1 8 (a) to 10 (c): Simulation 1, Comparative Examples 2, 3 and Example 1. 11 to 15: Simulation 2, Comparative Examples 2, 3 and Example 1. 16 to 17: Modification 1 of the first embodiment 18 to 20: Modification 2 of the first embodiment 21: Example 1 and its modification FIGS. 22 to 29: Example 2 30 to 35 (b): Simulation 3, Example 2 FIG. 36: Modification 1 of Example 2 37 to 44: Example 3 45 to 46: Modification 1 of Example 3 47 to 53: Modification 2 of Example 3 54 to 55 (c): Simulation of Example 3 and Modifications 1 to 3 FIGS. 56 to 58: Modification 4 of Example 3 FIGS. 59 (a) to 61 (b): Modification 5 of Example 3
  • Comparative Example 1 In Comparative Example 1, the conductive type of the feedback transistor and the connection destination of the gate are different from those in Patent Document 1.
  • 1 and 2 are circuit diagrams of the memory cell 10 in Comparative Example 1.
  • FIG. 1 is a circuit diagram of a loop display
  • FIG. 2 is a circuit diagram of a cross-couple display. Although the circuits of FIGS. 1 and 2 are the same, the loop display of FIG. 1 is easy to understand for the explanation of the operation, and the cross couple display of FIG. 2 is easy to understand for the explanation of the circuit area and the like.
  • the inverter circuits 14 and 16 include FETs m1 to m3 and m1a to m3a.
  • FETs m1, m2 and m3a are N-channel MOSFETs
  • FETs m1a, m2a and m3 are P-channel MOSFETs.
  • FETs m1, m2, m1a and m2a are connected in series between the ground line 15b and the power supply line 15a (virtual power supply line).
  • the gates of the FETs m1, m2, m1a and m2a are connected to the input node N1.
  • An output node N2 is located between the FETs m2 and m2a.
  • FETs m1 and m2 are drivers for inverter circuits 14 and 16, and FETs m1a and m2a are loads.
  • the FET m3 is connected between the intermediate node N3 and the bias node N4 between the FETs m1 and m2, and the FET m3a is connected between the intermediate node N3a and the bias node N4a between the FETs m1a and m2a.
  • the gates of the FETs m3 and m3a are connected to the input node N1.
  • the FETs m3 and m3a are feedback transistors FBTr.
  • the storage nodes Q1 and Q2 are connected to the bit lines BL and BLB via FETm5, respectively.
  • the gate of FETm5 is connected to the word line WL.
  • the FET m5 is an N-channel FET and is a pass transistor.
  • the driver 26 includes inverters 27a and 27b.
  • the inverter 27a outputs a signal VFN in which the control signal VCTRL is inverted to the bias node N4, and the inverter 27b outputs a signal VFP in which the signal VFN is inverted to the bias node N4a.
  • the power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage V VDD and supplies the voltage to the power supply line 15a.
  • the power switch 30 switches the virtual power supply voltage V VDD by a control signal from a control circuit (not shown).
  • the modes of the inverter circuits 14 and 16 can be changed to ST mode and BI mode by the control signal VCTRL.
  • V VDDH high level
  • VND low level
  • the inverter circuits 14 and 16 are in ST mode.
  • the ST mode is a mode in which the transmission characteristics of the inverter circuits 14 and 16 have hysteresis
  • the BI mode is a mode in which the transmission characteristics of the inverter circuits 14 and 16 have substantially no hysteresis.
  • V VDD-VGND applied to the inverter circuits 14 and 16
  • a normal voltage for example, 1.2V
  • the leakage current becomes large.
  • the BI mode the leakage current is smaller than that in the ST mode even when the voltage V VDD-VGND is used as a normal voltage.
  • substantially no hysteresis means that there is no intentional hysteresis as in the ST mode, and it is allowed to have an unintended hysteresis.
  • the memory cell 10 functions as a normal SRAM cell.
  • the bistable circuit 12 holds data even if the voltage (V VDD-VGND) is set to 0.2 V, for example, and an ultralow voltage (ULV).
  • Table 1 is a table showing the states in Comparative Example 1.
  • the state of reading and writing data to the memory cell 10 is the read / write state.
  • the control signal VCTRL is at high level H.
  • the inverter circuits 14 and 16 are in BI mode.
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDH (for example, 1.2V).
  • the voltage (V VDD-VGND) becomes VH (for example, 1.2V).
  • the state of holding data is the VDD retention state.
  • the control signal VCTRL is at high level H, and the inverter circuits 14 and 16 are in BI mode.
  • the virtual power supply voltage V VDD is V VDDH (for example, 1.2V)
  • the voltage (V VDD-VGND) is VH (for example, 1.2V).
  • the voltage VWL of the word line WL is low level (eg 0V) and the FETm5 is off because no reading or writing is performed.
  • the state in which the data in the memory cell 10 is held at an ultra-low voltage is the ULV retention state.
  • the control signal VCTRL is at low level L, and the inverter circuits 14 and 16 are in ST mode.
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDL (for example, 0.2 V).
  • the voltage (V VDD-VGND) is VL (for example, 0.2V) lower than VH.
  • the voltage VWL is low level (eg 0V) and the FETm5 is off.
  • FIG. 3 and 4 are circuit diagrams of the memory cell 10 in Comparative Example 2.
  • FIG. 3 is a circuit diagram of a loop display
  • FIG. 4 is a circuit diagram of a cross couple display.
  • Table 2 is a table showing the states in Comparative Example 2.
  • the voltage of the bias node N4 is constant at VFN (for example, 0.2V) regardless of the mode.
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDH (for example, 1.2 V) by a control signal from a control circuit (not shown).
  • the virtual power supply voltage (V VDD-VGND) applied to the bistable circuit 12 is VH (for example, 1.2V).
  • the inverter circuits 14 and 16 are in the BI mode.
  • the voltage VWL of the word line WL is at a high level (eg 1.2V).
  • the virtual power supply voltage V VDD is V VDDH (for example, 1.2V)
  • the voltage (V VDD-VGND) is VH (for example, 1.2V)
  • the inverter circuits 14 and 16 are in BI mode.
  • the voltage VWL of the word line WL is low level (0V).
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDL (for example, 0.2V).
  • the voltage (V VDD-VGND) is VL (for example, 0.2V) lower than VH.
  • V VDD-VGND the voltage (V VDD-VGND) is VL (for example, 0.2V) lower than VH.
  • the inverter circuits 14 and 16 are in the ST mode.
  • the voltage VWL is low level (eg 0V). Similar to Comparative Example 1, power consumption can be suppressed in the ULV retention state.
  • a type in which FET m3 is provided as a feedback transistor FBTr between FETs m1 and m2 of an N-type channel is called a pull-down feedback PDFB.
  • a type in which a FET m3a is provided as a feedback transistor FBTr between the FETs m1a and m2a of the P-type channel is called a pull-up type feedback PUFB.
  • a type in which both FETs m3 and m3a are provided is called a pull-up / pull-down type feedback PUPDFB.
  • Comparative Example 1 is PUPDFB
  • Comparative Example 2 is PDFB.
  • the FET to which the FBTr and the FBTr are connected is a different conductive type channel, it is called a different conductive type channel FBTr.
  • the FET m3 which is an FBTr is a P-type channel
  • the FETs m1 and m2 to which the FET m3 is connected are an N-type channel. Therefore, when the FBTr is a P-type channel in the PDFB, it is a different conductive type channel FBTr.
  • the FBTr is an N-type channel in PUFB, it is a different conductive type channel FBTr.
  • the FET to which the FBTr and the FBTr are connected is the same conductive channel, it is called the same conductive channel FBTr.
  • the FBTr is an N-type channel in PDFB, and when the FBTr is a P-type channel in PUFB, it is the same conductive type channel FBTr.
  • the gate is connected to the input node of the same inverter circuit or the output node of the other inverter circuit. In the same conductive channel FBTr, the gate is connected to the output node of the same inverter circuit or the input node of the other inverter circuit. Comparative Examples 1 and 2 are different conductive channels FBTr. Patent Document 1 discloses the conductive channel FBTr.
  • a method in which a power switch 30 is provided between the power supply line 15a and the power supply 15c, the power switch 30 sets a virtual power supply voltage V VDD, and the voltage V VDD-VGND is used as the power supply voltage of the memory cell 10 is called a header PS.
  • a method in which a power switch 30 is provided between the ground wire 15b and the ground, the power switch 30 sets a virtual ground voltage VVGND, and VDD-VVGND is used as the power supply voltage of the memory cell 10 is called a footer PS.
  • a power switch 30 is provided both between the power supply line 15a and the power supply 15c and between the ground line 15b and the ground.
  • a method in which the power supply voltage is 10 is called dual PS. Comparative Examples 1 and 2 are header PS.
  • a method in which a driver 26 is provided and high level and low level are applied to bias nodes N4 and N4a by a control signal VCTRL to switch between ST mode and BI mode is called type 2.
  • a method in which the bias node N4 is set to a constant voltage (constant bias) without providing the driver 26 is called type 1.
  • Comparative Example 1 is type 2
  • Comparative Example 2 is type 1.
  • Comparative Example 1 is PUPDFB, heteroconductive channel FBTr, header PS, and type 2.
  • Comparative Example 2 is a PDFB, a heteroconductive channel FBTr, a header PS, and a type 1.
  • the different conductive type channel FBTr improves the operation stability (for example, noise margin) of the bistable circuit 12 in the ULV retention state as compared with the same conductive type channel FBTr.
  • the FET m3 is a P-type channel (that is, a different conductive channel) as in Comparative Example 2, for example, when the storage nodes Q1 and Q2 are at low level and high level, respectively, the FET m3 of the inverter circuit 14 is turned on.
  • the intermediate node N3 is charged from the bias node N4 whose voltage is VFN. Since the FET m3 is a P-type channel and a sufficiently low voltage is applied to the source and drain at the gate of the FET m3, the intermediate node N3 can be pulled up to the VFN. As a result, the feedback effect of FETm3 is sufficiently generated. Therefore, the operational stability of the bistable circuit in the ULV retention state can be improved.
  • Comparative Example 2 is Type 1.
  • VFN has a constant bias of about V VDDL.
  • V VDDH is applied to the power supply line 15a
  • the inverter circuits 14 and 16 are in BI mode because the VFN is sufficiently lower than V VDDH.
  • V VDDL is applied to the power supply line 15a
  • the inverter circuits 14 and 16 are in the ST mode because the VFN is higher than the VGND and equal to or close to the V VDDL.
  • the driver 26 is not required for the PDFB / header PS.
  • the PUFB / footer PS does not require the driver 26.
  • Comparative Example 1 the number of transistors in the memory cell 10 is 14, and the driver 26 is provided. As a result, as shown in FIG. 2, the area of the circuit becomes large. Since feedback is applied by both FBTrs (FET m3 and m3a) on the pull-up side with respect to the inverter circuits 14 and 16 and the pull-down side with respect to the inverter circuits 14 and 16, the noise margin in the ULV retention state becomes large. As a result, V VDDL can be set to, for example, 0.15 V, and there is a possibility that power consumption can be suppressed.
  • Comparative Example 2 the number of transistors in the memory cell 10 is 10, and the driver 26 is unnecessary. As a result, the area of the circuit can be reduced as shown in FIG. However, since feedback is applied only by the FBTr (FETm3) on the pull-down side, the noise margin in the ULV retention state is smaller than that in Comparative Example 1. As a result, V VDDL becomes, for example, 0.2V. Therefore, the power consumption is larger than that of Comparative Example 1.
  • Example 1 is an example of PDFB, heteroconductive channel FBTr, header PS, and type 1.
  • the load FET m1a of Comparative Example 2 and the pass transistor FET m5 are regarded as one FET m4.
  • the number of transistors in the memory cell 10 can be reduced to 8 as compared with Comparative Example 2.
  • the noise margin in ULV retention can be increased.
  • FIG. 5 and 6 are circuit diagrams of memory cells according to the first embodiment.
  • FIG. 5 is a circuit diagram of a loop display
  • FIG. 6 is a circuit diagram of a cross couple display.
  • the memory cell 10 mainly includes inverter circuits 14 and 16.
  • the inverter circuits 14 and 16 are connected in a loop to form a bistable circuit 12.
  • the inverter circuits 14 and 16 include FETs m1 to m4, respectively.
  • FETs m1 and m2 are N-channel MOSFETs
  • FETs m3 and m4 are P-channel MOSFETs.
  • FETs m1 to m4 are, for example, normal off type transistors.
  • FETm1 the source is connected to the ground wire 15b to which the ground voltage VGND is applied, the drain is connected to the intermediate node N3, and the gate is connected to the input node N1.
  • FETm2 the source is connected to the intermediate node N3, the drain is connected to the output node N2, and the gate is connected to the input node N1.
  • FETs m1 and m2 are drivers.
  • FETm3 one of the source and drain is connected to the intermediate node N3, the other of the source and drain is connected to the bias node N4, and the gate is connected to the input node N1.
  • FETm3 is a feedback transistor FBTr.
  • FETm4 one of the source and drain is connected to the output node N2, the other of the source and drain is connected to the control line CTRL1 or CTRL2, and the gate is connected to the word line WL.
  • the FETm4 functions as a pass transistor in the read / write state and as a load in the VDD retention state and the ULV retention state.
  • the input node N1 of the inverter circuit 14 and the output node N2 of the inverter circuit 16 are connected to the storage node Q1, and the input node N1 of the inverter circuit 16 and the output node N2 of the inverter circuit 14 are connected to the storage node Q2.
  • Storage nodes Q1 and Q2 are complementary nodes.
  • the storage node Q1 is connected to the control line CTRL1 via the FET m4 of the inverter circuit 16, and the storage node Q2 is connected to the control line CTRL2 via the FET m4 of the inverter circuit 14.
  • the selection circuit 32 connects the control line CTRL1 to either the bit line BL or the power supply line 15a (virtual power supply line).
  • the selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the power supply line 15a.
  • the power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage V VDD and supplies the voltage to the power supply line 15a.
  • FIG. 7A is a block diagram of the memory array according to the first embodiment.
  • the memory array 22 is divided into a plurality of blocks 24 having memory cells 10.
  • the number of blocks 24 can be appropriately designed.
  • a plurality of memory cells 10 are arranged in an n-column matrix in the memory array 22.
  • the word line WL extends in the row direction
  • the control lines CTRL1 and CTRL2 extend in the column direction.
  • a word line WL, a control line CTRL1 and a control line CTRL2 are connected to each memory cell 10.
  • the control lines CTRL1 and CTRL2 in rows 1 to n are shown as control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.
  • a control circuit 28, a power switch 30, and a peripheral circuit 38 are provided corresponding to the memory array 22.
  • the control circuit 28 controls the power switch 30 and the peripheral circuit 38.
  • the power switch 30 outputs the virtual power supply voltage V VDD obtained from the voltage VDD of the power supply 15c, for example, by a voltage dividing circuit, according to the control signal from the control circuit 28.
  • the voltage V VDD-VGND becomes the voltage applied to the bistable circuit 12.
  • the peripheral circuit 38 includes a WL decoder 31, a selection circuit 32b, a precharge circuit 33, and a read / write circuit 34.
  • FIG. 7A the selection circuits 32 and 32a of FIGS. 5 and 6 will be described as the selection circuits 32b. The same is true for the following similar figures.
  • the selection circuit 32b switches from the control lines CTRL11 and CTRL21 to connect the power supply line 15a to the CTRL1n and CTRL2n.
  • the selection circuit 32b switches the control lines CTRL11 and CTRL21 to connect the bit lines BL1 and BLB1 to BLn and BLBn to CTRL1n and CTRL2n, respectively.
  • the WL decoder 31 selects the word line WL based on the row address.
  • the column address is input to the read / write circuit 34.
  • the read / write circuit 34 selects the bit lines BL and BLB corresponding to the column selected from the bit lines BL1 and BLB1 to BLn and BLBn based on the column address.
  • the precharge circuit 33 precharges the bit lines BL and BLB.
  • the read / write circuit 34 writes data to the bistable circuit 12 of the selected memory cell 10 or reads data from the bistable circuit 12 and outputs the data to the bus 25.
  • FIG. 7B is a diagram showing a power switch and a selection circuit according to the first embodiment.
  • the power switch 30 includes FET PS1 and PS2.
  • FET PS1 and PS2 are P-channel FETs.
  • the FETPS1 is connected between the power supply 15cH and the power supply line 15a
  • the FETPS2 is connected between the power supply 15cL and the power supply line 15a.
  • Power supply voltages VDDH and VDDL are supplied to the power supply 15 cH and the power supply 15 cL, respectively.
  • Signals VPS1 and VPS2 are input to the gates of FETPS1 and PS2, respectively.
  • FETPS1 and PS2 are turned on and off, respectively, and the virtual power supply voltage V VDD becomes VDDH.
  • the virtual power supply voltage VVDD becomes VDDH in the read / write state and the VDD retention state, and the voltage V VDD-VGND is, for example, 1.2V.
  • FETPS1 and PS2 are turned off and on, respectively, and the virtual power supply voltage V VDD is VDDL.
  • the virtual power supply voltage V VDD becomes VDDL in the ULV retention state, and the voltage V VDD-VGND is, for example, 0.2V.
  • both the signals VPS1 and VPS2 are at high level, both FETPS1 and PS2 are turned off and the virtual power supply voltage V VDD is cut off.
  • the virtual power supply voltage V VDD is cut off in the shutdown state.
  • a precharge / selection circuit 33a is provided between the power supply line 15a and the control lines CTRL1 and CTRL2.
  • the precharge / selection circuit 33a includes FETs M10 to M12.
  • the FET M10 is connected between the power supply line 15a and the control line CTRL1.
  • the FET M11 is connected between the power supply line 15a and the control line CTRL2.
  • the FET M12 is connected between the control lines CTRL1 and CTRL2.
  • FETs M10 to M12 are P-channel FETs.
  • a selection signal Self is input to the gates of FETs M10 to M12.
  • a selection circuit 32b is provided between the control lines CTRL1 and CTRL2 and the bit lines BL and BLB connected to the read / write circuit 34.
  • the selection circuit 32b includes transfer gates M13 and M14.
  • the transfer gate M13 is connected between the bit line BL and the control line CTRL1.
  • the transfer gate M14 is connected between the bit line BLB and the control line CTRL2.
  • the selection signals Sel'and the complementary signal SelB'of the selection signals Sel' are input to the transfer gates M13 and M14.
  • FIG. 7C is a block diagram showing another example of the memory array in the first embodiment.
  • the precharge / selection circuit 33a is provided between the power switch 30 and the memory array 22.
  • the precharge / selection circuit 33a includes FETs M11-13 of FIG. 7B, and the selection circuit 32b includes transfer gates M13 and M14 of FIG. 7B.
  • the FETs M10 to M12 When the selection signal Self is at a low level, the FETs M10 to M12 are turned on, and the virtual power supply voltage V VDD is supplied to the control lines CTRL1 and CTRL2.
  • the selection signal Self When the selection signal Self is at a high level, the FETs M10 to M12 are turned off. When the FETs M10 to M12 are off and the selection signal Self'is at a high level, the transfer gates M13 and M14 are on and the control lines CTRL1 and CTRL2 function as bit lines BL and BLB. When the FETs M10 to M12 are on and the selection signal Self'is low level, the transfer gates M13 and M14 are turned off and the control lines CTRL1 and CTRL2 are disconnected from the bit lines BL and BLB.
  • the precharge / selection circuit 33a may be connected to the ends of the control lines CTRL1 and CTRL2, and the selection circuit 32b may be connected to the other ends of the control lines CTRL1 and CTRL2.
  • the control circuit 28 of the electronic circuit of FIGS. 7A and 7C controls the power switch 30, and in the ULV retention state in which the bistability circuit 12 holds the data, the voltage VL (0) of the voltage V VDD-VGND in Table 3 of the first embodiment. .2V) is lower than the voltage VH (1.2V) in the read / write state (second state). As a result, the power consumption in the ULV retention state can be suppressed.
  • Table 3 is a table showing the states in Example 1.
  • Bias node N4 is a constant voltage VFN (for example, 0.2V).
  • the selection circuit 32b connects the bit line BL (bit line BL and BLB in FIGS. 5 and 6) to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6).
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDH (for example, 1.2V).
  • the voltage V VDD-VGND becomes VH (for example, 1.2V).
  • the bit wires BL and BLB are substantially V VDDH.
  • one of the bit lines BL and BLB is approximately V VDDH, and the other is approximately VGND.
  • the high level of the storage nodes Q1 and Q2 is approximately V VDDH, and the low level is approximately VGND.
  • the inverter circuits 14 and 16 are in BI mode.
  • the voltage V1 is a voltage at which the FET m4 is turned on at both the high level and the low level of the storage nodes Q1 and Q2. As a result, data can be read and written from the memory cell 10.
  • the selection circuit 32b connects the power supply line 15a to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6).
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDH (for example, 1.2V).
  • V VDD-VGND becomes VH (for example, 1.2V).
  • the inverter circuits 14 and 16 are in BI mode.
  • the voltage VWL of the word line WL be the voltage V2 (for example, 1.1V). Since the voltage V2 is slightly lower than V VDDH, the FET m4 is slightly turned on when the storage nodes Q1 and Q2 are at both high and low levels. As a result, the FET m4 functions as a load for the inverter circuits 14 and 16. In the VDD retention state, the data of the bistable circuit 12 is held.
  • the selection circuit 32b connects the power supply line 15a to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6).
  • the power switch 30 sets the virtual power supply voltage V VDD to V VDDL (for example, 0.2 V).
  • V VDD-VGND becomes VL (for example, 0.2V).
  • the inverter circuits 14 and 16 are in ST mode.
  • the voltage VWL of the word line WL be the voltage V3 (for example, 0.2V).
  • V3 the voltage V3
  • the FET m4 is turned off at both the high level and the low level of the storage nodes Q1 and Q2, but the leakage current of the FET m4 causes the FET m4 to function as a load of the inverter circuits 14 and 16.
  • the data of the bistable circuit 12 is held at an ultra-low voltage. As a result, power consumption due to leakage current can be suppressed.
  • Simulation 1 is a simulation of SNM (Static Noise Margin) and standby power at the time of reading in the VDD retention state and the read / write state.
  • Example 1 Comparative Example 2
  • Comparative Example 3 which is a SRAM cell (6T) using 6 transistors.
  • the simulation conditions are as follows.
  • each FET in the first embodiment is as follows.
  • FET m1, m2 driver: 100 nm / 60 nm
  • FETm3 feedback transistor
  • FETm4 pass transistor / load
  • V VDDH 1.2V
  • VGND 0V
  • the channel width W / length L of each FET in Comparative Example 2 is as follows.
  • Each voltage in Comparative Example 2 is as follows.
  • VFN 0.2V
  • the channel width W / length L of each FET in Comparative Example 3 is as follows.
  • Pass transistor 100nm / 60nm
  • Each voltage in Example 3 is as follows.
  • the virtual power supply voltage V VDD is supplied to the memory cell 10 from the control lines CTRL1 and CTRL2. Therefore, the noise margin and the standby power are determined by the size of the FET m4 and the voltage VWL of the word line WL in the VDD retention state. Further, since VFN is set to a constant bias, feedback is applied even in BI mode, although it is weaker than in ST mode due to FETm3. Therefore, the noise margin can be designed according to the size of the FET m3.
  • the size of FETm4 (channel width WLP) and the size of FETm3 (channel width WFB) were changed, and SNM (Static Noise Margin) and standby power in the VDD retention state were simulated.
  • the standby power corresponds to the total leakage current of each FET in the state of holding data.
  • the voltage VWL of the word line WL was changed, and the SNM and standby power in the VDD retention state were simulated.
  • the SNM has a noise margin, and if the SNM is small, the data of the bistable circuit 12 is likely to be inverted due to noise or the like, and if the SNM is large, the data of the bistable circuit 12 is difficult to be inverted due to noise or the like.
  • the goal was to set the SNM to 80 mV or more as an index of the SNM.
  • the TT of the SNM is the SNM when the threshold voltages of the PFET and the NFET are typical.
  • the FF of the SNM is the SNM when the threshold voltages of the PFET and the NFET are both shifted by 3 ⁇ to the Fast (F) side (lower side) from the Typical value due to the process fluctuation.
  • the SS of the SNM is the SNM when the threshold voltages of both the PFET and the NFET are deviated by 3 ⁇ toward the Slow (S) side (higher side) from the Typical value due to process fluctuation.
  • the FS and SF of the SNM are SNMs when one of the threshold voltages of the PFET and the NFET is deviated from the Typical value to the F side and the other is deviated from the Typical value to the S side by 3 ⁇ . If the SNMs of TT, FF, SS, FS and SF are secured, the SNMs can be secured even if the threshold voltages of the PFETs and NFETs vary within the range of ⁇ 3 ⁇ . In Comparative Example 3, the channel width W of the pass transistor is constant.
  • WLP is changed from 100 nm to 300 nm.
  • the larger the WLP the larger the SNM.
  • all SNMs are 80 mV or more.
  • the standby power of Example 1 is smaller than that of Comparative Example 3 (6T) when the WLP is 110 nm or less. Therefore, WLP is set to 110 nm.
  • 9 (a) and 9 (b) are diagrams showing SNM and standby power for VWL in the VDD retention state and read / write state leads of Example 1 and Comparative Example 3.
  • VWL is changed from 0 V to 1.2 V.
  • the smaller the VWL the larger the standby power.
  • VWL is lowered to turn on FETm4.
  • SNM is large. As shown in FIG. 9A, when the VWL is 0.25 V or more, all SNMs are 80 mV or more. Therefore, VWL was set to 0.25V.
  • Example 1 Comparative Examples 2 and 3, SNM in the read / write state and the VDD retention state was simulated.
  • VWL in the VDD retention state was 1.1 V
  • VWL in the read / write state was 0.25 V.
  • FIG. 10 (a) to 10 (c) are diagrams showing SNMs in the VDD retention state and read / write state of Examples 1, Comparative Examples 2 and 3.
  • FIG. 10 (a) shows the SNM in the VDD retention state
  • FIG. 10 (b) shows the SNM in the read / write state when reading
  • FIG. 10 (c) shows the SNM in the read / write state when writing. be.
  • the SNM of Example 1 is smaller than Comparative Examples 2 and 3, but is larger than 80 mV in all SNMs.
  • the SNM of Example 1 in the lead, is substantially the same as Comparative Examples 2 and 3, and is greater than 80 mV in all SNMs.
  • the SNM of Example 1 in light, is larger than Comparative Examples 2 and 3, and is greater than 80 mV in all SNMs. As described above, in Example 1, it is larger than 80 mV in all SNMs. Also, the SNM of TT is larger than 100 mV.
  • a sufficient noise margin can be secured in the read / write state and the VDD retention state.
  • the optimization of VWL in FIGS. 9 (a) and 9 (b) is performed for leads in the VDD retention state and the read / write state, but as shown in FIGS. 10 (a) to 10 (c), SNM can also be increased in light.
  • Simulation 2 is a simulation of the transmission characteristics of the inverter circuits 14 and 16 in the ULV retention state, the butterfly curve of the bistable circuit 12, the SNM, and the standby power.
  • the channel width W / length L and each voltage of each FET not specifically described are the same as in simulation 1.
  • V VDD 0.2V.
  • Example 1 the transmission characteristics of the inverter circuits 14 and 16 in the ULV retention state were simulated by changing the voltage VWL of the word line WL.
  • FIG. 11 is a diagram showing the transmission characteristics of the inverter circuit in the ULV retention state of the first embodiment, and shows the output voltage Vout (output node N2) with respect to the input voltage Vin (voltage of the input node N1) of the inverter circuits 14 and 16. It is a figure.
  • the threshold voltage at which the output voltage Vout shifts from the high level to the low level shifts to the higher Vin.
  • the threshold voltage at which the output voltage Vout shifts from the low level to the high level shifts to the lower Vin.
  • the higher the VWL the lower the threshold voltage shifts to the lower Vin.
  • FIGS. 12 (a) and 12 (b) are circuit diagrams of the bistable circuit in the first embodiment.
  • the circuit of the bistable circuit 12 is a circuit diagram in the ULV retention state in FIGS. 5 and 6, and is displayed so that the principle can be easily understood.
  • FIGS. 12A and 12B the input voltage Vin and the output voltage Vout of the inverter circuit 14 will be described.
  • the forward sweep will be described with reference to FIG. 12 (a).
  • the input voltage Vin is at a low level (eg 0V) and the output voltage Vout is at a high level (eg 0.2V).
  • FETs m1 and m2 are off, and FETm3 is on.
  • VWL is lower than 0.2V, FETm4 is turned on.
  • the output node N2 is charged from the V VDDL of the control line CTRL1 by the leak current or the on current of the FET m4 as shown by the dotted arrow 92, and the intermediate node N3 is charged by the VFN of the bias node N4 as shown by the dotted arrow 93. ..
  • the output node N2 When the input voltage Vin becomes high, in order to lower the output voltage Vout, the output node N2 is discharged to the intermediate node N3 as shown by the solid arrow 90. However, unless the intermediate node N3 is discharged to the ground line 15b as shown by the solid line arrow 91, the output node N2 cannot be discharged to the intermediate node N3. Therefore, since the output node N2 is discharged after the intermediate node N3 is discharged, the threshold voltage at which the output voltage Vout becomes a low level shifts to the higher Vin.
  • the backward sweep will be described with reference to FIG. 12 (b).
  • the input voltage Vin is at a high level (eg 0.2V) and the output voltage Vout is at a low level (eg 0V).
  • FETs m1 and m2 are on, and FETs m3 and m4 are off. Therefore, the intermediate node N3 is discharged to the ground line 15b as shown by the dotted arrow 95.
  • VWL is lower than 0.2V, FETm4 turns on weakly. Since the discharge via the FET m2 of the dotted arrow 94 is faster than the charge via the FET m4 of the dotted arrow 96, the output node N2 is discharged to the intermediate node N3.
  • the FET m1 When the input voltage Vin becomes low, the FET m1 is turned off and the FET m3 is turned on, so that the intermediate node N3 is charged by the VFN of the bias node N4 as shown by the solid arrow 97.
  • the output node N2 When the FET m2 is off and the FET m4 is off or weakly on, the output node N2 is charged from the V VDDL of the control line CTRL1 as shown by the dotted arrow 96.
  • the output node N2 since the output node N2 is charged with a current close to the off current of the FET m4, the charging depends on the VWL. As a result, the threshold voltage at which the output voltage Vout becomes a high level shifts to the lower side of Vin when the VWL is increased.
  • VWL is applied to the gate of FETm4. Therefore, the magnitude of the current indicated by the dotted arrow 96 depends on the VWL.
  • the current of the FET m4 is small, so that the threshold voltage shifts according to the lower Vin.
  • FIG. 13 (a) and 13 (b) are diagrams showing the butterfly curves of the bistable circuit in the ULV retention state of Example 1, Comparative Examples 2 and 3.
  • FIG. 13A shows an operating point when Q1 is at a low level and Q2 is at a high level
  • FIG. 13B shows an operating point when Q1 is at a high level and Q2 is at a low level.
  • the butterfly curve opening (love) is narrow and the noise margin is small.
  • the opening on the operating point side is widened and the noise margin is large.
  • the opening on the operating point side is wider than that of the comparative example 2, and the noise margin is further larger than that of the comparative example 2.
  • FIG. 14A is a diagram showing SNM in the ULV retention state of Example 1, Comparative Examples 2 and 3. As shown in FIG. 14A, in Comparative Example 3, each SNM is smaller than 80 mV and the noise margin is small. In Comparative Example 2, each SNM is 80 mV or more, and the noise margin is large. In Example 1, each SNM is 130 mV or more, and the noise margin is larger than that of Comparative Example 2. Assuming that the practical SNM is 80 mV, V VDD can be made lower than 0.2 V in the first embodiment. When V VDD is 0.2 V, the SNM is 130 mV or more, and the bistable circuit 12 is more stable than when V VDD is lower than 0.2 V.
  • V VDD was changed and SNM and standby power were simulated.
  • FIG. 14B is a diagram showing SNM and standby power with respect to V VDD in the ULV retention state of Example 1.
  • V VDD is changed from 0.1 to 0.2 V.
  • SNM becomes large and standby power becomes large.
  • V VDD is 0.15 V or more, all SNMs are 80 mV or more. Therefore, V VDD (that is, V VDDL) in the ULV retention state can be set to 0.15 V.
  • Example 1 For Example 1 and Comparative Example 3, the standby power for each V VDD was simulated.
  • the reduction rate of the standby power at this time is 7%.
  • the standby power reduction rate is 95%.
  • V VDD 0.15V
  • the reduction rate of the standby power is 97%.
  • Comparative Example 2 the number of transistors in the memory cell 10 is 10, but in the first embodiment, the number of transistors in the memory cell 10 can be reduced to eight. As a result, the circuit area can be suppressed as in the comparison between FIGS. 4 and 6. Further, as shown in FIG. 14A, the noise margin in the ULV retention state can be made larger than that in Comparative Example 2. Assuming that the noise margin is the same as that of Comparative Example 2, V VDDL can be made lower than that of Comparative Example 2. As a result, the standby power can be further suppressed.
  • Modification 1 of Example 1 is an example of PUFB, a heteroconductive channel FBTr, a footer PS, and type 1.
  • 16 and 17 are circuit diagrams of the memory cell 10 in the first modification of the first embodiment.
  • FIG. 16 is a circuit diagram of a loop display
  • FIG. 17 is a circuit diagram of a cross couple display.
  • the VSS retention state is not the VDD retention state, but here, it is referred to as the VDD retention state in order to match with the first embodiment.
  • the inverter circuits 14 and 16 include FETs m1a to m4a, respectively.
  • FETs m1a and m2a are P-channel MOSFETs
  • FETs m3a and m4a are N-channel MOSFETs.
  • the source is connected to the power supply line 15a to which the power supply voltage VDD is applied.
  • the selection circuit 32 connects the control line CTRL1 to either the bit line BL or the ground line 15b (virtual ground line).
  • the selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the ground line 15b.
  • the power switch (PS) 30 converts the voltage VGND of the ground 15d into a virtual ground voltage VVGND and supplies it to the ground wire 15b.
  • a constant bias VFP is applied to the bias node N4.
  • Other circuit configurations are the same as the circuits in which FETs m1 to m4 in FIGS. 5 and 6 of Example 1 are replaced with FETs m1a to m4a, respectively.
  • Table 4 is a table showing the states in the first modification of the first embodiment.
  • the bias node N4 has a constant voltage VFP (for example, 1.0 V).
  • VFP constant voltage
  • the selection circuits 32 and 32a connect the bit lines BL and BLB to the control lines CTRL1 and CTRL2, respectively.
  • the power switch 30 sets the virtual ground voltage VVGND to VVGNDL (for example, 0V).
  • the virtual power supply voltage VDD-VVGND applied to the bistable circuit 12 is VH (for example, 1.2V).
  • the bit wires BL and BLB can be made almost VVGNDL.
  • one of the bit lines BL and BLB can be made almost VVGNDL, and the other can be made almost VDD.
  • the high level of the storage nodes Q1 and Q2 is approximately VDD, and the low level is approximately VVGNDL.
  • the inverter circuits 14 and 16 are in BI mode. Let the voltage VWL of the word line WL of the memory cell 10 to be read or written be the voltage V1 (for example, 0.9V).
  • the selection circuits 32 and 32a connect the ground line 15b to the control lines CTRL1 and CTRL2.
  • the power switch 30 sets the virtual ground voltage VVGND to VVGNDL (for example, 0V).
  • the voltage VDD-VVGND becomes VH (for example, 1.2V).
  • the inverter circuits 14 and 16 are in BI mode. Let the voltage VWL of the word line WL be the voltage V2 (for example, 0.1V).
  • the selection circuits 32 and 32a connect the ground line 15b to the control lines CTRL1 and CTRL2.
  • the power switch 30 sets the virtual ground voltage VVGND to VVGNDH (for example, 1.0 V).
  • the voltage VDD-VVGND becomes VL (for example, 0.2V).
  • the inverter circuits 14 and 16 are in ST mode. Let the voltage VWL of the word line WL be the voltage V3 (for example, 1.0V).
  • the data of the bistable circuit 12 is held at an ultra-low voltage. As a result, power consumption due to leakage current can be suppressed.
  • Modification 2 of Example 1 is an example of PDFB, the same conductive channel FBTr, header PS, and type 1.
  • 18 and 19 are circuit diagrams of the memory cell 10 in the second modification of the first embodiment.
  • FIG. 18 is a circuit diagram of a loop display
  • FIG. 19 is a circuit diagram of a cross couple display.
  • the FET m3 is an N-channel FET in the inverter circuits 14 and 16.
  • the gate of the FET m3 of the inverter circuit 14 is connected to the output node N2 of the inverter circuit 14 or the input node N1 of the inverter circuit 16, and the gate of the FET m3 of the inverter circuit 16 is the output node N2 of the inverter circuit 16 or the input of the inverter circuit 14. It is connected to node N1.
  • Other circuit configurations are the same as those in FIGS. 5 and 6 of the first embodiment. Similar to FIG.
  • a part of the selection circuits 32 and 32a is a precharge / selection circuit 33a provided between the power switch 30 and the control lines CTRL1 and CTRL2, and other of the selection circuits 32 and 32a.
  • a part may be a selection circuit 32 provided between the read / write circuit 34 and the control lines CTRL1 and CTRL2.
  • the butterfly curve in the ULV retention state of the modification 2 of the first embodiment was simulated.
  • the simulation conditions are almost the same as the simulation 2 of the first embodiment.
  • V VDD was set to 0.2V.
  • FIG. 20 is a diagram showing a butterfly curve of the bistable circuit in the ULV retention state of Example 1 and its modified example 2.
  • the operating point is when Q1 is at a low level and Q2 is at a high level.
  • the butterfly curve of the first embodiment is the same as that of FIG. 13 (a).
  • the opening on the operating point side is smaller than the opening on the operating point side of the first embodiment.
  • the feedback transistor (FETm3) is the same conductive type channel as the FETs m1 and m3, the noise margin is smaller than that of the different conductive type channel.
  • the opening on the operating point side is wider than that of Comparative Example 3 in FIG. 13 (a). Therefore, the power consumption can be suppressed by ULV retention as compared with Comparative Example 3. Further, the circuit area can be reduced as compared with Comparative Example 2.
  • the source is the ground wire 15b (or It is connected to the power line 15a)
  • the drain is connected to the intermediate node N3
  • the gate is connected to the input node N1.
  • the ground wire 15b corresponds to the power supply line
  • the power supply line 15a corresponds to the power supply line.
  • FETm2 In FETm2 (second FET) (or FETm2a), the source is connected to the intermediate node N3 and the drain is connected to the output node N2.
  • FETm3 third FET
  • one of the source and drain is connected to the intermediate node N3, and the other of the source and drain is connected to the bias node N4.
  • FET m4 fourth FET
  • one of the source and drain is connected to the output node N2, and the other of the source and drain is connected to the control line CTRL1 or CTRL2.
  • the conductive type (second conductive type) of the FET m4 (or m4a) is opposite to the conductive type (first conductive type) of the FETs m1 and m2 (or FETs m1a and m2a).
  • the bistable circuit 12 is formed.
  • the gate of the FET m4 (or FET m4a) of the inverter circuits 14 and 16 is connected to the word line WL.
  • the gate of the FET m3 (or FET m3a) of the inverter circuit 14 is connected to any one of the input node N1 and the output node N2 of the inverter circuit 14, the input node N1 and the output node N2 of the inverter circuit 16.
  • the gate of the FET m3 (or FET m3a) of the inverter circuit 16 is connected to any one of the input node N1 and the output node N2 of the inverter circuit 16, the input node N1 and the output node N2 of the inverter circuit 14.
  • the load of the inverter circuits 14 and 16 and the pass transistor can be shared by the FET m4 (or FET m4a). Therefore, the circuit area can be reduced as compared with Comparative Example 2. Further, the FET m3 (or FET m3a), which is an FBTr, makes the noise margin in the ULV retention state wider than that in Comparative Example 3. Therefore, the power consumption can be reduced.
  • the FET m3 (or FET m3a) is a second conductive channel opposite to the first conductive channel of the FETs m1 and m2 (or FET m1a and m2a). That is, FBTr is a heteroconductive channel.
  • the gate of the FET m3 (or FET m3a) of the inverter circuit 14 is connected to the input node N1 of the inverter circuit 14 or the output node N2 of the inverter circuit 16, and the gate of the FET m3 (or FET m3a) of the inverter circuit 16 is the inverter circuit. It is connected to the input node N1 of 16 or the output node N2 of the inverter circuit 14.
  • the noise margin in the ULV retention state can be made larger than that in Comparative Example 2 as in Simulation 2 of Example 1. Further, by lowering V VDDL, power consumption can be suppressed.
  • the FET m3 is the same first conductive channel as the FETs m1 and m2. That is, FBTr is the same conductive channel.
  • the gate of the FET m3 of the inverter circuit 14 is connected to the output node N2 of the inverter circuit 14 or the input node N1 of the inverter circuit 16, and the gate of the FET m3 of the inverter circuit 16 is the output node N2 of the inverter circuit 16 or the inverter circuit. It is connected to 14 input nodes N1.
  • the noise margin in the ULV retention state can be made larger than that in Comparative Example 3. Further, by lowering V VDDL, power consumption can be suppressed.
  • the control circuit 28 of the electronic circuit of FIGS. 7A and 7C controls the power switch 30 (power supply circuit), and in the ULV retention state (first state) in which the bistable circuit 12 holds data, Table 3 of Example 1 shows.
  • the voltage VL (first voltage) of the voltage V VDD-VGND and the VDD-VVGND of Table 4 of the modification 1 of the first embodiment is set to be lower than the voltage VH (second voltage) in the read / write state (second state). As a result, the power consumption in the ULV retention state can be suppressed.
  • the voltage VL corresponds to the voltage V VDD-VGND between the ground wire 15b in the ULV retention state and the control lines CTRL1 and CTRL2 in the first embodiment, and the power supply line 15a in the ULV retention state in the first modification of the first embodiment.
  • the voltage VH corresponds to the voltage between the storage nodes Q1 and Q2 in the read / write state.
  • the voltage VL may be smaller than the voltage VH, but the voltage VL is preferably 1/2 or less, more preferably 1/4 or less of the voltage VH, from the viewpoint of securing SNM and suppressing power consumption in the ULV retention state. 5/5 or less is more preferable, and 1/6 or less is more preferable. In particular, about 1/10 is preferable from the viewpoint of suppressing power consumption.
  • the voltage VL is greater than 0V.
  • the control circuit 28 controls the selection circuit 32b, and in the read / write state, connects the bit lines BL and BLB for reading or writing data from the bistable circuit 12 to the control lines CTRL1 and CTRL2. That is, the control lines CTRL1 and CTRL2 are set to the bit lines BL and BLB. As a result, data can be read or written from the bistable circuit 12 via the control lines CTRL1 and CTRL2.
  • the control circuit 28 makes the voltage VWL of the word line WL of the power switch 30 higher than the voltage of the ground line 15b.
  • FIG. 9A it is possible to prevent the SNM from becoming smaller than the target of 80 mV.
  • the control circuit 28 lowers the voltage VWL of the word line WL to be lower than the voltage VDD of the power supply line 15a.
  • the difference between the voltage of the ground line 15b (or the power supply line 15a) and VWL is preferably 1/10 or more of VH, more preferably 1/5 or more, and about 1/2 as shown in FIG. 9A. More preferred.
  • the difference between the voltage of the ground wire 15b (or the power supply line 15a) and the VWL is preferably 1/2 or less, more preferably 1/4 or less, and even more preferably 1/5 or less of the voltage VH.
  • the difference between the voltage of the ground wire 15b and the VWL is set to about 1/6 in order to give priority to the speed performance.
  • the voltage between the word line WL and the ground line 15b (or the power supply line 15a) is preferably 1/4 or more, more preferably 1/2 or more of the voltage VL.
  • the control circuit 28 makes the voltage between the word line WL and the ground line 15b smaller than VH.
  • VH 1.2V.
  • the control circuit 28 makes the voltage between the word line WL and the power supply line 15a smaller than VH.
  • the difference between the voltage of the ground line 15b (or the power supply line 15a) and VWL is preferably 49/50 or less of VH, more preferably 19/20 or less, and even more preferably 9/10 or less.
  • the difference between the voltage of the ground line 15b (or the power supply line 15a) and the VWL is preferably 1 ⁇ 2 or more, more preferably 3/4 or more, and even more preferably 4/5 or more of the voltage VH.
  • VFN or VFP which is a constant bias
  • VFN or VFP which is a constant bias
  • 21 (a) and 21 (b) are diagrams showing the voltages of the header PS / PDFB / type 1 and the footer PS / PUFB / type 1, respectively.
  • V VDDH and V VDDL with respect to VGND are shown in the vertical direction
  • VVGNDL and VVGNDH with respect to VDD are shown in the vertical direction.
  • V VDDH is supplied to the power supply line 15a and VGND is supplied to the ground line 15b in the read / write state and the VDD retention state.
  • the VFN is set to a constant bias of about V VDDL, the VFN is sufficiently lower than the V VDDH, so that the inverter circuits 14 and 16 are in the BI mode.
  • V VDDL is supplied to the power supply line 15a and VGND is supplied to the ground line 15b.
  • the VFN is set to about V VDDL, the inverter circuits 14 and 16 are in the ST mode because the VFN is higher than the VGND.
  • the constant voltage VFN should be smaller than V VDDH and larger than VGND. That is, the VFN may be between the voltage of the storage node Q1 and the voltage of the storage node Q2 in the read / write state (range 40 in FIG. 21A). If the constant voltage VFN is too close to V VDDH, it is difficult for the inverter circuits 14 and 16 to enter the BI mode when the virtual power supply voltage V VDD is set to V VDDH. If the constant voltage VFN is too close to VGND, it is difficult for the inverter circuits 14 and 16 to enter the ST mode when the virtual power supply voltage V VDD is set to V VDDL.
  • the constant voltage VFN is preferably equal to or less than the midpoint voltage between V VDDH and VGND (that is, (V VDDH-VGND) / 2 or less). It is more preferable that the voltage is equal to or less than the voltage obtained by adding 1/2 of the voltage of the difference between V VDDL and VGND to V VDDL (that is, V VDDL + (V VDDL-VGND) / 2 or less), and further, (V VDDH-VGND) / 2, V VDDL and VGND.
  • V VDDL-VGND voltage at the midpoint
  • V VDDL-VGND voltage at the midpoint
  • range 41 in FIG. between the degree and (range 42 in FIG. 21 (a)) is preferable. Further, about V VDDL is preferable.
  • VVGNDL is supplied to the ground line 15b and VDD is supplied to the power supply line 15a in the read / write state and the VDD retention state.
  • VFP is set to a constant bias of about VVGNDH
  • the inverter circuits 14 and 16 are in BI mode because VFP is sufficiently higher than VVGNDL.
  • VVGNDH is supplied to the ground line 15b and VDD is supplied to the power supply line 15a.
  • the inverter circuits 14 and 16 are in the ST mode because the VFP is lower than the VDD.
  • the constant voltage VFP should be larger than VVGNDL and smaller than VDD. That is, the VFP may be between the voltage of the storage node Q1 and the voltage of the storage node Q2 in the read / write state (range 40 in FIG. 21B). If the constant voltage VFP is too close to VVGNDL, the inverter circuits 14 and 16 are unlikely to be in BI mode when the virtual ground voltage VVGND is set to VVGNDL. If the constant voltage VFP is too close to VDD, the inverter circuits 14 and 16 are unlikely to be in ST mode when the virtual ground voltage VVGND is set to VVGNDH.
  • the constant voltage VFP is preferably equal to or higher than the midpoint voltage between VDD and VVGNDL (that is, (VDD-VVGNDL) / 2 or higher).
  • VVGNDH minus 1/2 of the voltage difference between VDD and VVGNDH is more preferable. It is preferably between the voltage at the midpoint with VVGNDH (that is, about VVGNDH + (else-VVGNDH) / 2) (range 41 in FIG. 21 (b)), VVGNDH- (VDD-VVGNDH) / 2, and VVGNDH + (. Between VDD-VVGNDH) / 2 (range 42 in FIG. 21B) is preferable. Further, about VVGNDH is preferable.
  • the type 1 in which the driver 26 is not provided has been described as an example, but the type 2 in which the driver 26 is provided may also be used.
  • the combination of PDFB and PUFB, the different conductive channel and the same conductive channel, and the header PS, footer PS, and dual PS can be arbitrarily set.
  • the bistable circuit of Example 1 and its modified example may be used for the flip-flop circuit such as the master-slave type flip-flop circuit.
  • a switch such as a pass gate that turns on and off in synchronization with the clock signal may be provided in the loop of the bistable circuit 12.
  • FIG. 22 is a circuit diagram of a virtual power supply type memory cell using the virtual power supply voltage V VDD in the second embodiment.
  • the power switch 30 is provided between the power supply line 15a (virtual power supply line) and the power supply 15c.
  • the memory cell 10 mainly includes inverter circuits 14 and 16, FETs M5 and M6, and spin transfer torque magnetic tunnel junction elements (STT-MTJ: hereinafter simply referred to as ferromagnetic tunnel junction elements) MTJ1 and MTJ2 as non-volatile memory elements. ing.
  • Inverter circuits 14 and 16 are connected in a loop to form a bistable circuit 12.
  • the inverter circuit 14 includes FETs M2 and M4.
  • the inverter circuit 16 includes FETs M1 and M3.
  • FETs M1, M2, M5 and M6 are N-channel MOSFETs, and FETs M3 and M4 are P-channel MOSFETs.
  • FETs M1 (first FET) and M2 (second FET) the source is connected to the ground wire 15b to which the ground voltage VGND is applied, and the drains are connected to the storage nodes Q1 (first storage node) and Q2 (second storage node), respectively. Connected, the gates are connected to storage nodes Q2 and Q1, respectively. Storage nodes Q1 and Q2 are complementary nodes. FETs M1 and M2 are drivers.
  • FETs M3 and M4 In FETs M3 (third FET) and M4 (fourth FET), one of the source and drain is connected to the storage nodes Q1 and Q2, respectively, and the other of the source and drain is the control lines CTRL1 (first control line) and CTRL2 (second control line), respectively. It is connected to the control line) and the gate is connected to the word line WL. FETs M3 and M4 function as pass transistors during read and write operations and as loads during hold, store and restore operations.
  • the FETM5 and the ferromagnetic tunnel junction element MTJ1 are connected between the storage node Q1 and the control line CTRL0, and the FETM6 and the ferromagnetic tunnel junction element MTJ2 are connected between the storage node Q2 and the control line CTRL0.
  • FETs M5 (1st switch) and M6 (2nd switch) one of the source and drain is connected to the storage nodes Q1 and Q2, respectively, and the other of the source and drain is connected to the ferromagnetic tunnel junction elements MTJ1 and MTJ2, respectively. ing.
  • the gate is connected to the switch line SR.
  • the ferromagnetic tunnel junction element MTJ1 (first non-volatile memory element) and MTJ2 (second non-volatile memory element) have a free layer 17, a tunnel insulating film 18, and a pin layer 19, respectively.
  • the free layer 17 is connected to the control line CTRL0 and the pin layer 19 is connected to the FETs M5 and M6.
  • the free layer 17 and the pin layer 19 are made of a ferromagnet. In a state where the magnetization directions of the free layer 17 and the pin layer 19 are parallel (parallel state), the resistance values of MTJ1 and MTJ2 are low.
  • the resistance values of MTJ1 and MTJ2 are higher than in the parallel state.
  • MTJ1 and MTJ2 store data according to the magnetization state (that is, resistance value) of MTJ1 and MTJ2.
  • MTJ will be described as an example of the non-volatile memory element, but the non-volatile memory element is a giant magnetoresistive (GMR) element, a variable resistance element such as that used for ReRAM (Resistance Random Access Memory), or a PRAM (Phase change RAM). ) May be the phase change element used.
  • GMR giant magnetoresistive
  • ReRAM Resistance Random Access Memory
  • PRAM Phase change RAM
  • the selection circuit 32 connects the control line CTRL1 to either the bit line BL or the power supply line 15a.
  • the selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the power supply line 15a.
  • the power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage V VDD and supplies the voltage to the power supply line 15a.
  • FIG. 23 is a diagram showing a power switch and a selection circuit in a virtual power supply system using the virtual power supply voltage of the second embodiment.
  • the memory cell 10 is an NV-RAM cell.
  • the virtual power supply voltage VVDD becomes VDDH during the store operation and the restore operation, and the voltage V VDD-VGND is, for example, 1.2V.
  • the virtual power supply voltage V VDD becomes VDDL in the hold state, and the voltage V VDD-VGND is, for example, 1.0 V.
  • FETs M10 to M12 are turned off during read operation and write operation.
  • FIG. 24 is a circuit diagram of the virtual grounding type memory cell 10 in the second embodiment.
  • the power switch 30 is provided between the ground wire 15b (virtual ground wire) and the ground 15d.
  • FETs M1a to M6a are provided in place of the FETs M1 to M6.
  • FETs M1a, M2a, M5a and M6a are P-channel FETs, and FETs M3a and M4a are N-channel FETs.
  • the sources of FET M1a and M2a are connected to the power supply line 15a.
  • the pin layers 19 of MTJ1 and MTJ2 are connected to the control line CTRL0, and the free layer 17 is connected to FETM5 and M6.
  • the selection circuit 32 connects the control line CTRL1 to either the bit line BL or the ground line 15b.
  • the selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the ground line 15b.
  • the power switch (PS) 30 converts the voltage VGND of the ground 15d into a virtual ground voltage VVGND and supplies it to the ground wire 15b.
  • Other configurations are the same as those in FIG. 22 of the virtual power supply system, and the description thereof will be omitted.
  • FIG. 25 is a diagram showing a power switch and a selection circuit in the virtual grounding method of the second embodiment.
  • the selection circuit 32b connects any of the bit lines BL and BLB and the ground line 15b connected to the read / write circuit 34 to the control lines CTRL1 and CTRL2.
  • the power switch 30 includes FET PS1a and PS2a.
  • FET PS1a and PS2a are N-channel FETs.
  • the FETPS1a is connected between the ground 15dL and the ground wire 15b
  • the FETPS2a is connected between the ground 15dH and the ground wire 15b.
  • the ground voltage VGNDL and the voltage VGNDH are supplied to the ground 15dL and 15dH, respectively.
  • Signals VPS1 and VPS2 are input to the gates of FETPS1a and PS2a, respectively.
  • FETPS1a and PS2a are turned on and off, respectively, and the virtual ground voltage VVGND becomes VGNDL.
  • the virtual ground voltage VVGND becomes VGNDL during the store operation and the restore operation, and VDD-VVGND is, for example, 1.2 V.
  • FETPS1a and PS2a are turned off and on, respectively, and the virtual ground voltage VVGND becomes VGNDH.
  • the virtual ground voltage VVGND becomes VGNDH in the hold state, and VDD-VVGND is, for example, 1.0 V.
  • VDD-VVGND is, for example, 1.0 V.
  • the precharge / selection circuit 33a includes FETs M10 to M12.
  • FETM10 is connected between the power supply 15c and the control line CTRL1.
  • FETM11 is connected between the power supply 15c and the control line CTRL2.
  • FETM12 is connected between the control lines CTRL1 and CTRL2.
  • a selection signal Self is input to the gates of FETs M10 to M12. When the selection signal Self is at a low level, the FETs M10 to M12 are turned on, and the power supply voltage VDD is applied to the control lines CTRL1 and CTRL2. FETs M10 to M12 are turned on when the read operation is precharged. When the selection signal Self is at a high level, the FETs M10 to M12 are turned off and the selection circuit 32b connects the control lines CTRL1 and CTRL2 to the bit lines BL and BLB or the ground line 15b.
  • the memory array and operation of the second embodiment will be described below by taking the virtual power supply method as an example.
  • FIG. 26 is a block diagram of the memory array according to the second embodiment. As shown in FIG. 26, the memory array 22 is divided into a plurality of blocks 24 having memory cells 10. The number of blocks 24 can be appropriately designed. A plurality of memory cells 10 are arranged in a matrix in the memory array 22. In the memory array 22, the word line WL and the switch line SR extend in the row direction, and the control lines CTRL0 to CTRL2 extend in the column direction. A word line WL, a switch line SR, and control lines CTRL0 to CTRL2 are connected to each memory cell 10. In FIG. 26, the control lines CTRL1 and CTRL2 in rows 1 to n are shown as control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.
  • a control circuit 28, a power switch 30, and a peripheral circuit 38 are provided corresponding to the memory array 22.
  • the control circuit 28 controls the power switch 30 and the peripheral circuit 38.
  • the peripheral circuit 38 includes a WL decoder 31, a selection circuit 32b, a precharge / selection circuit 33a, a read / write circuit 34, an SR decoder 35, and a column decoder 36.
  • the selection circuit 32b connects the bit lines BL1 and BLB1 to BLn and BlBn from the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.
  • the WL decoder 31 selects the word line WL based on the row address.
  • the read / write circuit 34 selects the bit lines BL and BLB corresponding to the column selected from the bit lines BL1 and BLB1 to BLn and BLBn based on the column address.
  • the precharge / selection circuit 33a precharges the bit lines BL and BLB.
  • the read / write circuit 34 writes data to the bistable circuit 12 of the selected memory cell 10 or reads data from the bistable circuit 12 and outputs the data to the bus 25.
  • the selection circuit 32b connects the power supply line 15a from the control lines CTRL11 and CTRL21 to the CTRL1n and CTRL2n.
  • the SR decoder 35 selects the switch line SR based on the row address.
  • the column decoder 36 selects the control line CTRL0 based on the column address.
  • the data of the bistable circuit 12 is non-volatilely stored in the ferromagnetic tunnel junction elements MTJ1 and MTJ2.
  • [Explanation of operation] 27 (a) to 29 are diagrams showing the operation of the memory cell in the second embodiment.
  • H indicates a high level
  • L indicates a low level
  • parentheses indicate an example of voltage.
  • the control circuit 28 causes the selection circuit 32b to function the control lines CTRL1 and CTRL2 as bit lines BL and BLB. For example, the control circuit 28 turns off the FETs M10 to M12 in FIG. 23 and turns on the transfer gates M13 and M14.
  • the control circuit 28 sets the word line WL to L (for example, 0V), turns off the FETs M5 and M6 (for example, sets the switch line SR to L (for example, 0V)), and sets the control line CTRL0 to L (for example, 0V).
  • the read / write circuit 34 sets the control lines CTRL1 and CTRL2 to H (for example, 1.2V) and reads the data of the bistable circuit.
  • the control circuit 28 causes the selection circuit 32b to function the control lines CTRL1 and CTRL2 as bit lines BL and BLB.
  • the word line WL is set to L
  • the FETs M5 and M6 are turned off
  • the control line CTRL0 is set to L.
  • the read / write circuit 34 sets the bit lines BL and BLB to L (for example, 0V) and H (for example, 1.2V), respectively. As a result, L and H are written to the storage nodes Q1 and Q2, respectively.
  • the control circuit 28 when the bistable circuit 12 is in a hold state in which data is volatilely held, the control circuit 28 has a voltage VDDH (H) on the control lines CTRL1 and CTRL2 on the power switch 30 and the selection circuit 32b. For example, 1.2V) is applied.
  • the control circuit 28 turns on the FETs M10 to M12 in FIG. 23, turns off the transfer gates M13 and M14, turns on the FET PS1 and turns off the PS2.
  • the control circuit 28 sets the word line WL to H (for example, 1.2V), turns off the FETs M5 and M6, and sets the control line CTRL0 to L.
  • the storage nodes Q1 and Q2 are maintained at H and L, respectively.
  • the FETs M5 and M6 are turned off, so that the influence of the MTJ1 and the MTJ2 does not reach the bistable circuit 12.
  • the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply a voltage VDDH as H to the control lines CTRL1 and CTRL2.
  • the word line WL is set to L
  • the FETs M5 and M6 are turned on (for example, the voltage VSR is set to 0.7 V)
  • the control line CTRL0 is set to L.
  • the current Im1 flows from the storage node Q1 to the control line CTRL0 via the MTJ1. Therefore, MTJ1 is in an antiparallel state and has a high resistance.
  • the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply a voltage VDDH as H to the control lines CTRL1 and CTRL2.
  • the word line WL is set to H'(for example, 0.8V)
  • the FETs M5 and M6 are turned on (for example, the voltage VSR is set to 0.7V)
  • the control line CTRL0 is set to Vc (for example, 0.5V). ..
  • the current Im2 flows from the control line CTRL0 from the storage node Q2 via the MTJ2. Therefore, MTJ2 is in a parallel state and has low resistance.
  • the voltage VWL (first voltage) of the word line WL in the H-store operation (first store operation) is L-. It is lower than the voltage VWL (fourth voltage) of the store operation (second store operation), and the voltage Vc (third voltage) of the control line CTRL0 of the H-store operation is lower than the voltage Vc (sixth voltage) of the L-store operation. Low.
  • the voltages (second voltage and fifth voltage) of the control lines CTRL1 and CTRL2 in the H-store operation and the L-store operation are higher than the voltage VGND of the ground line 15b.
  • the data of the bistable circuit 12 can be stored in MTJ1 and MTJ2.
  • the FETs M1a and M2a are P-type channels
  • the first voltage is higher than the fourth voltage and the third voltage is higher than the sixth voltage.
  • the second voltage and the fifth voltage are lower than the voltage VDD of the power supply line 15a.
  • the power supply is shut down after the store operation (voltage V VDD-VGND is set to 0 V).
  • the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply a voltage VGND (for example, 0V) as L to the control lines CTRL1 and CTRL2.
  • VGND for example, 0V
  • the word line WL is set to L
  • the FETs M5 and M6 are turned off
  • the control line CTRL0 is set to L.
  • the control circuit 28 shuts down the power supply of the memory cell 10.
  • MTJ1 and MTJ2 are maintained at high resistance and low resistance, respectively.
  • the power supplies of the control circuit 28 and the peripheral circuits 38 may or may not be shut down.
  • the control circuit 28 raises the control lines CTRL1 and CTRL2 from L to H'(for example, 1.0V) on the power switch 30 and the selection circuit 32b.
  • the word line WL is set to L'(for example, 0.1 V)
  • the FETs M5 and M6 are turned on (for example, the voltage VSR is set to 0.7 V)
  • the control line CTRL0 is set to L.
  • a current Im3 flows from the control line CTRL1 to MTJ1 via FETs M3 and M5.
  • a current Im4 flows from the control line CTRL2 to the MTJ2 via the FETs M4 and M6. Since MTJ1 and MTJ2 have high resistance and low resistance, respectively, the current Im4 is larger than Im3. As a result, the voltage of the storage node Q2 becomes faster and lower than the voltage of the storage node Q1. Therefore, the storage nodes Q1 and Q2 are stable at H and L, respectively. This completes the restore operation.
  • the bistable circuit 12 volatilely holds the data by putting it in the hold state after the restore operation. It also performs read and write operations.
  • the control circuit 28 sends the FETs M5 and M6 during the write operation of volatilely writing data to the bistable circuit 12 and the read operation of reading from the bistable circuit 12. Turn off. As shown in FIGS. 28 (a), 28 (b) and 29, during the store operation in which the data is non-volatilely stored from the bistable circuit 12 to the MTJ1 and MTJ2, and the data is stored from the MTJ1 and MTJ2 to the bistable circuit 12. Restore FETs M5 and M6 are turned on during the restore operation. As a result, it is possible to suppress the influence of MTJ1 and MTJ2 on the bistable circuit 12 during the write operation and the read operation.
  • Example 3 Appropriate channel widths and voltages in Example 2 were simulated. In simulation 3, the following steps S1 to S5 were performed to determine each channel width and voltage.
  • the channel width of each FET was set as follows. The channel length of each FET is 60 nm.
  • step S1 the channel widths WLP of FETs M3 and M4 were determined from the SNM in the hold state of the 4T cells (FETM1 to M4) of the bistable circuit 12 of Example 2.
  • FIG. 30 is a diagram showing SNM and standby power for WLP in the hold state in simulation 3.
  • the channel widths WDRV of the FETs M1 and M2 are 150 nm
  • the voltage VWL of the word line WL is 1.2 V
  • the voltage VDDH of the control lines CTRL1 and CTRL2 is 1.2 V.
  • SNM has been illustrated for TT, SS, SF, FS and FF.
  • the simulation result of Example 2 (4T cell) is shown as a solid line
  • the simulation result of Comparative Example 3 (6T cell) is shown as a broken line.
  • the WLP is 105 nm or more and all SNMs are 80 mV or more.
  • the standby power exceeds that of Comparative Example 3. From these facts, WLP was determined to be 105 nm.
  • step S2 the voltage VWL of the word line WL in the read operation, the write operation, and the hold state was determined from the SNM in the read operation and the hold state of the 4T cell.
  • FIG. 31 is a diagram showing SNM for VWL in the read operation and hold state in simulation 3.
  • the channel width WDRV of FETM1 and M2 is 150 nm
  • the channel width WLP of FETM3 and M4 is 105 nm
  • the voltage VDDH of the control lines CTRL1 and CTRL2 is 1.2V.
  • SNM has been illustrated for TT, SS, SF, FS and FF.
  • the VWL When the VWL is around 0V, it corresponds to the read operation and the write operation which turn on the FETs M3 and M4, and when the VWL is around 1.2V, it corresponds to the hold state where the FETs M3 and M4 are turned off.
  • SNM depends on VWL.
  • VWL increases from 0V
  • the SNM increases, and when VWL decreases from 1.2V, the SNM increases.
  • step S3 the current Im1 (see FIG. 28A) in the H-store operation was designed.
  • the target current Im1 was 1.2 times the threshold current Ic at which MTJ1 and MTJ2 switch from the parallel state to the antiparallel state.
  • the control lines CTRL1 and CTRL2 are H (1.2V) to hold the data of the bistable circuit 12. Since the current Im1 is passed from the storage node Q1 of H to MTJ1, the voltage Vc of the control line CTRL0 is set to 0V. Turn on FETs M5 and M6. FETM3 is turned on so that the storage node Q1 does not become L. Therefore, the voltage VWL of the word line WL is set to 0V.
  • 32 (a) and 32 (b) are diagrams showing the currents Im1 and SNM with respect to the voltage VSR of the H-store operation in the simulation 3, respectively.
  • the current Im1 increases as the voltage VSR increases.
  • the voltage VSR is 0.7V or more
  • the current Im1 is 1.2Ic or more.
  • the higher the voltage VSR the smaller the SNM.
  • the voltage VSR is 0.95 V or more
  • the SNM falls below 80 mV.
  • the voltage VSR was determined to be 0.7 V so that the SNM was 80 mV or more and the current Im1 was around 1.2 Ic.
  • step S4 the current Im2 (see FIG. 28B) in the L-store operation was designed.
  • the target current Im2 was 1.2 times or more the threshold current Ic at which MTJ1 and MTJ2 switch from the antiparallel state to the parallel state.
  • the control lines CTRL1 and CTRL2 are H (1.2V) to hold the data of the bistable circuit 12. Since the current Im2 is passed from the control line CTRL0 to the storage node Q2 of L via MTJ2, the voltage Vc of the control line CTRL0 is set higher than L. Since the FETs M5 and M6 are turned on, the voltage VSR is set to 0.7V, which is the same as the H-store operation. The voltage VWL of the word line WL and the voltage Vc of the control line CTRL0 were changed.
  • 33 (a) and 33 (b) are diagrams showing the currents Im2 and SNM with respect to the voltage Vc of the L-store operation in the simulation 3, respectively. Since SF is the smallest, SF is shown as SNM. As shown in FIG. 33 (a), the current Im2 increases as the voltage Vc of the control line CTRL0 increases, and the current Im2 increases as the voltage VWL of the word line WL increases. The reason why the current Im2 becomes smaller when the voltage VWL becomes lower is that the FET M4 is completely turned on when the voltage VWL is near 0 V, and the voltage of the storage node Q2 becomes higher.
  • the voltage VWL during the L-store operation is such that the FETs M3 and M4 are slightly turned on. Therefore, when the FETs M1 and M2 are N-type channels, the voltage VWL in the L-store operation is preferably lower than the voltage of the control lines CTRL1 and CTRL2. Further, when the FETs M1a and M2a are P-type channels, the voltage VWL in the second store operation is preferably higher than the voltages of the control lines CTRL1 and CTRL2. As a result, the SNM can be increased.
  • the voltage VWL at the time of the second store operation is preferably VGND + 1/4 (VDD-VGND) or more and VDD-1 / 4 (VDD-VGND) or less.
  • step S5 the voltage VSR of the switch line SR and the voltage VWL of the word line WL in the restore operation were determined.
  • the voltage Vc of the control line CTRL0 is set to 0V, and the voltages of the control lines CTRL1 and CTRL2 are increased.
  • the data is restored to the bistable circuit 12 without raising the voltages of the control lines CTRL1 and CTRL2 to the voltage VDDH (1.2V). Therefore, the restore operation ends when the voltages of the control lines CTRL1 and CTRL2 are raised to 1.0 V.
  • the restore operation for example, when the hold state is set, the voltages of the control lines CTRL1 and CTRL2 are raised to VDDH (1.2V).
  • the voltage VSR can be set to 0 V and the voltage VWL can be set to 1.0 V or more, so that the power consumption can be reduced.
  • the voltage VWL of the word line WL By lowering the voltage VWL of the word line WL and turning on the FETs M3 and M4, a current flows from the control line CTRL1 to the storage node Q1 of H, the H of the storage node Q1 can be maintained, and the SNM becomes large. If the voltage VWL is set too low, the voltage of the storage node Q2 of L becomes high and the SNM is lowered. In consideration of these, the voltage VSR was determined to be 0.7V, which is the same as the store operation, and the voltage VWL was determined to be 0.1V.
  • the voltage VWL of the word line WL is higher than the lower voltage VDD (for example, 0V) of the storage nodes Q1 and Q2 during the write operation, and the higher voltage of the storage nodes Q1 and Q2. It is lower than VGND (eg 1.2V). As a result, the SNM can be increased as shown in FIGS. 34 (a) and 34 (b).
  • the voltage VWL during the restore operation is preferably lower than VGND + 1/4 (VDD-VGND) when FETM1 and M2 are N-type channels, and VDD-1 / 4 (VDD-VGND) when FETM1a and M2a are P-type channels. ) Higher is preferable.
  • Table 5 shows the channel width and each voltage of each FET determined based on the above steps S1 to S5.
  • the voltage VWL of the word line WL in the read operation, the write operation, the H-store operation, and the L-store operation is the voltage VWL in the memory cell 10 to be accessed.
  • the voltage VWL of the inaccessible memory cell 10 is 1.2 V (high level) at which the FETs M3 and M4 are turned off.
  • -0.2V which is lower than L, is applied as the voltage VSR of the switch line SR during the hold state, read operation, and write operation. This is to suppress the leakage current of the FETs M5 and M6.
  • the voltage VSR may be any voltage as long as the FETs M5 and M6 are turned off.
  • the voltage Vc of the control line CTRL0 may be higher than L.
  • the voltage Vc may be 0.05V.
  • the voltage VSR may be lower than L and the voltage Vc may be higher than L.
  • the voltage VSR in the H-store operation, the L-store operation, and the restore operation may be such that the FETs M5 and M6 are turned on.
  • the voltage VWL of the word line WL in the hold state may be such that the FETs M3 and M4 are turned off, and the voltage VWL of the read operation, the write operation, the H-store operation and the restore operation may be such that the FETs M3 and M4 are turned on. Just do it.
  • the channel width and each voltage are not limited to the examples in Table 5, and can be set as appropriate.
  • FIG. 35 (a) is a diagram showing the SNM in the second embodiment. As shown in FIG. 35 (a), the SNM of the FS in the hold state is the smallest. The SNM is 80 mV or higher at all corners of all states and movements. In TT, the SNM is 100 mV or higher in all states and operations.
  • FIG. 35B is a diagram showing standby powers of Example 2 and Comparative Example 3.
  • the FETs M1 and M2 are used as the FETs of the first conductive type channel
  • the FETs M3 and M4 are used as the FETs of the second conductive type channel opposite to the first conductive type
  • the FETs M3 and M4 are passed. Used as a transistor and load. As a result, the standby power can be lowered and the number of transistors can be reduced to 6, so that the size can be reduced.
  • FIG. 36 is a circuit diagram of the memory cell according to the first modification of the second embodiment.
  • the FET M5 and the MTJ1 are connected between the storage node Q1 of FIG. 6 and the control line CTRL0 of the first embodiment, and the storage node Q2 and the control line CTRL0 FETM6 and MTJ2 are connected between them.
  • the bistable circuit 12 may be used as the bistable circuit of the first embodiment and its modifications. Similar to FIGS. 7B and 23, the precharge / selection circuit 33a may be connected to the ends of the control lines CTRL1 and CTRL2, and the selection circuit 32b may be connected to the other ends of the control lines CTRL1 and CTRL2.
  • the access interval to the memory cell 10 is short, the data is ULV retained in the bistable circuit 12, and if the access interval is long, the data is stored in MTJ1 and MTJ2 and shut down. As a result, the power consumption can be further reduced.
  • Example 3 is an application example to a binarized neural network (BNN: Binary Neural Network) such as BinaryNET or XNOR-NET.
  • BNN can be realized with low power consumption and a small amount of memory without significantly deteriorating the inference accuracy, and is expected to be applied to edge computing.
  • edge computing learning and inference are not always performed, but it is necessary to store data such as weights stored in the BNN device in memory. Therefore, reducing the standby power consumption of the memory becomes an issue.
  • ULVR-SRAM or NV-SRAM for the memory portion of the BNN device (BNN accelerator), it is possible to reduce the standby power consumption of the memory.
  • FIG. 37 is a diagram showing a BNN model in Example 3. Below, Batch Normalization Free Technique (Y. Yonekawa and H. Nakahara, “On-chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA”, 2017 IEEE International Parallel The BNN model using -105,2017) is shown.
  • Batch Normalization Free Technique Y. Yonekawa and H. Nakahara, “On-chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA”, 2017 IEEE International Parallel The BNN model using -105,2017
  • the number of layers may be 4 or more.
  • the X layer has nodes x1 to xn
  • the Y layer has nodes y1 to yn
  • the Z layer has nodes z1 to zn.
  • Nodes x1 to xn, y1 to yn, and z1 to zn each have 1 bit.
  • the outputs of the nodes x1 to xn of the X layer are integrated with the weights wi1 to win of 1 bit (i is an integer of 1 to n) and input to the node yi.
  • an integer bias W0i is input to the node yi from the node l.
  • the output of node yi is obtained by passing an evaluation function to the sum of these.
  • the data of all the nodes yi can be obtained.
  • 1-bit weights w'1j to w'nj (j is an integer of 1 to n) are integrated into the output of the node yj of the Y layer and input to each node zk (k is an integer of 1 to n).
  • An integer bias W'j0 is input to the node zj from the node l.
  • Each data of the weight matrices w11 to wnn and w'11 to w'nn is 1 bit, and each data of the integer bias columns W01 to W0n and W'10 to W'n0 is an integer (multi-bit). The same applies when there are layers after the Z layer.
  • the operation for calculating the Y layer from the X layer is performed by performing an operation corresponding to a solid line from the nodes x1 to xn to the node y1, and then performing an operation corresponding to a broken line from the nodes x1 to xn to the node y2. Then, the operation corresponding to the dotted line from the nodes x1 to xn to the node y3 is performed. After that, operations are sequentially performed on the nodes y4 to yn. This is called an n-to-1 connection.
  • the calculation for calculating the Z layer from the Y layer is performed by performing a solid line calculation from the node y1 to the nodes z1 to zn, then performing a dashed line calculation from the node y2 to the nodes z1 to zn, and then performing a dashed line calculation from the node y3 to the node z1.
  • the dotted line is calculated from to zn. This is called a 1-to-n connection.
  • the operations of the solid line and the broken line of the 1-to-n connection can be performed in parallel with the operations of the broken line and the dotted line of the n-to-1 connection, respectively.
  • FIG. 38 is a block of an arithmetic circuit that calculates an n-to-1 connection according to the third embodiment.
  • the arithmetic circuit 50 includes a memory 51 and a processing unit 52.
  • the processing unit 52 includes an XNOR circuit 53, a counter 54, an adder 55, an evaluation unit 56, and an output unit 57.
  • the input unit 48 is an n-bit latch circuit and holds data of nodes x1 to xn.
  • the XNOR circuit 53 acquires the data of the nodes x1 to xn from the input unit 48, acquires the weight strings w1i to wni from the memory 51, and performs XNOR calculation on the data of the nodes x1 to xn and the weight columns w1i to wni.
  • the counter 54 bit-counts the output of the XNOR circuit 53 and calculates the sum. That is, the number of output bits of the n XNOR circuits 53 is 1.
  • the adder 55 acquires the integer bias W0i from the memory 51 and adds it to the output of the counter 54.
  • the evaluation unit 56 compares the output of the adder 55 with the evaluation function f, and outputs a 1-bit result to the output unit 57 as data of the node yi.
  • the output unit 57 is a 1-bit latch circuit and holds the data of the node yi.
  • FIG. 39 (a) is a block of an arithmetic circuit that performs an arithmetic of a 1-ton connection in the third embodiment.
  • the arithmetic circuit 60 includes a memory 61 and a processing unit 62.
  • the processing unit 62 includes an XNOR circuit 63, a storage unit 64, an adder 65, an evaluation unit 66, and an output unit 67.
  • the XNOR circuit 63 acquires the data of the node yi from the output unit 57, acquires the weight strings w'i1 to w'in from the memory 61, and XNORs the data of the node yi and the weight strings w'i1 to w'in. Calculate.
  • FIG. 39 (b) is a block diagram of the accumulator.
  • the accumulator 64 includes an adder 64c and a latch circuit 64d.
  • the adder 64c adds the output of the latch circuit 64d and the output of the XNOR circuit 63.
  • the latch circuit 64d holds the output of the adder 64c.
  • the adder 65 acquires the integer bias strings W'10 to W'n0 from the memory 61 and adds them to the output string of the accumulator 64.
  • the evaluation unit 66 compares the output string of the adder 65 with the evaluation function f, and outputs the result of 1 bit to the output unit 67 as data of the nodes z1 to zn.
  • the output unit 67 is an n-bit latch circuit and holds data of nodes z1 to zn.
  • FIG. 40 is a block diagram of the BNN device according to the third embodiment.
  • the memories 51 (first memory) and 61 (second memory) are in a matrix.
  • the memory 51 stores the integer bias columns W01 to W0n and the weight matrices w11 to wnn.
  • the weights w11 to wnn are each stored in the memory cell 10 (first memory cell).
  • a plurality of weights w1i to wni corresponding to one node yi are stored in the same line, and a plurality of weights corresponding to different nodes yi (for example, w11 to wn1 and w12 to wn2) are stored in different lines. ..
  • a plurality of memory cells 10 in the same row are each connected to a plurality of bit lines BL (first bit lines) extending in the column direction.
  • Each integer bias (W01 to W0n) is multi-bit and is stored in the memory cell 10.
  • the memory 61 stores the integer bias columns W'10 to W'n0 and the weight matrices w'11 to w'nn.
  • the weights w'11 to w'nn are each stored in the memory cell 10'(second memory cell).
  • a plurality of weights w'i1 to w'in corresponding to one second node yi are on the same row, and a plurality of weights corresponding to different second nodes yi (for example, w'11 to w'1n and w). '21 to'w'2n) are stored in different lines.
  • a plurality of memory cells 10'in the same row are each connected to a plurality of second bit lines BL'extending in the column direction.
  • Each integer bias (W'10 to W'n0) is multi-bit and is stored in the memory cell 10'.
  • the processing unit 52 acquires a plurality of first weights w1i to wni from the memory 51 via the plurality of bit lines BL when processing the node yi. can. Further, the processing unit 62 can acquire a plurality of weights w'i1 to w'in from the memory 61 via the second bit line BL'when processing the node yi. As a result, the processing units 52 and 62 can efficiently perform processing.
  • the memory cells 10 and 10' may be 6T-RAM cells, but may be memory cells 10 of Examples 1 and 2 and variations thereof. At least a part of the processing units 52 and 62 may be realized as a dedicated circuit. At least a part of the processing units 52 and 62 may be realized by the processor in cooperation with the software. In this case, at least a part of the processing units 52 and 62 becomes a processor.
  • the XNOR circuit 53 is provided corresponding to the columns of the weight matrices w11 to wnn, and performs XNOR calculation on the output data of the nodes x1 to xn of the input unit 48 and the weight columns w1i to wni.
  • the counter 54 counts the output bits of the XNOR circuit 53.
  • the adder 55, the evaluation unit 56, and the output unit 57 are the same as those described in FIG. 38.
  • the XNOR circuit 63 to the output unit 67 are provided corresponding to the columns of the weight matrices w'11 to w'nn.
  • the XNOR circuit 63 performs XNOR calculation on the output data of the node yi of the output unit 57 and the weight strings w'i1 to w'in.
  • the accumulation device 64 to the output unit 67 are performed for each column. Other operations are the same as those described in FIG. 39 (a).
  • the nodes z1 to zn of the output unit 67 serve as an input data string for the n-to-1 connection process of the next layer.
  • FIG. 41 is a flowchart showing the processing of the n-to-1 connection performed by the processing unit 52 in the third embodiment.
  • the processing unit 52 sets i to 1 (step S10).
  • the processing unit 52 acquires the weight strings w1i to wni from the memory 51 (step S12).
  • the processing unit 52 calculates the XNOR between the data of the nodes x1 to xn and the weight columns w1i to wni (step S14).
  • the processing unit 52 bit-counts the calculation result of each XNOR and calculates the total (step S16).
  • the processing unit 52 acquires the weight W0i from the memory 51 and adds it to the total sum of steps S16 (step S18).
  • the processing unit 52 includes a control circuit that controls the operation of each circuit, and the control circuit may execute steps S10 to S24.
  • FIG. 42 is a flowchart showing the processing of the 1-ton connection performed by the processing unit 62 in the third embodiment.
  • the processing unit 62 sets i to 1 (step S30).
  • the processing unit 62 acquires the weight strings w'i1 to w'in from the memory 61 (step S32).
  • the processing unit 62 acquires the data of the node yi from step S20 of FIG. 41, and calculates the XNOR between the data of the node yi and the weight columns w'i1 to w'in (step S34).
  • the processing unit 62 accumulates the calculation results of n XNORs (step S36).
  • the processing unit 62 acquires the weights W'10 to W'n0 from the memory 61 and adds them to the n results of step S36 (step S42).
  • the processing unit 62 calculates and holds the data of the nodes z1 to zn of 1 bit each by comparing the n results of step S42 with the evaluation function f (step S44). After that, the 1-to-n connection process is terminated.
  • the data of the nodes z1 to zn becomes an input data string when making an n-to-1 connection of the next layer.
  • the processing unit 62 includes a control circuit that controls the operation of each circuit, and the control circuit may execute steps S30 to S44.
  • FIG. 43 is an explanatory diagram showing the processing operation of the third embodiment along the time axis.
  • the processing operation of the third embodiment is shown so that it can be compared with the processing operations of the cases 1 and 2 described later.
  • Processes 71 to 74 indicate operations between layers.
  • the process 71 is a process of calculating each node y1 to yn of the Y layer from each node x1 to xn of the X layer in FIG. 37
  • the process 72 is a process of calculating each node y1 to yn of the Y layer to each node z1 to the Z layer. This is a process for calculating zn.
  • the process 73 is a process of calculating each node of the subsequent layer from each node z1 to zn of the Z layer.
  • the process 74 is a subsequent process.
  • Process 70 indicates a process corresponding to one node.
  • the process of calculating one node yi from n nodes x1 to xn corresponds to the process 70.
  • the process of calculating n nodes z1 to zn from one node yi corresponds to the process 70.
  • n processes 70 are sequentially executed.
  • the processes 71 to 74 are all n-to-1 connection processes or all 1-to-n connection processes. In this case, the processes 71 to 74 cannot be processed in parallel.
  • the processes 71 and 73 are 1-to-n connection processes, and the processes 72 and 74 are n-to-1 connection processes. In this case, the processes 71 and 72 cannot be processed in parallel.
  • Process 72 and process 73 can be processed in parallel.
  • the processes 71 and 73 are n-to-1 connection processes, and the processes 72 and 74 are 1-to-n connection processes.
  • the i + 1th process 70 of the process 71 and the i-th process of the process 72 can be processed in parallel. Therefore, the process 70 and the process 71 can be processed in the time of n + 1 processes 70.
  • the process 73 is started. The i + 1th process 70 of the process 73 and the i-th process of the process 74 can be processed in parallel.
  • the processing time can be shortened as compared with Case 1, but in Example 3, the processing time can be further shortened as compared with Case 2.
  • the memory array 22 of FIG. 7A of the first embodiment or the memory array 22 of FIG. 26 of the second embodiment can be used for the memories 51 and 61 of the third embodiment. As a result, power consumption can be suppressed.
  • FIG. 44 is a block diagram showing an example of the memory in the third embodiment.
  • power switches PS1 to PSn are provided for each row of the memories 51 and 61.
  • a power switch control circuit 58 for independently controlling the power switches PS1 to PSn in different states is provided.
  • the virtual power supply voltages V VDD1 to VVDDn can be set for each row.
  • the power switch control circuit 58 sets the first power supply so that the line in which the data to be processed is stored is in a state in which the data can be read. Supply voltage.
  • the power switch control circuit 58 puts the other rows in the ULV retention state when the memory array of the first embodiment is used for the memories 51 and 61, and is in the shutdown state when the memory array of the second embodiment is used.
  • the power switch control circuit 58 performs the i-th row of the memory 51 or 61.
  • the virtual power supply voltage V VDDi supplied to the memory cell is set to the first power supply voltage at which data can be read from the memory cell 10 or 10', and the virtual power supply voltage V VDD supplied to the rows other than the i-th row is lower than the first power supply voltage and is set to the memory cell.
  • 10 or 10' is a second power supply voltage capable of holding data or shuts down the power supply voltage.
  • the second power supply voltage is a voltage that is in the ULV retention state.
  • the power supply voltage is shut down.
  • the power switch control circuit 58 may supply the second power supply voltage to at least a part of the rows other than the i-th row or shut down the power supply voltage.
  • the control of the power switches PS1 to PSn is not limited to the control described above, but the recovery time until the data can be read from the ULV retention state of the memories 51 and 61, and the memory array of the second embodiment reads the data from the shutdown state. Considering the recovery time until it can be output, power is supplied so that the rows near the rows that perform n-to-1 connection processing and 1-to-n connection processing can also read the data. May be good.
  • Each virtual power supply voltage V VDD1 to V VDDn may have a plurality of stages.
  • a power switch corresponding to the number of virtual power supply voltages is provided.
  • a power switch is provided for each row, but a power switch may be provided for each of a plurality of rows.
  • the virtual power supply method has been described as an example, a virtual grounding method may also be used.
  • FIG. 44 describes an example of reducing power consumption by controlling the power switches PS1 to PSn described above in both the n-to-1 connection processing and the 1-ton connection processing of the neural network processing.
  • the power consumption is reduced by controlling the power switches PS1 to PSn described above. May be good.
  • a processing device having an inferencer learned by deplaning in which n-to-1 connection processing and 1-to-n connection processing are repeated in multiple layers, n-to-1 connection processing and 1-to are performed. Power consumption can be reduced by controlling the power switches PS1 to PSn described above for at least one layer of the -n connection process. All of these are included in the embodiments of the fourth invention of the present application.
  • the power consumption of the BNN apparatus was simulated in the case where the 6T cell of Comparative Example 3 and the ULVR-SRAM cell of Example 1 were used for the memory cells 10 and 10'in the memories 51 and 61.
  • the power consumption of the memory can be reduced by 50% to 60% in the sleep state in which the power supply voltage is 70% of the normal state.
  • the power consumption of the memory can be reduced by 90% to 95% as compared with the normal state of the 6T cell.
  • the power consumption of the BNN apparatus can be reduced by using the ULVR-RAMC cell of Example 1 or the NV-RAM cell of Example 2 for the memory cells 10 and 10'. Further, the ULVR-RAMC cell described in Patent Document 1 or the NV-RAM cell described in Patent Document 2 may be used for the memory cells 10 and 10'. As a result, standby power consumption can be reduced.
  • the processing unit 52 (first processing unit) has a plurality of first nodes corresponding to a plurality of first nodes x1 to xn of the X layer (first layer).
  • first layer By weighting the data with a plurality of first weights w1i to wni and then adding them as in step S18, a plurality of second nodes in the Y layer (second layer) as in steps S16, S18 and S20.
  • the data of the second node yi of one of the plurality of second data corresponding to y1 to yn is calculated.
  • the processing unit 52 calculates a plurality of second data by performing this processing on the plurality of second nodes y1 to yn.
  • the processing unit 62 (second processing unit) has a plurality of second weights w'i1 to w'on the data of the second node yi of the plurality of second nodes y1 to yn.
  • second processing unit has a plurality of second weights w'i1 to w'on the data of the second node yi of the plurality of second nodes y1 to yn.
  • the processing unit 62 adds a part of the data of the plurality of third nodes z1 to zn for each of the plurality of third nodes z1 to zn by a plurality of second nodes y1 to yn. As a result, the data of the plurality of third nodes z1 to zn are calculated. Then, the processing unit 52 processes the other second node yi + 1 of the plurality of second data in parallel with the processing of the second node yi of the plurality of second data performed by the processing unit 62. As a result, as shown in FIG. 43, the processing time of the processing apparatus can be shortened.
  • the data of the nodes x1 to xn, y1 to yn and z1 to zn, the weights w11 to wnn and the weights w'11 to w'nn are 1 bit each.
  • BNN can be processed.
  • the processing unit 52 weights the data of the plurality of first nodes x1 to xn and the plurality of first weights w1i to wni by performing XNOR calculation, and the processing unit 62 performs weighting with the data of the second node yi. Weighting is performed by performing XNOR calculation on a plurality of second weights w'i1 to w'in. As a result, weighting can be performed in BNN.
  • FIG. 45 is a block diagram of the BNN device according to the first modification of the third embodiment.
  • the XNOR circuits 53a and 53b, the counters 54a and 54b, the adders 55a and 55b, the evaluation units 56a and 56b, and the output units 57a and 57b are included in the processing unit 52, respectively.
  • a plurality of lines of the memory 51 are provided.
  • the processing unit 62 processes the processes corresponding to the plurality of rows of the memory 61 in parallel.
  • XNOR circuits 63a and 63b are provided for a plurality of lines of the memory 61, respectively.
  • the processing unit 62 processes the processes corresponding to the plurality of rows of the memory 61 in parallel.
  • FIG. 46 is a diagram showing an example of the memory in the first modification of the third embodiment.
  • the peripheral circuits other than the sense amplifiers 44a and 44b are not shown.
  • memory cells 10a and 10b are arranged in a matrix in the memories 51 and 61.
  • the bit lines BL1 and BLB1 and the bit lines BL2 and BLB2 extend in the column direction.
  • the storage nodes Q1 and Q2 (see FIGS. 1 and 22 and the like) of the memory cells 10a are connected to the bit lines BL1 and BLB1, respectively, and are not connected to the bit lines BL2 and BLB2. ..
  • the storage nodes Q1 and Q2 of the memory cell 10b are connected to the bit lines BL2 and BLB2, respectively, and are not connected to the bit lines BL1 and BLB1.
  • a plurality of sense amplifiers 44a and 44b are provided in one row.
  • the bit lines BL1 and BLB1 are connected to the sense amplifier 44a, and the bit lines BL2 and BLB2 are connected to the sense amplifier 44b.
  • the sense amplifiers 44a and 44b read the data of the memory cells 10a and 10b selected by the word line WL, respectively.
  • the sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively.
  • the memory cell 10 may be a 6T cell as in Comparative Example 3, or may be a memory cell 10 of Examples 1 and 2 and a modification thereof.
  • the second modification of the third embodiment is an example in which the multi-port cell is used for the memories 51 and 61.
  • a multi-port cell As a multi-port cell, a 2R1W type having one write port and two read ports and a 2RW type having both a write port and a read port will be described.
  • FIG. 47 is a circuit diagram showing an example of a 2R1W type NV-RAM memory cell in the second modification of the third embodiment. As shown in FIG. 47, WWL, RWL1 and RWL2 are provided as word lines. WWL is a write word line, and RWL1 and RWL2 are read word lines. Control lines CTRL1 to CTRL3 are provided.
  • the gate of FETM3 is connected to WWL, one of the source and drain is connected to the storage node Q1, and the other of the source and drain is connected to the control line CTRL1.
  • the gate of FETM41 is connected to RWL1, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL2.
  • the gate of FETM42 is connected to RWL2, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL3.
  • Other configurations are the same as those in the second embodiment, and the description thereof will be omitted.
  • Table 6 is a table showing the voltage of each line in each state and operation.
  • the voltages of the word lines WWL, RWL1 and RWL2 in the write operation, the read operation 1 and the read operation 2 are the voltages in the memory cell 10 to be accessed.
  • the voltage of the word lines WWL, RWL1 and RWL2 of the inaccessible memory cell 10 is 1.2V.
  • the voltages of WWL, RWL1, RWL2 and CTRL1 to CTRL3 are 1.2V (high level), and FETM3, M41 and M42 are off.
  • the WWL voltage of the cell 10 to be lit is set to 0 V (low level).
  • the FET M3 of the cell to be lit is turned on.
  • the voltage of the word lines RWL1 and RWL2 is 1.2V and the FETs M41 and M42 are off.
  • the storage node Q1 becomes H or L. As a result, the data is written in the cell 10.
  • the voltage of RWL1 of the cell 10 to be read is set to 0V.
  • the FET M41 of the lead cell 10 is turned on.
  • the voltage of RWL2 is 1.2V and FETM42 is off.
  • the voltage of WWL is 0.7V, and FETM3 is turned on slightly.
  • FIG. 48 is a circuit diagram showing an example of a 2R1W type ULVR-SRAM memory cell in the second modification of the third embodiment. As shown in FIG. 48, WWL, RWL1 and RWL2 are provided as word lines. Control lines CTRL1 to CTRL3 are provided.
  • the gate of FETm4 is connected to WWL, one of the source and drain is connected to the storage node Q1, and the other of the source and drain is connected to the control line CTRL1.
  • the gate of FETm41 is connected to RWL1, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL2.
  • the gate of FETm42 is connected to RWL2, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL3.
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • Table 7 is a table showing the voltage of each line in each state and operation.
  • the voltage of the word lines WWL, RWL1 and RWL2 is 1.1V
  • the voltage of CTRL1 to CTRL3 is 1.2V
  • the FETs m4, m41 and m42 are off. ..
  • the voltage of the WWL of the memory cell 10 to be written is set to 0.3 V.
  • the FET m3 of the memory cell 10 to be written is turned on.
  • the voltage of the word lines RWL1 and RWL2 is 1.1V and the FETs m41 and m42 are off.
  • the storage node Q1 becomes H or L.
  • the data is written to the memory cell 10.
  • the voltage of RWL1 of the memory cell 10 to be read is set to 0.3V.
  • the FET m41 of the leading memory cell 10 is turned on.
  • the voltage of RWL2 is 1.1V and FETm42 is off.
  • the voltage of WWL is 0.6V, and FETm4 is turned on slightly.
  • the lead operation 2 is the same as the lead operation 1.
  • the voltage of the word lines WWL, RWL1 and RWL2 of the inaccessible memory cell 10 is 1.1 V. Other operations are the same as in the first embodiment.
  • the SNM for the voltage VWWL of the word line WWL at the time of read operations 1 and 2 was simulated.
  • WLP 105 nm
  • WDRV 150 nm
  • VRWL 0 V of the word lines RWL1 and RWL2.
  • V VDD 1.2V
  • BI mode BI mode
  • WLP 110 nm
  • WFB 230 nm.
  • FIG. 49 (a) is a diagram showing SNM with respect to VWWL of the 2R1W type NV-RAM memory cell in the read operation of the second modification of the third embodiment
  • FIG. 49 (b) is a diagram showing the 2R1W type ULVR-RAM memory cell in the read operation. It is a figure which shows the SNM for VWWL of. As shown in FIGS. 49 (a) and 49 (b), the SNM becomes smaller as the voltage VWWL of the word line WWL becomes higher. In the read operation, the word line WWL for writing is not selected, and FETM3 and FETm4 are turned off. However, when FETM3 and FETm4 are completely turned off, the SNM becomes smaller.
  • the voltage VWWL (for example, 0.6V) of the word line WWL for writing in the read operations 1 and 2 is made higher than the voltage VWWL (for example, 0.3V) in the writing operation. Further, the voltage VWWL of the read operation 1 (for example, 0.6 V) is made lower than the voltage of the word line RWL1 for the read operation 2 (for example, 1.2 V). The same applies to the lead operation 2. As a result, the SNM can be increased.
  • FIG. 50 is a circuit diagram showing an example of a 2RW type NV-RAM memory cell in the second modification of the third embodiment. As shown in FIG. 50, WL1 and WL2 are provided as word lines. CTRL1, CTRL1', CTRL2 and CTRL2'are provided as control lines.
  • FETM31 third FET
  • one of the source and drain is connected to the storage node Q1 (first storage node)
  • the other of the source and drain is the control line CTRL1 (first). It is connected to the control line).
  • the gate of FETM32 is connected to WL2 (second word line), one of the source and drain is connected to the storage node Q1, and the other of the source and drain is connected to the control line CTRL1'(fourth control line).
  • the gate of the FET M41 (fourth FET) is connected to WL1, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL2 (second control line).
  • the gate of the FET M42 (sixth FET) is connected to WL2, one of the source and drain is connected to the storage node Q2, and the other of the source and drain is connected to the control line CTRL2'(fifth control line).
  • Other configurations are the same as those in the second embodiment, and the description thereof will be omitted.
  • Table 8 is a table showing the voltage of each line in each state and operation.
  • the voltage of the word lines WL1, WL2, the control lines CTRL1, CTRL1', CTRL2 and CTRL2' is 1.2V (high level), and the FETs M31, M32, M41 and M42 are It is off.
  • the WL1, CTRL1 and CTRL2 are used to write and read data via the FETs M31 and M41.
  • the write operation 2 and the read operation 2 are the same as the write operation 1 and the read operation 1.
  • the voltage of the word lines WL1 and WL2 of the inaccessible memory cell 10 is 1.2V. Other operations are the same as in the second embodiment.
  • FIG. 51 is a circuit diagram showing an example of a 2RW type ULVR-SRAM memory cell in the second modification of the third embodiment. As shown in FIG. 51, WL1 and WL2 are provided as word lines. CTRL1, CTRL1', CTRL2 and CTRL2'are provided as control lines.
  • FETm41 third FET, fourth FET
  • WL1 first word line
  • one of the source and drain is connected to the storage nodes Q1 and Q2
  • the other of the source and drain is the control line CTRL1 (first control). Line) and CTRL2 (second control line).
  • the gate of the FET m42 is connected to WL2 (second word line)
  • one of the source and drain is connected to the storage nodes Q1 and Q2
  • the other of the source and drain is the control line CTRL1'(third). It is connected to the control line) and CTRL2'(fourth control line).
  • Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.
  • Table 9 is a table showing the voltage of each line in each state and operation.
  • the voltages of WL1 and WL2 are 1.1V, the voltages of CTRL1, 2, 1'and 2'are 1.2V, and the FETs m41 and m42 are off.
  • the WL1, CTRL1 and CTRL2 are used to write and read data via the FET m41.
  • the voltage of WL2 is set to 1.1V
  • the voltage of CTRL1'and CTRL2' is set to 1.2V
  • the FET m42 is turned off.
  • the write operation 2 and the read operation 2 are the same as the write operation 1 and the read operation 1.
  • the voltage of the word lines WL1 and WL2 of the inaccessible memory cell 10 is 1.1 V. Other operations are the same as in the second embodiment.
  • FIG. 52 is a diagram showing an example of the 2R1W type memory in the second modification of the third embodiment.
  • the peripheral circuits other than the sense amplifiers 44a and 44b are not shown.
  • the memory cells 10 are arranged in a matrix in the memories 51 and 61.
  • the memory cell 10 is a 2R1W type NV-RAM cell or a 2R1W type ULVR-SRAM cell.
  • the control line CTRL2 is connected to the sense amplifier 44a, and the control line CTRL3 is connected to the sense amplifier 44b.
  • the sense amplifier 44a reads the data of the memory cell 10 selected by the word line RWL1, and the sense amplifier 44b reads the data of the memory cell 10 selected by the word line RWL2.
  • the sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively.
  • the weight columns of a plurality of rows can be output in parallel from the memory 51 or 61 to the XNOR circuits 53a and 53b (or 63a and 63b).
  • the memory cell 10 may be a 6T cell.
  • FIG. 53 is a diagram showing an example of a 2RW type memory in the second modification of the third embodiment.
  • the peripheral circuits other than the sense amplifiers 44a and 44b are not shown.
  • the memory cell 10 is a 2RW type NV-RAM cell or a 2RW type ULVR-SRAM cell.
  • the control lines CTRL1 and CTRL2 are connected to the sense amplifier 44a, and the control lines CTRL1'and CTRL2' are connected to the sense amplifier 44b.
  • the sense amplifier 44a reads the data of the memory cell 10 selected by the word line WL1, and the sense amplifier 44b reads the data of the memory cell 10 selected by the word line WL2.
  • Other configurations are the same as in FIG. 52.
  • the sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively.
  • the weight columns of a plurality of rows can be output in parallel from the memory 51 or 61 to the XNOR circuits 53a and 53b (or 63a and 63b).
  • the memory cell 10 may be a 6T cell.
  • FIG. 54 is a diagram showing processing for time in the modified example of Example 3. Case 1, Case 2 and Example 3 are the same as those in FIG. 43, and the description thereof will be omitted.
  • the processing for two lines of the memories 51 and 61 can be performed in parallel.
  • the process 71 can be processed in parallel with the processes 71a and 71b.
  • the processes 72a and 72b can be processed in parallel
  • the processes 73a and 73b can be processed in parallel
  • the processes 74a and 74b can be processed in parallel. Therefore, the processing time can be shortened as compared with the third embodiment.
  • the processing for four lines of the memories 51 and 61 is performed in parallel.
  • the process 71 can be processed in parallel with the processes 71a to 71d.
  • the processes 72a to 72d can be processed in parallel
  • the processes 73a to 73d can be processed in parallel
  • the processes 74a to 74d can be processed in parallel. Therefore, the processing time can be further shortened as compared with the modified examples 1 and 2 of the third embodiment.
  • the processing unit 52 processes the processing of at least two second nodes among the plurality of second nodes y1 to yn in parallel, and the processing unit 62 processes the processing of the plurality of second nodes.
  • the processing of at least two second nodes out of the two nodes y1 to yn is processed in parallel.
  • the processing time can be shortened as shown in FIG. 54.
  • the plurality of memory cells 10 have a pair of complementary storage nodes Q1 and Q2, respectively, and at least one storage node of the pair of storage nodes Q1 and Q2. Is connected to a control line CTRL2 (first bit line) extending in parallel in the column direction and a control line CTRL3 or CTRL2'(second bit line).
  • the processing unit 52 acquires a plurality of first weights from the memory 51 via the first bit line when performing one of the processes of the second data to be processed in parallel, and when performing another process, the memory A plurality of first weights are acquired from 51 via the second bit line. As a result, the processing unit 52 can execute the two processes in parallel.
  • the control line CTRL2 (third bit line) is transmitted from the memory 61.
  • the plurality of first weights are acquired from the memory 61 via the control line CTRL3 or CTRL2'(fourth bit line).
  • the processing unit 62 can execute the two processes in parallel.
  • the other of the source and drain of FETM3 is connected to the first control line CTRL1, and the gate is connected to the first word line WWL.
  • the other of the source and drain of FETM41 is connected to the second control line CTRL2 and the gate is connected to the second word line RWL1.
  • One of the source and drain of the FET M42 (fifth FET) is connected to the storage node Q2, the other of the source and drain is connected to the fourth control line CTRL3, and the gate is connected to the third word line RWL2.
  • the inverter circuit 16 (second inverter circuit)
  • the other of the source and drain of the FET m4 is connected to the first control line CTRL1.
  • the gate is connected to the first word line WWL.
  • the other of the source and drain of the FET m41 is connected to the second control line CTRL2, and the gate is connected to the second word line RWL1.
  • One of the source and drain of the FET m42 is connected to the second storage node Q2, the other of the source and the drain is connected to the third control line CTRL3, and the gate is connected to the third word line RWL2.
  • the control circuit 28 uses the word line WWL to turn on the FET M3 in FIG. 47 or the FET m4 of the inverter circuit 16 in FIG. 48, and uses the control line CTRL1 to write data to the bistable circuit 12.
  • the control circuit 28 uses the word line RWL1 to turn on the FETM41 or FETm41, uses the control line CTRL2 to read data from the bistability circuit 12, turns on the FETM42 or FETm42 using the word line RWL2, and uses the control line CTRL3 to twin. Data is read from the stabilization circuit 12.
  • the control lines CTRL2 and CTRL3 that lead data from the bistability circuit 12 can be selected by using the word lines RWL1 and RWL2.
  • the control circuit 28 sets the voltage of the word line WWL when reading data from the bistable circuit 12 to the bistable circuit 12
  • the voltage is higher than the voltage of the word line WWL when writing data to, and is lower than the voltage of the word lines RWL1 and RWL2 when reading data from the bistable circuit 12.
  • the voltage of the word line WWL during the read operation is preferably higher than the voltage of the word line WWL during the write operation by (VDD-VGND) / 10, and of the voltages of the word lines RWL1 and RWL2 during the read operation. It is preferably lower than the higher voltage by (VDD-VGND) / 10 or more.
  • the control circuit 28 sets the voltage of the word line WWL when reading data from the bistable circuit 12 and the ward line when writing data to the bistable circuit 12. It should be lower than the voltage of WWL and higher than the lower voltage of the word lines RWL1 and RWL2 when reading data from the bistable circuit 12. As a result, the SNM at the time of reading can be improved.
  • the voltage of the word line WWL during the read operation is preferably lower than the voltage of the word line WWL during the write operation by (VDD-VGND) / 10 or more, and among the voltages of the word lines RWL1 and RWL2 during the read operation. It is preferable that the voltage is (VDD-VGND) / 10 or more higher than the higher voltage.
  • FIG. 56 is a circuit diagram of an NV-RAM memory cell according to a modification 4 of the third embodiment.
  • cells 78 and 78 ′ include memory cells 10 and 10 ′ of Example 2 and an XNOR circuit 79.
  • the XNOR circuit 79 includes FETs M7 to M9.
  • FETM7 one end of the source and drain is connected to the control line CTRL1, the other end of the source and drain is connected to node N5, and the gate is connected to storage node Q2.
  • FETM8 one end of the source and drain is connected to the control line CTRL2, the other end of the source and drain is connected to node N5, and the gate is connected to storage node Q1.
  • FETM9 one end of the source and drain is connected to the ground wire 15b, the other end of the source and drain is connected to the output line SAIN, and the gate is connected to the node N5.
  • the XNOR circuit 79 In the hold state of the memory cell 10, the XNOR circuit 79 outputs the XNOR of the storage node Q1 and the control line CTRL1 (corresponding to the XNOR of the storage node Q2 and the control line CTRL2) to the output line SAIN.
  • One bit of calculation data (for example, H is 1.2V and L is 0V) is input to the control line CTRL1, and complementary data of the calculation data is input to the control line CTRL2.
  • the calculation data and the XNOR of the storage node Q1 are output to the output line SAIN.
  • FIG. 57 is a circuit diagram of the ULVR-SRAM memory cell according to the fourth modification of the third embodiment.
  • cells 78 and 78 ′ include memory cells 10 and 10 ′ of Example 1 and an XNOR circuit 79.
  • the circuit configuration and function of the XNOR circuit 79 are the same as those in FIG. 56.
  • FIG. 58 is a block diagram of the BNN device according to the fourth modification of the third embodiment.
  • the memory cells in the memories 51 and 61 are cells 78 and 78'in FIG. 56 or 57.
  • the processing units 52 and 62 do not have an XNOR circuit.
  • the XNOR is output from the memory 51, the data of the nodes x1 to xn of the input unit 48 and the complementary data thereof are input to the control line CTRL1 and the control line CTRL2 of the memory 51, respectively.
  • the sense amplifier of the memory 51 reads data from the output line SAIN of each column and outputs the data to the counter 54.
  • the data of the node yi of the output unit 57 and its complementary data are input to the control line CTRL1 and the control line CTRL2 of the memory 61.
  • the sense amplifier of the memory 61 reads data from the output line SAIN of each column and outputs the data to the accumulator 64.
  • the XNOR circuit 79 may be provided in each of the cells 78 and 78'as in the modified example 4 of the third embodiment. In the modifications 1 to 3 of the third embodiment, the XNOR circuit 79 may be provided in each cell 78.
  • the memories 51 and 61 include XNOR circuits 79 (first XNOR circuit and second XNOR circuit) corresponding to the memory cells 10 and 10'. As a result, it is not necessary to provide the XNOR circuits 53 and 63 in the processing units 52 and 62.
  • FIG. 59 (a) and 59 (b) are block diagrams in the vicinity of the power switch of the modified example 5 of the comparative example 4 and the third embodiment, respectively.
  • a plurality of 6T cells 10 are arranged in one row of the memory array.
  • the number of cells 10 in one row is, for example, 512.
  • the power supply lines 15a (virtual power supply lines) of the memory cells 10 in one row are commonly connected.
  • one FETPS2 is provided between the power supply 15cL of the voltage VDDL for the sleep state and the power supply line 15a.
  • the power supply 15cH having a voltage of VDDH and the FETPS1 for a power switch are not shown. When FETPS2 is turned on, the virtual power supply voltage V VDD of the power supply line 15a becomes VDDL.
  • the power switch 30 is provided with FETPS2 for each memory cell 10, and each FETPS2 has a power supply 15 cL of a voltage VDDL for a sleep state and a power supply line. It is connected to 15a.
  • the power supply 15cH having a voltage of VDDH and the FETPS1 for a power switch are not shown.
  • FETPS2 is turned on, the virtual power supply voltage V VDD of the power supply line 15a becomes VDDL.
  • FIG. 60 is a circuit diagram of the 6T cell in the modified example 5 of the third embodiment.
  • the bistability circuit 12 includes an inverter circuit 14 having PFETM1'and NFETM1 and an inverter circuit 16 having PFETM2'and NFETM2.
  • the inverter circuits 14 and 16 are connected in a loop.
  • NFETs M3 and M4 for the path are provided.
  • the power switch 30 includes a FETPS1 that connects the power supply 15cH that supplies the voltage VDDH and the power supply line 15a, and a FETPS2 that connects the power supply 15cL that supplies the voltage VDDL and the power supply line 15a.
  • the voltage VDDH is a power supply voltage (second power supply voltage) during read or write operation, and is, for example, 1.2 V.
  • the voltage VDDL is a power supply voltage (first power supply voltage) in a sleep state in which the bistable circuit 12 holds data but does not perform write and read operations, and is, for example, 1/3 to 1/4 of VDDH.
  • the FETPS1 (second power switch) and the FETPS2 (first power switch) are connected to one or several (for example, 10 or less) virtual power lines 15a of the memory cells 10 each.
  • the FETPS1 may be supplied by more cells than the FETPS2. For example, one FETPS1 may be connected to 64, 128 or 256 memory cells 10.
  • 61 (a) and 61 (b) are diagrams showing SNM and standby power with respect to VDDL in Comparative Example 4 and Modification 5 of Example 3, respectively.
  • VDDL As shown in FIG. 61A, in Comparative Example 4, when VDDL is 1.2V, SNM is 100 mV to 180 mV. The lower the VDDL, the smaller the SNM. The minimum VDDL at which all SNMs are 80 mV or more is 0.8 V. Therefore, VDDL in the sleep state is set to 0.8V. When VDDL is 0.8V, the standby power is about 1.6nW.
  • the SNM is 300 mV or more when the VDDL is 1.2 V.
  • the lower the VDDL the smaller the SNM.
  • the minimum VDDL at which all SNMs are 80 mV or more is 0.35 V. Therefore, VDDL in the sleep state is set to 0.35V.
  • the standby power is about 0.5nW. As described above, in Comparative Example 5 of Example 3 of FIG. 59 (b), the standby power can be reduced as compared with Comparative Example 4 of FIG. 59 (a).
  • the SNM can be increased even if the VDDL is lowered.
  • the virtual power supply voltage V VDD becomes lower than the VDDL, and the SNM becomes This is because the virtual power supply voltage V VDD can be kept at VDDL when only one memory cell 10 (or several) is connected, although it deteriorates.
  • the power supply voltage for retention can be lowered even if the 6T memory cells are used as the memory cells 10 and 10'. Therefore, the area of the memory cell can be reduced and the power consumption can be suppressed.
  • the virtual power supply method has been described as an example, a virtual grounding method may also be used.
  • the modified example 5 of the third embodiment may be applied to the BNN apparatus of the third embodiment and the modified examples 1 to 4 thereof.
  • the third embodiment and its modifications can be applied to a neural network device other than the BNN device.

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TWI891723B (zh) 2025-08-01

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