JP7420804B2 - 改良された速度モードによるデータ通信 - Google Patents

改良された速度モードによるデータ通信 Download PDF

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Publication number
JP7420804B2
JP7420804B2 JP2021527859A JP2021527859A JP7420804B2 JP 7420804 B2 JP7420804 B2 JP 7420804B2 JP 2021527859 A JP2021527859 A JP 2021527859A JP 2021527859 A JP2021527859 A JP 2021527859A JP 7420804 B2 JP7420804 B2 JP 7420804B2
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Japan
Prior art keywords
link
speed
controller
pcie
interconnect
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JP2021527859A
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English (en)
Japanese (ja)
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JP2022510812A5 (https=
JP2022510812A (ja
JPWO2020122989A5 (https=
Inventor
キャルック ゴードン
アール． タルボット ジェラルド
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ATI Technologies ULC
Advanced Micro Devices Inc
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ATI Technologies ULC
Advanced Micro Devices Inc
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Publication of JPWO2020122989A5 publication Critical patent/JPWO2020122989A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
JP2021527859A 2018-12-14 2019-06-27 改良された速度モードによるデータ通信 Active JP7420804B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/221,181 2018-12-14
US16/221,181 US11151075B2 (en) 2018-12-14 2018-12-14 Data communications with enhanced speed mode
PCT/US2019/039505 WO2020122989A1 (en) 2018-12-14 2019-06-27 Data communications with enhanced speed mode

Publications (4)

Publication Number Publication Date
JP2022510812A JP2022510812A (ja) 2022-01-28
JP2022510812A5 JP2022510812A5 (https=) 2022-06-27
JPWO2020122989A5 JPWO2020122989A5 (https=) 2022-06-27
JP7420804B2 true JP7420804B2 (ja) 2024-01-23

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JP2021527859A Active JP7420804B2 (ja) 2018-12-14 2019-06-27 改良された速度モードによるデータ通信

Country Status (6)

Country Link
US (2) US11151075B2 (https=)
EP (1) EP3895029B1 (https=)
JP (1) JP7420804B2 (https=)
KR (1) KR102865968B1 (https=)
CN (1) CN113196254B (https=)
WO (1) WO2020122989A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11151075B2 (en) * 2018-12-14 2021-10-19 Ati Technologies Ulc Data communications with enhanced speed mode
US11386026B1 (en) 2021-02-09 2022-07-12 Microsoft Technology Licensing, Llc Shell PCIe bridge and shared-link-interface services in a PCIe system
CN120336240B (zh) * 2025-06-20 2025-10-21 上海芯力基半导体有限公司 一种基于PCIe的高速数据传输方法、设备及系统

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JP2009065643A (ja) 2007-07-11 2009-03-26 Genesis Microchip Inc マルチメディアインターフェース
US20100103994A1 (en) 2006-12-13 2010-04-29 Frans Yohan U Interface With Variable Data Rate
US20140181355A1 (en) 2012-12-21 2014-06-26 Ati Technologies Ulc Configurable communications controller
US20150199822A1 (en) 2005-10-17 2015-07-16 Nvidia Corporation Pcie clock rate stepping for graphics and platform processors
US20170046302A1 (en) 2015-08-10 2017-02-16 Mediatek Inc. Method and associated interface circuit for mitigating interference due to signaling of a bus
US20180331864A1 (en) 2017-05-12 2018-11-15 Intel Corporation Bypassing equalization at lower data rates

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US7620062B2 (en) * 2003-05-01 2009-11-17 Genesis Microchips Inc. Method of real time optimizing multimedia packet transmission rate
US7426597B1 (en) * 2003-05-07 2008-09-16 Nvidia Corporation Apparatus, system, and method for bus link width optimization of a graphics system
US7461195B1 (en) * 2006-03-17 2008-12-02 Qlogic, Corporation Method and system for dynamically adjusting data transfer rates in PCI-express devices
US7660925B2 (en) * 2007-04-17 2010-02-09 International Business Machines Corporation Balancing PCI-express bandwidth
US8477831B2 (en) 2010-02-17 2013-07-02 Altera Corporation Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device
TWI408557B (zh) * 2010-03-18 2013-09-11 Faraday Tech Corp 高速輸入輸出系統及其節能控制方法
US9268732B2 (en) 2012-06-08 2016-02-23 Advanced Micro Devices, Inc. Tunnel suitable for multi-segment communication links and method therefor
US8972640B2 (en) * 2012-06-27 2015-03-03 Intel Corporation Controlling a physical link of a first protocol using an extended capability structure of a second protocol
JP6139689B2 (ja) * 2012-10-22 2017-05-31 インテル・コーポレーション 装置
US9692426B2 (en) * 2013-05-06 2017-06-27 Advanced Micro Devices, Inc. Phase locked loop system with bandwidth measurement and calibration
KR101995623B1 (ko) 2014-01-16 2019-07-02 인텔 코포레이션 고속 구성 메커니즘을 위한 장치, 방법, 및 시스템
US9825730B1 (en) 2016-09-26 2017-11-21 Dell Products, Lp System and method for optimizing link performance with lanes operating at different speeds
US20180173666A1 (en) 2016-12-16 2018-06-21 Intel Corporation APPARATUSES AND METHODS TO COUPLE AN EMBEDDED UNIVERSAL SERIAL BUS (eUSB) CIRCUIT TO A UNIVERSAL SERIAL BUS (USB) TRANSCEIVER INTERFACE CIRCUIT
US10789201B2 (en) 2017-03-03 2020-09-29 Intel Corporation High performance interconnect
US10545773B2 (en) * 2018-05-23 2020-01-28 Intel Corporation System, method, and apparatus for DVSEC for efficient peripheral management
US11151075B2 (en) * 2018-12-14 2021-10-19 Ati Technologies Ulc Data communications with enhanced speed mode

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US20150199822A1 (en) 2005-10-17 2015-07-16 Nvidia Corporation Pcie clock rate stepping for graphics and platform processors
US20100103994A1 (en) 2006-12-13 2010-04-29 Frans Yohan U Interface With Variable Data Rate
JP2009065643A (ja) 2007-07-11 2009-03-26 Genesis Microchip Inc マルチメディアインターフェース
US20140181355A1 (en) 2012-12-21 2014-06-26 Ati Technologies Ulc Configurable communications controller
JP2016506151A (ja) 2012-12-21 2016-02-25 エーティーアイ・テクノロジーズ・ユーエルシーＡｔｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｕｌｃ 構成可能な通信制御装置
US20170046302A1 (en) 2015-08-10 2017-02-16 Mediatek Inc. Method and associated interface circuit for mitigating interference due to signaling of a bus
US20180331864A1 (en) 2017-05-12 2018-11-15 Intel Corporation Bypassing equalization at lower data rates

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SOLOMON, Richard，Using CCIX to implement cache coherent heterogeneous multiprocessor systems，[online], Tech Design Forum，米国，2017年07月18日，[retrieved on 2023-06-16]. Retrieved from the Internet: <URL: https://www.techdesignforums.com/practice/technique/using-ccix-to-implement-cache-coherent-heterogeneous-multiprocessor-systems/>

Also Published As

Publication number Publication date
US20200192852A1 (en) 2020-06-18
EP3895029B1 (en) 2024-04-17
JP2022510812A (ja) 2022-01-28
CN113196254A (zh) 2021-07-30
US20220035765A1 (en) 2022-02-03
EP3895029A4 (en) 2022-09-07
CN113196254B (zh) 2025-03-11
WO2020122989A1 (en) 2020-06-18
KR102865968B1 (ko) 2025-09-29
US11151075B2 (en) 2021-10-19
EP3895029A1 (en) 2021-10-20
KR20210092230A (ko) 2021-07-23

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