JP7412161B2 - 基板処理装置及び基板処理方法 - Google Patents

基板処理装置及び基板処理方法 Download PDF

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JP7412161B2
JP7412161B2 JP2019231786A JP2019231786A JP7412161B2 JP 7412161 B2 JP7412161 B2 JP 7412161B2 JP 2019231786 A JP2019231786 A JP 2019231786A JP 2019231786 A JP2019231786 A JP 2019231786A JP 7412161 B2 JP7412161 B2 JP 7412161B2
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wafer
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peripheral
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JP2021100071A (ja
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隼斗 田之上
陽平 山脇
陽平 山下
征二 中野
弘明 森
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Tokyo Electron Ltd
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JP2021100071A5 JP2021100071A5 (https=) 2022-09-30
JP7412161B2 true JP7412161B2 (ja) 2024-01-12

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KR20240073916A (ko) * 2021-09-30 2024-05-27 도쿄엘렉트론가부시키가이샤 처리 방법 및 처리 시스템

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016004799A (ja) 2014-06-13 2016-01-12 株式会社ディスコ 貼り合わせウェーハ形成方法
JP2017055089A (ja) 2015-09-11 2017-03-16 株式会社東芝 半導体装置の製造方法
WO2019208298A1 (ja) 2018-04-27 2019-10-31 東京エレクトロン株式会社 基板処理システム及び基板処理方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016004799A (ja) 2014-06-13 2016-01-12 株式会社ディスコ 貼り合わせウェーハ形成方法
JP2017055089A (ja) 2015-09-11 2017-03-16 株式会社東芝 半導体装置の製造方法
WO2019208298A1 (ja) 2018-04-27 2019-10-31 東京エレクトロン株式会社 基板処理システム及び基板処理方法

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