JP7393088B2 - Ｕｓｂ２．０高速アプリケーションにおけるｄｃ損失の補償 - Google Patents

Ｕｓｂ２．０高速アプリケーションにおけるｄｃ損失の補償 Download PDF

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JP7393088B2
JP7393088B2 JP2020538839A JP2020538839A JP7393088B2 JP 7393088 B2 JP7393088 B2 JP 7393088B2 JP 2020538839 A JP2020538839 A JP 2020538839A JP 2020538839 A JP2020538839 A JP 2020538839A JP 7393088 B2 JP7393088 B2 JP 7393088B2
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coupled
input
output
data line
voltage threshold
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Japanese (ja)
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JP2021510874A (ja
JP2021510874A5 (https=
JPWO2019140246A5 (https=
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タン ヨンフイ
ファン ヤンリ
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テキサス インスツルメンツ インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0282—Provision for current-mode coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Information Transfer Systems (AREA)
JP2020538839A 2018-01-11 2019-01-11 Ｕｓｂ２．０高速アプリケーションにおけるｄｃ損失の補償 Active JP7393088B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862616201P 2018-01-11 2018-01-11
US62/616,201 2018-01-11
US15/967,883 US10733129B2 (en) 2018-01-11 2018-05-01 Compensating DC loss in USB 2.0 high speed applications
US15/967,883 2018-05-01
PCT/US2019/013271 WO2019140246A1 (en) 2018-01-11 2019-01-11 Compensating dc loss in usb 2.0 high speed applications

Publications (4)

Publication Number Publication Date
JP2021510874A JP2021510874A (ja) 2021-04-30
JP2021510874A5 JP2021510874A5 (https=) 2022-01-19
JPWO2019140246A5 JPWO2019140246A5 (https=) 2022-01-19
JP7393088B2 true JP7393088B2 (ja) 2023-12-06

Family

ID=67139849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020538839A Active JP7393088B2 (ja) 2018-01-11 2019-01-11 Ｕｓｂ２．０高速アプリケーションにおけるｄｃ損失の補償

Country Status (5)

Country Link
US (4) US10733129B2 (https=)
EP (1) EP3738043A4 (https=)
JP (1) JP7393088B2 (https=)
CN (2) CN111801660B (https=)
WO (1) WO2019140246A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11843376B2 (en) * 2021-05-12 2023-12-12 Gowin Semiconductor Corporation Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA)
US11689201B2 (en) 2021-07-26 2023-06-27 Qualcomm Incorporated Universal serial bus (USB) host data switch with integrated equalizer
US12003237B2 (en) * 2022-01-28 2024-06-04 Texas Instruments Incorporated Methods and apparatus for arc reduction in power delivery systems
US11764672B1 (en) * 2022-06-28 2023-09-19 Diodes Incorporated Signal boosting in serial interfaces
US12362717B2 (en) 2022-11-16 2025-07-15 Qualcomm Incorporated Second-order equalizer for high-speed data lines
US20240402739A1 (en) * 2023-06-02 2024-12-05 Texas Instruments Incorporated Methods and apparatus to compensate for ground shift

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110221521A1 (en) 2009-12-14 2011-09-15 Charles Razzell Active Eye Opener for Current-Source Driven, High-Speed Serial Links
US20150358011A1 (en) 2014-06-04 2015-12-10 Texas Instruments Incorporated Adaptive edge-rate boosting driver with programmable strength for signal conditioning
JP2016511568A (ja) 2013-01-24 2016-04-14 日本テキサス・インスツルメンツ株式会社 信号コンディショナー

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524291A (en) * 1983-01-06 1985-06-18 Motorola, Inc. Transition detector circuit
US6867631B1 (en) * 2003-04-18 2005-03-15 Apple Computer, Inc. Synchronous frequency convertor for timebase signal generation
US7161392B2 (en) * 2004-06-23 2007-01-09 Teradyne, Inc. Comparator feedback peak detector
JP4578316B2 (ja) * 2005-05-02 2010-11-10 ザインエレクトロニクス株式会社 送信装置
US8185682B2 (en) * 2007-06-01 2012-05-22 International Business Machines Corporation USB 2.0 bi-directional bus channel with boost circuitry
US7394281B1 (en) * 2008-01-31 2008-07-01 International Business Machines Corporation Bi-directional universal serial bus booster circuit
JP5730520B2 (ja) * 2010-09-03 2015-06-10 スパンション エルエルシー スイッチングレギュレータ
US8610456B2 (en) * 2011-09-23 2013-12-17 Qualcomm Incorporated Load detecting impedance matching buffer
US9483435B2 (en) * 2014-07-06 2016-11-01 Freescale Semiconductor, Inc. USB transceiver
US10002101B2 (en) * 2015-03-06 2018-06-19 Apple Inc. Methods and apparatus for equalization of a high speed serial bus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110221521A1 (en) 2009-12-14 2011-09-15 Charles Razzell Active Eye Opener for Current-Source Driven, High-Speed Serial Links
JP2016511568A (ja) 2013-01-24 2016-04-14 日本テキサス・インスツルメンツ株式会社 信号コンディショナー
US20150358011A1 (en) 2014-06-04 2015-12-10 Texas Instruments Incorporated Adaptive edge-rate boosting driver with programmable strength for signal conditioning

Also Published As

Publication number Publication date
JP2021510874A (ja) 2021-04-30
US12026115B2 (en) 2024-07-02
EP3738043A1 (en) 2020-11-18
US20200327082A1 (en) 2020-10-15
US20230039848A1 (en) 2023-02-09
CN118606248A (zh) 2024-09-06
CN111801660B (zh) 2024-10-18
US12517854B2 (en) 2026-01-06
US10733129B2 (en) 2020-08-04
US20190213158A1 (en) 2019-07-11
WO2019140246A1 (en) 2019-07-18
CN111801660A (zh) 2020-10-20
EP3738043A4 (en) 2021-02-24
US20240320178A1 (en) 2024-09-26

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