JP7364545B2 - アイソレータ - Google Patents
アイソレータ Download PDFInfo
- Publication number
- JP7364545B2 JP7364545B2 JP2020152253A JP2020152253A JP7364545B2 JP 7364545 B2 JP7364545 B2 JP 7364545B2 JP 2020152253 A JP2020152253 A JP 2020152253A JP 2020152253 A JP2020152253 A JP 2020152253A JP 7364545 B2 JP7364545 B2 JP 7364545B2
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- Prior art keywords
- electrode
- insulating
- insulating film
- film
- isolator
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- H—ELECTRICITY
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- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L2224/732—Location after the connecting process
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/273—Indexing scheme relating to amplifiers the DC-isolation amplifier, e.g. chopper amplifier, modulation/demodulation amplifier, uses inductive isolation means, e.g. transformers
Description
本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
(第1実施形態)
図1は、第1実施形態に係るアイソレータ100、第1回路1および第2回路2を表す平面図である。
図2は、第1実施形態に係るアイソレータ100を表す模式断面図である。図2は、図1中のA1-A2線に沿った断面図である。
図11は、第2実施形態に係るアイソレータ200を示す模式断面図である。アイソレータ200の第1電極11および第2電極12は、それぞれ平板状に設けられ、対向して配置される。第1電極11と第2電極12との間に設けられる第2絶縁部30は、空隙VA、VBおよびVCを含む。
図12は、第3実施形態に係るアイソレータ300、第1回路1および第2回路2を表す平面図である。アイソレータ300は、図1に示すアイソレータ100と同じ平面配置を有する。
図13は、第3実施形態に係るアイソレータ300の断面構造を表す模式図である。
図16は、図14のB1-B2断面図である。
図17は、第3実施形態の第1変形例に係るアイソレータ310の断面構造を表す模式図である。
図19は、第3実施形態の第2変形例に係るアイソレータ320の断面構造を表す模式図である。
図21は、第4実施形態に係るパッケージ400を表す斜視図である。
図22は、第4実施形態に係るパッケージ400の断面構造を表す模式図である。
Claims (8)
- 第1絶縁部と、
前記第1絶縁部中に設けられた第1電極と、
前記第1絶縁部および前記第1電極の上に設けられた第2絶縁部と、
前記第2絶縁部上に設けられた第3絶縁部と、
前記第3絶縁部中に設けられた第2電極と、
を備え、
前記第2絶縁部は、前記第1絶縁部と前記第2絶縁部との界面に平行な第1方向に並んだ複数の第1空隙と、前記複数の第1空隙の上方に設けられた第2空隙と、を含む、アイソレータ。 - 前記第2空隙は、前記複数の第1空隙のうちの少なくとも1つと連通するように設けられる請求項1記載のアイソレータ。
- 前記第2電極と前記第2絶縁部との間に設けられ、前記第2絶縁部の材料とは異なる材料を含む第1絶縁膜をさらに備える請求項1または2に記載のアイソレータ。
- 前記第2絶縁部は、前記第1絶縁部と前記第3絶縁部との間に延在する第3絶縁膜と、前記第1絶縁膜と前記第3絶縁部との間に延在する第4絶縁膜とを含み、
前記第3絶縁膜は、前記第1方向に並ぶ前記複数の第1空隙を含み、
前記第4絶縁膜は、前記第2空隙に囲まれた複数の島状領域を含む請求項3記載のアイソレータ。 - 前記複数の第1空隙は、前記第1方向と交差する第2方向に延在し、
前記第2空隙は、前記第1方向に延在する請求項1~3のいずれか1つに記載のアイソレータ。 - 前記第2絶縁部は、前記第1電極と前記複数の第1空隙との間に連続的に設けられた第2絶縁膜を含む請求項1~5のいずれか1つに記載のアイソレータ。
- 前記第2絶縁部は、前記第1絶縁部から前記第3絶縁部に向かう第3方向において、前記第1空隙のレベルと前記第2空隙のレベルとの間のレベルに設けられた第3空隙をさらに含み、
前記第1~第3空隙は、それぞれ四角形の形状を有し、
前記第3空隙は、前記四角形の四隅において前記第1空隙および前記第2空隙に連通するように設けられる請求項1~4のいずれか1つに記載のアイソレータ。 - 前記第1空隙および前記第2空隙は、前記第1方向と交差する第2方向に延在するスリット状に設けられる請求項1記載のアイソレータ。
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JP2017513222A (ja) | 2014-04-04 | 2017-05-25 | クアルコム,インコーポレイテッド | ウェハ反り低減のための応力軽減構造 |
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