JP7338258B2 - Bonding material evaluation method and evaluation test device - Google Patents

Description

The present invention relates to a bonding material evaluation method and an evaluation test apparatus for evaluating a bonding material for bonding a semiconductor chip and a substrate.

2. Description of the Related Art Conventionally, a power cycle test is performed in which a voltage is repeatedly applied to a semiconductor device to evaluate deterioration of each part. A semiconductor device used for such tests is formed through a wire bonding process, a sealing process using a sealing material, and the like after bonding a semiconductor chip to a substrate with a bonding material. For example, Patent Document 1 describes a semiconductor device in which wires are connected to a semiconductor chip.

JP-A-11-297929

Here, when a power cycle test is performed on the semiconductor device described above, the wire may break before the bonding material that bonds the semiconductor chip and the substrate deteriorates. was difficult.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a bonding material evaluation method capable of appropriately evaluating the deterioration of a bonding material that bonds a semiconductor chip and a substrate, and an evaluation test apparatus for performing an evaluation test of the deterioration of the bonding material. and

A bonding material evaluation method of the present invention is a bonding material evaluation method for evaluating deterioration of a bonding material in an evaluation body in which a semiconductor chip and a substrate are bonded by a bonding material. an installation step of installing the evaluation body in an installation space provided between the jig so that the semiconductor chip faces the first pressure jig and the substrate faces the second pressure jig; A pressurizing step of urging at least one of the first pressurizing jig and the second pressurizing jig by a pressurizing mechanism to sandwich and press the evaluation object between the first pressurizing jig and the second pressurizing jig. and a voltage application step of applying a voltage to the semiconductor chip of the evaluation body in a state of being pressurized by the pressurizing mechanism, and an evaluation step of evaluating deterioration of the bonding material after voltage application.

In this bonding material evaluation method, a voltage is applied to the semiconductor chip while the evaluation body is sandwiched between the first pressure jig and the second pressure jig. That is, in this bonding material evaluation method, since a voltage is applied in a state in which no wire is connected to the semiconductor chip, the wire does not affect the deterioration evaluation test of the bonding material. Therefore, this bonding material evaluation method can appropriately evaluate the deterioration of the bonding material that bonds the semiconductor chip and the substrate. In addition, in this bonding material evaluation method, the semiconductor chip or the like of the evaluation body is not sealed with a sealing material, and no wires are connected to the semiconductor chip. Therefore, an evaluation body for evaluating deterioration of the bonding material can be easily produced. In addition, since the semiconductor chip or the like is not sealed with a sealing material, it is not necessary to remove the sealing material when evaluating the deterioration of the bonding material, and the bonding material can be evaluated easily.

In the bonding material evaluation method, in the pressurizing step, the evaluation body may be pressurized with a pressure of 0.01 MPa or more and 10 MPa or less. In this case, the deterioration of the bonding material can be evaluated appropriately while suppressing the deterioration of the bonding material due to the pressure applied in the pressing step.

The bonding material evaluation method may further include a coating step of coating a portion of the bonding material's outer surface that is not covered with either the semiconductor chip or the substrate with an insulating material. For example, the exposure of the bonding material may affect the deterioration of the bonding material. Even in such a case, by coating the exposed parts of the bonding material with an insulating material, the deterioration caused by the exposure of the bonding material can be suppressed, It is possible to appropriately evaluate the deterioration of materials.

An evaluation test apparatus of the present invention is an evaluation test apparatus for performing an evaluation test of deterioration of a bonding material of an evaluation body in which a semiconductor chip and a substrate are bonded by a bonding material, and comprises a first pressure jig, a first a second pressure jig that is spaced apart from the first pressure jig and forms an installation space between the first pressure jig and the first pressure jig, in which the evaluation object can be installed; the first pressure jig; a pressurizing mechanism that urges at least one of the second pressurizing jigs to sandwich and press the evaluation object installed in the installation space between the first pressurizing jig and the second pressurizing jig; and a voltage application unit that applies a voltage to the semiconductor chip of the evaluation body that is in a state of being pressurized by the pressurizing mechanism.

According to this evaluation test apparatus, a voltage can be applied to the semiconductor chip while the evaluation body is sandwiched between the first pressure jig and the second pressure jig. That is, in this evaluation test apparatus, since a voltage is applied in a state in which no wire is connected to the semiconductor chip, the evaluation test of deterioration of the bonding material is not affected by the wire. Therefore, with this evaluation test apparatus, it is possible to appropriately perform an evaluation test of the deterioration of the bonding material that bonds the semiconductor chip and the substrate, and to appropriately evaluate the deterioration of the bonding material. In addition, in this evaluation test apparatus, the semiconductor chip or the like of the evaluation body is not sealed with a sealing material, and no wires are connected to the semiconductor chip. Therefore, an evaluation body for evaluating deterioration of the bonding material can be easily produced. In addition, since the semiconductor chip or the like is not sealed with a sealing material, it is not necessary to remove the sealing material when evaluating the deterioration of the bonding material, and the bonding material can be evaluated easily.

ADVANTAGE OF THE INVENTION According to this invention, deterioration of the joining material which joins a semiconductor chip and a board|substrate can be evaluated appropriately.

It is a sectional view showing a schematic structure of an evaluation object concerning an embodiment. It is a figure which shows schematic structure of an evaluation test apparatus. It is a flow chart which shows each process of a bonding material evaluation method.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference numerals, and overlapping descriptions are omitted.

In this embodiment, deterioration of the bonding material is evaluated using an evaluation body in which a semiconductor chip and a substrate are bonded with the bonding material.

<Evaluation body>
First, the evaluator will be explained. As shown in FIG. 1, the evaluation body 100 includes a semiconductor chip 101, a substrate 102, and a bonding material 103. As shown in FIG. As the semiconductor chip 101, for example, various semiconductor elements such as power semiconductors can be used. The semiconductor chip 101 in this embodiment has a first major surface 101a which is one of the outer surfaces of the semiconductor chip 101, and a second major surface 101b which is the outer surface opposite to the first major surface 101a. ing. Semiconductor chip 101 realizes various functions by applying a voltage between a first electrode provided on first main surface 101a and a second electrode provided on second main surface 101b.

The substrate 102 is a conductive substrate. The substrate 102 may be, for example, a plate member made of metal such as copper. As the substrate 102, in addition to a metal plate member, a substrate having a ceramic layer (insulating layer) in the middle such as a DBC substrate, or a substrate laminated with dissimilar metals such as a CIC substrate may be used. The surface of the substrate 102 may be plated with nickel or the like, for example.

The bonding material 103 bonds the second main surface 101 b of the semiconductor chip 101 and the substrate 102 . Also, the bonding material 103 electrically connects the second electrode provided on the second main surface 101b of the semiconductor chip 101 and the substrate 102 . In this embodiment, the bonding material 103 is subject to deterioration evaluation. Since the bonding material 103 mainly serves to bond the semiconductor chip 101 and the substrate 102 together, it can be called a bonding layer.

As the bonding material 103, a material that can bond the semiconductor chip 101 and the substrate 102 and has conductivity can be used. As the bonding material 103, for example, sintered metal such as sintered silver or sintered copper, solder, or the like can be used.

In addition, of the outer surface of the bonding material 103, a portion not covered by either the semiconductor chip 101 or the substrate 102 (that is, a portion exposed from the semiconductor chip 101 and the substrate 102) is coated with the insulating material 104. good too. When a material such as sintered copper that can cause surface oxidation is used as the bonding material 103 , surface oxidation of the exposed portion can be suppressed by coating with the insulating material 104 . This makes it possible to evaluate deterioration of the bonding material 103 while suppressing the influence of surface oxidation.

<Evaluation test equipment>
Next, an evaluation test apparatus for performing a deterioration evaluation test on the bonding material 103 of the evaluation body 100 will be described. This evaluation test for deterioration of the bonding material 103 is a test for evaluating deterioration of the bonding material 103 caused by repeated self-heating and cooling of the semiconductor chip 101 by applying a voltage to the semiconductor chip 101 . This evaluation test for deterioration of the bonding material 103 is a so-called power cycle test.

As shown in FIG. 2, the evaluation test device 1 includes an upper pressure jig (first pressure jig) 2, a lower pressure jig (second pressure jig) 3, a pressure mechanism 4, and a voltage applying section D. Note that FIG. 2 shows a state in which the evaluation body 100 is installed in the installation space R of the evaluation test apparatus 1 . Hereinafter, for convenience of explanation, the side on which the upper pressure jig 2 is arranged with respect to the lower pressure jig 3 will be referred to as the "upper" side, and the opposite side will be referred to as the "lower" side. However, the orientation of the evaluation test device 1 is not limited to this vertical orientation.

The upper pressure jig 2 and the lower pressure jig 3 are plate-like members, for example. The lower pressurizing jig 3 is provided at a position below the upper pressurizing jig 2 so as to be spaced apart from the upper pressurizing jig 2 . An installation space R in which the evaluation body 100 can be installed is formed between the upper pressurizing jig 2 and the lower pressurizing jig 3 . The evaluation body 100 is arranged in the installation space R such that the semiconductor chip 101 faces the upper pressure jig 2 side and the substrate 102 faces the lower pressure jig 3 side. That is, in this embodiment, the evaluation body 100 is placed on the upper surface of the lower pressure jig 3 with the semiconductor chip 101 facing upward.

The pressurizing mechanism 4 urges the upper pressurizing jig 2 toward the lower pressurizing jig 3 (downward). By urging the upper pressure jig 2, the pressure mechanism 4 sandwiches and presses the evaluation object 100 installed in the installation space R between the upper pressure jig 2 and the lower pressure jig 3. . The pressurizing mechanism 4 is configured by, for example, a spring in this embodiment.

The pressure mechanism 4 may press the evaluation body 100 with a pressure of 0.01 MPa or more, for example, from the viewpoint of appropriately pressing the upper electrode D1 and the like against the evaluation body 100 . For example, if the pressure mechanism 4 presses the evaluation body 100 too strongly, the bonding material 103 is less likely to come off, and the deterioration of the bonding material 103 cannot be evaluated correctly. Therefore, the pressure mechanism 4 may press the evaluation body 100 with a pressure of 10 MPa or less, for example, so as to suppress deterioration of the bonding material 103 . Further, when a sintered metal is used as the bonding material 103, from the viewpoint of preventing structural change (densification of the sintered metal) due to pressure and deterioration suppression (lifetime improvement) due to this structural change, for example, 10 MPa or less The evaluation body 100 may be pressurized with pressure.

In this embodiment, for example, a gate-shaped frame 9 is provided on the upper surface of the lower pressure jig 3 . The frame 9 includes a pair of pillars 9b rising from the upper surface of the lower pressure jig 3, and an upper frame 9a connecting the upper ends of the pair of pillars 9b. The upper end of the pressure mechanism 4 is in contact with the upper frame 9a. A lower end portion of the pressure mechanism 4 is in contact with the upper surface of the upper pressure jig 2 . Thereby, the pressurizing mechanism 4 can urge the upper pressurizing jig 2 downward. However, the configuration for the pressing mechanism 4 to urge the upper pressing jig 2 is not limited to the configuration using the frame 9 described above, and various configurations may be employed.

A rod 2 a extending in the vertical direction may be attached to the upper surface of the upper pressing jig 2 . The rod 2a is passed through a guide hole h provided in the upper frame 9a. Thereby, the rod 2a can guide the movement direction of the upper pressure jig 2 so that the upper pressure jig 2 moves along the vertical direction.

The voltage applying section D applies a voltage to the semiconductor chip 101 that is being pressed by the pressing mechanism 4 . The voltage application unit D repeatedly applies and stops applying voltage to the semiconductor chip 101 , thereby causing the semiconductor chip 101 to repeatedly generate heat and cool (radiate heat). In this embodiment, applying a voltage to the semiconductor chip 101 means that the first electrode provided on the first main surface 101a of the semiconductor chip 101 and the second electrode provided on the second main surface 101b of the semiconductor chip 101 are connected. is to apply a voltage between

Specifically, the voltage application section D includes an upper electrode D1, a lower electrode D2, and a power supply unit D3. In this embodiment, the upper electrode D1 becomes an anode and the lower electrode D2 becomes a cathode. The power supply unit D3 creates a potential difference between the upper electrode D1 and the lower electrode D2. The position where the power supply unit D3 is provided is not particularly limited.

The upper electrode D<b>1 is arranged between the semiconductor chip 101 of the evaluation body 100 and the upper pressing jig 2 . In this embodiment, an insulator 5 is arranged between the upper electrode D1 and the upper pressure jig 2 so that current does not flow from the upper electrode D1 to the upper pressure jig 2 and the pressure mechanism 4 side. there is Examples of the insulator 5 include insulating glass, polyimide sheet, polyimide film, silicone rubber, ceramic substrate, and the like.

Further, in this embodiment, a conductive spacer 6 may be provided between the semiconductor chip 101 and the upper electrode D1. The spacer 6 prevents the upper electrode D1 from coming into contact with an unintended portion (for example, the substrate 102 or the like) and short-circuiting. As the spacer 6, for example, a conductive material such as molybdenum can be used. A buffer layer 7 may be interposed between the spacer 6 and the semiconductor chip 101 . The buffer layer 7 prevents the spacer 6 from coming into contact with the semiconductor chip 101 (only a portion of the lower surface of the spacer 6 comes into contact with the semiconductor chip 101). As the buffer layer 7, for example, a conductive material such as a silver sheet can be used. Thus, the upper pressing jig 2 presses the evaluation object 100 through the insulator 5, the upper electrode D1, the spacer 6, and the buffer layer 7. FIG.

The lower electrode D2 is in contact with the upper surface of the substrate 102 . Therefore, in a state where the evaluation object 100 is pressed between the upper pressure jig 2 and the lower pressure jig 3 by the pressure mechanism 4, the power supply unit D3 is operated to press the upper electrode D1 and the lower electrode D2. A voltage is applied to the semiconductor chip 101 by creating a potential difference therebetween. That is, the current supplied by the power supply unit D3 flows from the upper electrode D1 through the spacer 6, the buffer layer 7, the semiconductor chip 101, the bonding material 103, and the substrate 102 to the lower electrode D2. Also, the power supply unit D3 repeatedly applies and stops applying voltage to the semiconductor chip 101 . In this manner, the evaluation test apparatus 1 performs an evaluation test for deterioration of the bonding material 103 of the evaluation body 100 .

The voltage value applied to the semiconductor chip 101 by the voltage applying unit D can be appropriately set according to various conditions such as the properties of the bonding material 103 to be evaluated. Similarly, the period of voltage application to the semiconductor chip 101 (on-off period) can be appropriately set according to various conditions such as the properties of the bonding material 103 to be evaluated.

The evaluation test apparatus 1 may include a cooling section 8 that cools the heat generated in the evaluation body 100 . In this embodiment, the cooling part 8 is provided on the lower surface of the lower pressure jig 3, for example. Inside the cooling unit 8, for example, a cooling pipe 8a through which a coolant flows is provided. Various mechanisms can be adopted as the mechanism for cooling in the cooling unit 8 .

If an insulating layer is not provided on the outer surface of the substrate 102 (the surface in contact with the lower pressure jig 3), for example, an insulating layer may be formed between the substrate 102 and the lower pressure jig 3 in order to prevent short circuits. Alternatively, an insulating layer may be provided on the outer surface of the lower pressure jig 3 or between the lower pressure jig 3 and the cooling section 8 .

<Procedure of bonding material evaluation method>
Next, a procedure of a bonding material evaluation method for evaluating deterioration of the bonding material 103 of the evaluation body 100 will be described. As shown in FIG. 3, first, a semiconductor chip 101 and a substrate 102 are bonded with a bonding material 103 to produce an evaluation body 100 (S101: evaluation body manufacturing step). Then, the portions where the bonding material 103 is exposed from the semiconductor chip 101 and the substrate 102 are coated with the insulating material 104 (S102: coating step). However, the step of coating with the insulating material 104 is not an essential step.

Next, the fabricated evaluation body 100 is installed in the installation space R so that the semiconductor chip 101 faces the upper pressure jig 2 side and the substrate 102 faces the lower pressure jig 3 side (S103 : installation process). The upper pressurizing jig 2 is urged by the pressurizing mechanism 4, and the evaluation body 100 is sandwiched and pressurized by the upper pressurizing jig 2 and the lower pressurizing jig 3 (S104: pressurizing step).

The voltage application unit D applies a voltage to the semiconductor chip 101 of the evaluation body 100 in a pressurized state (S105: voltage application step). Here, the voltage application unit D repeatedly applies and stops applying voltage to the semiconductor chip 101 . After applying the voltage, deterioration of the bonding material 103 of the evaluation body 100 is evaluated (S106: evaluation step). Here, for example, the evaluation body 100 is removed from the evaluation test apparatus 1, and peeling of the bonding material 103 from the semiconductor chip 101 or the substrate 102 is evaluated as deterioration of the bonding material 103. FIG. As the evaluation of the deterioration of the bonding material 103, various events other than peeling can be evaluated.

As described above, according to the bonding material evaluation method and evaluation test apparatus 1, a voltage is applied to the semiconductor chip 101 while the evaluation body 100 is sandwiched between the upper pressure jig 2 and the lower pressure jig 3. be done. That is, in this bonding material evaluation method and evaluation test apparatus 1, since a voltage is applied in a state in which no wire is connected to the semiconductor chip 101, the deterioration evaluation test of the bonding material 103 is not affected by the wire. . Therefore, the bonding material evaluation method and evaluation test apparatus 1 can appropriately evaluate the deterioration of the bonding material 103 that bonds the semiconductor chip 101 and the substrate 102 together. Moreover, in the evaluation body 100 used in the bonding material evaluation method and the evaluation test apparatus 1, the semiconductor chip 101 and the like are not sealed with a sealing material, and the semiconductor chip 101 is not connected to wires. Therefore, the evaluation body 100 for evaluating the deterioration of the bonding material 103 can be easily manufactured, and the time required for manufacturing can be shortened. In addition, since the semiconductor chip 101 and the like are not sealed with a sealing material, there is no need to remove the sealing material when evaluating the deterioration of the bonding material 103, and the bonding material 103 can be evaluated easily. .

The pressurizing mechanism 4 can press the evaluation object 100 with a pressure of 0.01 MPa or more and 10 MPa or less in the pressurizing step. In this case, deterioration of the bonding material 103 can be evaluated appropriately while suppressing the deterioration of the bonding material 103 due to pressurization.

A portion of the outer surface of the bonding material 103 that is not covered with either the semiconductor chip 101 or the substrate 102 may be coated with the insulating material 104 . For example, the exposure of the bonding material 103 may affect the deterioration of the bonding material 103 . Even in such a case, since the exposed portion of the bonding material 103 is coated with the insulating material 104, the influence of deterioration caused by the exposure of the bonding material 103 is suppressed. In addition, the deterioration of the bonding material 103 can be evaluated appropriately.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, the pressure mechanism 4 is not limited to a configuration including a spring. The evaluation body 100 may be pressurized. Various configurations can be adopted as the configuration of the pressurizing mechanism 4 for pressurizing the evaluation body 100 .

In addition, the pressurizing mechanism 4 urges the upper pressurizing jig 2 toward the lower pressurizing jig 3 side, but urges the lower pressurizing jig 3 toward the upper pressurizing jig 2 side. Alternatively, the upper pressure jig 2 and the lower pressure jig 3 may be biased so that they approach each other. That is, the pressurizing mechanism 4 only needs to be able to pressurize the evaluation object 100 installed in the installation space R by urging at least one of the upper pressurizing jig 2 and the lower pressurizing jig 3 .

Further, for example, the upper pressing jig 2 may also function as the upper electrode D1. In this case, the upper pressure jig 2 as the upper electrode and the lower electrode D2 are not short-circuited through the rod 2a, the frame 9, the lower pressure jig 3, etc. without passing through the evaluation body 100. An insulating material may be provided at the position of . The lower electrode D2 may be provided on a portion other than the upper surface of the substrate 102 as long as a voltage can be applied to the semiconductor chip 101 of the evaluation body 100 with the upper electrode D1.

At least some of the embodiments described above may be combined arbitrarily.

DESCRIPTION OF SYMBOLS 1... Evaluation test apparatus, 2... Upper side pressure jig, 3... Lower side pressure jig, 4... Pressure mechanism, 100... Evaluation body, 101... Semiconductor chip, 102... Substrate, 103... Bonding material, 104... Insulating material, D... Voltage application part.

Claims (7)

A bonding material evaluation method for evaluating deterioration of the bonding material of an evaluation body in which a semiconductor chip and a substrate are bonded by the bonding material,
The semiconductor chip is placed in an installation space provided between the first surface of the first pressure jig and the second surface of the second pressure jig and opposite to the first surface. an installation step of installing the evaluation body so that it faces the side of one pressure jig and the substrate faces the side of the second pressure jig;
At least one of the first pressure jig and the second pressure jig is biased by a pressure mechanism to sandwich the evaluation body between the first pressure jig and the second pressure jig. A pressurization step of pressurizing with
a voltage application step of repeatedly applying and stopping voltage application to the semiconductor chip of the evaluation body in a state of being pressurized by the pressurizing mechanism;
an evaluation step of evaluating deterioration of the bonding material after voltage application;
Bonding material evaluation method. The bonding material evaluation method according to claim 1, wherein in the pressurizing step, the evaluation body is pressurized with a pressure of 0.01 MPa or more and 10 MPa or less. 3. The bonding material evaluation method according to claim 1, further comprising a coating step of coating a portion of the outer surface of said bonding material that is not covered with either said semiconductor chip or said substrate with an insulating material. In the voltage application step,
applying a voltage to the semiconductor chip via an electrode arranged between the first pressure jig and the semiconductor chip;
Alternatively, the bonding material evaluation method according to any one of claims 1 to 3, wherein a voltage is applied to the semiconductor chip through the conductive first pressure jig. The bonding evaluation method according to any one of claims 1 to 4, wherein in the evaluation step, deterioration of the bonding material is evaluated in a state in which pressure by the pressure mechanism is released after the voltage is applied. An evaluation test apparatus for performing an evaluation test of deterioration of a bonding material of an evaluation body in which a semiconductor chip and a substrate are bonded by the bonding material,
a first pressure jig;
a second pressurizing jig that is spaced apart from the first pressurizing jig and that forms an installation space between the first pressurizing jig and the first pressurizing jig in which the evaluation body can be installed;
By urging at least one of the first pressure jig and the second pressure jig, the semiconductor chip faces the first pressure jig and the substrate moves toward the second pressure jig. a pressurizing mechanism that sandwiches and presses the evaluation body installed in the installation space so as to face the tool side with the first pressurizing jig and the second pressurizing jig;
a voltage applying unit that repeatedly applies and stops applying a voltage to the semiconductor chip of the evaluation body that is in a state of being pressurized by the pressurizing mechanism;
The installation space is provided between a first surface of the first pressure jig and a second surface of the second pressure jig that faces the first surface. The voltage application unit is
an electrode disposed between the first pressure jig and the semiconductor chip, and applying a voltage to the semiconductor chip through the electrode;
7. The evaluation test apparatus according to claim 6 , wherein a voltage is applied to said semiconductor chip via said first pressure jig having conductivity.

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