JP2007273661A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high thermal resistance against a heat cycle from a temperature not higher than a freezing point to a high temperature of not lower than 100°C, concerning a semiconductor device which is equipped with and constituted of a semiconductor element in the desired place of a metallic circuit substrate by joining a circuit substrate composed of a metal plate to a ceramic substrate. <P>SOLUTION: An Mo material 4a is arranged immediately under the semiconductor element 3, and also a Cu material 4b is arranged in the joint of the element. By this constitution, the Mo material suppresses the plane direction expansion of the Cu material with respect to the element between the metallic circuit substrate 2 and the semiconductor element. Since the Cu material softer than the Mo material is arranged on a joint surface so as to mitigate stress on the joint. Thus, mounting with high thermal resistance and high strength is enabled. The cylindrical Mo material arranged to constrain the Cu material in the joint immediately under the element is adopted as a stress mitigating mechanism having the same operation effect. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a novel structure of a heat dissipation board in a semiconductor device having a structure in which a circuit board made of a metal plate is bonded to a ceramic substrate and a semiconductor element is mounted on the metal circuit board. Mo is placed at the junction with the metal circuit board, and the junction between the ceramic substrate and the metal circuit board is configured in the same way, with high heat resistance that can withstand heat cycle tests at temperatures above 100 ° C, for example, below 300 ° C. The present invention relates to a semiconductor device capable of exhibiting performance.

  Circuit boards made of metal plates are joined to ceramic substrates for various power modules such as IGBTs and switching power supplies used in inverter control of electric vehicles, hybrid vehicles using internal combustion engines and motors, fuel cell vehicles, etc. Is used as a metal circuit board by etching or the like, and a semiconductor device (Patent Document 1) having a structure in which a semiconductor element is directly attached to the metal circuit board is used.

Semiconductor devices used for the above applications are required to have a high boosted voltage and switching frequency in order to improve the output to be taken out. In order to obtain high heat resistance, the above structure in which the metal circuit board and the semiconductor element are directly placed on the ceramic substrate is adopted.
JP2005-005404 JP2004-343035 JP 05-226527

  When the semiconductor device having such a configuration is used in an automobile, depending on the environment, it is assumed that a heat cycle in a wide range of several tens of degrees Celsius to 300 ° C. is repeatedly received. Therefore, each joint is required to have high heat resistance that can withstand this heat cycle.

  The joints between the ceramic substrate and the metal circuit board, and between the metal circuit board and the semiconductor element must be mounted with high heat resistance and strength that can be used at high temperatures of 100 ° C or higher, and will not peel off in severe heat cycles Bonding that satisfies such conflicting conditions is also required because a stress relaxation mechanism is also required so that cracks do not occur in the joint due to the difference in thermal expansion coefficient from the bonding partner material, while also requiring high bonding strength. A structure is needed.

  The present invention can be used at a high temperature of 100 ° C. or higher in a semiconductor device having a structure in which a circuit board made of a metal plate is bonded to a ceramic substrate and a semiconductor element is mounted on a required portion of the metal circuit board. The purpose is to provide a semiconductor device having high heat resistance that can withstand a heat cycle test at 300 ° C. from below freezing point.

  As a result of intensive studies on the junction structure between the metal circuit board and the semiconductor element in order to achieve high heat resistance and high strength mounting in a temperature range of 100 ° C. or higher in the above semiconductor device, Between the metal circuit board and the semiconductor element, the Mo material is in the plane direction of the Cu material with respect to the element. It was found that expansion can be suppressed, and the stress applied to the joint can be relaxed by having a soft Cu material on the joint surface compared to the Mo material, enabling high heat resistance and high strength mounting.

  In addition, the inventors have disclosed a stress relaxation mechanism in which a Cu material is disposed at a joint portion of the semiconductor element and a Mo material is disposed immediately below the element. It has been found that the stress generated at the joint between the metal circuit board and the semiconductor element can be relieved by the same action and effect even if the Cu material is arranged to constrain, for example, a cylindrical Mo material.

  Furthermore, in addition to the joint structure between the metal circuit board and the semiconductor element described above, the joint part between the ceramic substrate and the metal circuit board has the same configuration, that is, the joint part between the ceramic substrate immediately below the semiconductor element is a Cu material, This Cu material has been found to be able to improve the high heat resistance of the entire semiconductor device by adopting a structure in which a Mo material is arranged and connected to a Cu or Al metal circuit board, and the present invention has been completed.

  That is, the present invention is a semiconductor device having a structure in which a circuit board made of a metal plate is bonded onto a ceramic substrate and a semiconductor element is attached to a required portion of the metal circuit board. The upper clad material in which the Mo layer and the Cu layer are laminated is interposed so that the Cu layer is in contact with the element.

  In the present invention, a plate-like two-layer upper clad material of a Mo layer and a Cu layer is disposed at a junction between a metal circuit board and a semiconductor element so that the Cu layer is in contact with the element side and the Mo layer is in contact with the circuit board. Alternatively, an annular upper clad material in which the Cu layer is in contact with the element side and the Mo layer is in contact with the outer periphery of the Cu layer directly below the element in a part or all around is arranged.

  Further, the present invention provides a semiconductor device having the above-described structure, in which a Cu layer is in contact with the ceramic substrate and a Mo layer is in contact with the circuit substrate at a joint portion between the ceramic substrate and the metal circuit substrate immediately below the semiconductor element. A semiconductor device is characterized in that a plate-like two-layer lower clad material with a Cu layer is disposed.

  According to the present invention, at the joint between the metal circuit board and the semiconductor element, the stress generated at the joint can be relieved to maintain a strong joint, and the joint between the ceramic substrate directly below the semiconductor element and the metal circuit board can also be maintained. Similarly, it is possible to relieve the stress generated in the same part and maintain strong bonding. Therefore, according to the present invention, it is possible to provide a semiconductor device that requires high heat resistance and high strength mounting in a temperature range of 100 ° C. to 400 ° C.

  According to the present invention, when manufacturing a semiconductor device, it is possible to join by brazing that does not require Ni plating, and the ceramic substrate, metal circuit board, semiconductor element, upper clad material, lower clad material Assembling can be completed by one-time joining by selecting any one or a plurality of joints and joining them by brazing or by brazing all the parts.

  According to the present invention, by employing brazing, the upper clad material can be locally disposed only at the semiconductor chip mounting portion, and the amount of Mo used can be minimized. Furthermore, by using a high melting point brazing material such as a Cu-based brazing material for the brazing material, it is possible to provide a semiconductor device having excellent thermal conductivity and electrical characteristics of the joint.

  In the present invention, the configuration of the semiconductor device may be any configuration as long as a circuit board made of a metal plate is bonded to a ceramic substrate and a semiconductor element is attached to a required portion of the metal circuit board.

As the ceramic substrate, SiN, AlN, Al ₂ O ₃ , SiC, Si ₃ N _{4 and the} like can be adopted. In particular, Si ₃ N ₄ can be expected to have high strength.

  For metal circuit boards, materials with excellent conductivity such as Cu, Al, Ag, Au can be adopted. In particular, Cu has low electrical resistance and various thicknesses are readily available, and Al has electrical resistance. It is convenient that low Al wire bonding is easy.

  As the semiconductor element, Si, SiC, GaN, GaAs or the like can be adopted, and SiC having excellent heat resistance is particularly suitable.

  In the present invention, an upper clad material having a structure in which a Mo layer and a Cu layer are disposed so that a Cu layer is in contact with the semiconductor element 3 at the junction between the metal circuit board 2 and the semiconductor element 3 provided on the ceramic substrate 1 For example, as shown in FIG. 1A, the upper clad material 4 having a plate-like two-layer structure of a Mo layer and a Cu layer so that the Cu layer is in contact with the semiconductor element 3 side and the Mo layer is in contact with the metal circuit board 2 as shown in FIG. In addition, as shown in FIG. 2A, the upper cladding of the annular structure (ring structure) configured such that the Cu layer is in contact with the semiconductor element 3 side and the Mo layer is in contact with the outer peripheral side of the Cu layer immediately below the element 3 The configuration of material 6 can be adopted.

  As the structure of the upper clad material in which the Mo layer and the Cu layer are laminated, the upper clad material can be easily joined by pressure welding, an Ag-based brazing material, or a Cu-based brazing material. The pressure welding method is not particularly limited, but Cu and Mo materials are prepared so as to have a required plate thickness ratio, and these are combined and pressed so that the reduction ratio is, for example, 60 to 80%, and then diffused. An annealing treatment, for example, a method of holding at 900 ° C. to 1000 ° C. for 1 to 10 minutes can be employed.

  Although it does not specifically limit as Ag type brazing material and Cu type brazing material composition, Sn-Cu material is excellent in adhesive strength, for example as Cu type brazing material composition, and joining property and handling are easy. As composition, 1-13 mass% Sn-Cu material is preferable, especially 2-7 mass% Sn-Cu material has a high melting point (970 ° C-890 ° C) and thermal conductivity (230 W / mK or more). It is more preferable because it is high.

  The structure of the clad material in which the Cu layer is in contact with the element side and the Mo layer is in contact with the outer peripheral side of the Cu layer directly below the element in a ring shape around the entire circumference is easily joined with an Ag-based brazing material or a Cu-based brazing material. be able to. The brazing material composition is not particularly limited, but the above-described Sn-Cu material is preferable as the Cu-based brazing material composition.

In the laminated upper clad material, the thickness ratio of the Mo layer and the Cu layer is not particularly limited, but Mo is preferably 20% to 80% of the total thickness.
In addition, in the clad material in which the Mo layer is annularly in contact with the outer peripheral side of the Cu layer directly below the element, the thickness of the Mo in the planar direction is not particularly limited, but Mo is configured to be aligned with Mo-Cu-Mo. % To 80% is preferable.

  In the present invention, as shown in FIGS.1B and 2B, the bonding portion between the ceramic substrate 1 and the metal circuit substrate 2 directly below the semiconductor element 3 is such that the Cu layer is in contact with the ceramic substrate 1 and the Mo layer is connected to the circuit substrate 2. A configuration in which the lower clad material 5 having a two-layer structure of a Mo layer and a Cu layer is disposed so as to be in contact with each other can be adopted.

  As a configuration of the lower clad material for laminating the Mo layer and the Cu layer, it can be easily joined by pressure welding, an Ag-based brazing material, or a Cu-based brazing material. The pressure welding method and the brazing material composition are not particularly limited, but as the pressure welding method, not only the Mo layer and the Cu layer, but also the Cu, Al, Ag, Au, etc. constituting the metal circuit after that are pressed. In addition to the metal layer being further formed by pressure welding, sputtering or plating, the metal layer, the Mo layer, and the Cu layer can be simultaneously pressured in advance to obtain a required thickness.

The brazing material composition for laminating the Mo layer and Cu layer of the lower clad material is not particularly limited, but the above-mentioned Sn—Cu material is preferable as the Cu-based brazing material composition.
In addition, in the case of a configuration in which the lower clad material is joined with a brazing material, the above Sn-Cu material is preferable as a Cu-based brazing material composition for joining with the metal layer constituting the metal circuit.

  Further, in the joint part between the ceramic substrate and the metal circuit substrate, the thickness ratio of the Mo layer and the Cu layer of the lower clad material is not particularly limited, but Mo is 20% to 80% of the total thickness. Preferably there is.

  In the present invention, each of the bonding of the semiconductor element and the upper cladding material, the bonding of the upper cladding material and the metal circuit layer of the metal circuit board, and the bonding of the lower cladding material and the ceramic substrate may be performed by using known solder or High melting point brazing material can be used. Examples of high melting point brazing filler metals include Ag-Sn, Ag-Cu, Sn-Cu, Al-Si, Au-Sn, Au-Si, various high heat resistant metal pastes and nano metal pastes. is there. Since these high melting point brazing filler metals generally have higher strength than solder, it is considered that the effect of stress relaxation of Cu employed in the present invention appears more remarkably.

Example 1
As a configuration of the semiconductor device of the example shown in FIG. 1A, a metal circuit board 2 of Cu foil formed by rolling with a thickness of 300 μm provided in a required pattern on a ceramic substrate 1 of a Si ₃ N ₄ plate, and a semiconductor element 3 made of SiC A structure is adopted in which the upper clad material 4 having a two-layer structure having a thickness of 200 μm is interposed and joined by rolling and welding the Mo material and the Cu material.

  First, a Cu-based brazing material (3Sn-Cu) with a thickness of 50 μm is placed on the ceramic substrate 1 and a 300 μm-thick Cu foil material is placed and bonded and laminated, and then the required pattern is formed by etching. Thus, a metal circuit board 2 was obtained.

  Next, in order to place the semiconductor element 3 at a required position on the metal circuit board 2, the upper clad material 4 having a two-layer structure was interposed and joined. Between the metal circuit board 2 and the Mo layer 4a of the upper clad material 4, a Cu-based brazing material (3Sn—Cu) foil having a thickness of 50 μm was disposed and the upper clad material 4 was laminated. Further, a brazing material foil (80Au—Sn) having a thickness of 50 μm was placed on the Cu layer 4b of the upper clad material 4, and the semiconductor element 3 was placed and bonded thereto.

  Using the obtained semiconductor device having the configuration shown in FIG. 1A, it was subjected to a heat cycle test (A test, B test). As a result, no defects such as peeling were observed in all the joints in both the A test and the B test.

  In the heat cycle test, the atmosphere is heated from -40 ° C to 120 ° C (A test) or 350 ° C (B test) first from room temperature to 120 ° C or 350 ° C, and then released from the high temperature to normal temperature. The process of cooling down to a low temperature of -40 ° C., leaving the low temperature to return to room temperature continuously is defined as one cycle, which is continuously or intermittently, 10,000 cycles for the A test and 100 cycles for the B test. It was performed under the condition of repeating 1,000 cycles.

Example 2
As the configuration of the semiconductor device of the embodiment shown in FIG. 1B, the Mo material and the metal circuit board 2 of Cu foil formed by rolling with a thickness of 300 μm provided in a required pattern on the ceramic substrate 1 of the Si ₃ N ₄ plate, The lower clad material 5 having a two-layer structure of 150 μm in thickness is interposed by rolling and welding the Cu material, and the Mo material is also present at the joint between the metal circuit board 2 and the semiconductor element 3 made of SiC. A structure was adopted in which an upper cladding material 4 having a two-layer structure having a thickness of 150 μm was interposed and rolled by pressure welding with a Cu material.

  A Cu-based brazing material (2Sn-Cu) foil having a thickness of 50 μm is disposed on the ceramic substrate 1, and the lower clad material 5 of the two-layer structure is placed thereon, and a Cu-based brazing material (2Sn-Cu) having a thickness of 50 μm is further placed. ) A foil was placed, a 300 μm thick Cu foil material was placed, and these were simultaneously bonded and laminated. Then, a required pattern was formed by etching to form a metal circuit board 2.

  Next, in order to place the semiconductor element 3 at a required position of the metal circuit board 2, the upper clad material 4 having the two-layer structure was interposed and joined. First, the upper clad material 4 was laminated by arranging a 50 μm thick Cu-based brazing material (2Sn—Cu) foil between the metal circuit board 2 and the Mo layer 4a of the upper clad material 4. Further, a brazing material (80Au—Sn) foil having a thickness of 50 μm was placed on the Cu layer 4b of the upper clad material 4, and the semiconductor element 3 was placed and bonded thereto.

  The obtained semiconductor device shown in FIG. 1B was used for the heat cycle test of Example 1. As a result, no defects such as peeling were observed in all the joints in both the A test and the B test.

Example 3
2A, as a configuration of the semiconductor device of the embodiment shown in FIG. 2A, a metal circuit board 2 made of Cu foil by rolling with a thickness of 300 μm provided in a required pattern on a ceramic substrate 1 made of Si ₃ N ₄ plate, and a semiconductor element 3 made of SiC An annular upper clad material 6 having a structure in which a Cu layer 6b having a thickness of 200 μm is in contact with the element 3 and a Mo layer 6a is press-contacted to the outer peripheral side of the Cu layer 6b immediately below the element 3 is interposed and joined to the joint portion The configuration is adopted.

  First, a Cu-based brazing material (3Sn-Cu) with a thickness of 50 μm is placed on the ceramic substrate 1 and a 300 μm-thick Cu foil material is placed and bonded and laminated, and then the required pattern is formed by etching. Thus, a metal circuit board 2 was obtained.

  Next, in order to place the semiconductor element 3 at a required position of the metal circuit board 2, the annular upper clad material 6 was interposed and joined. Between the metal circuit board 2 and the annular Mo layer 6a and the Cu layer 6b of the annular upper clad material 6, a Cu-based brazing material (3Sn—Cu) foil having a thickness of 50 μm was disposed to laminate the annular upper clad material 6. Furthermore, a brazing material foil (80Au—Sn) having a thickness of 50 μm was placed on the Cu layer 6b of the annular upper clad material 6, and the semiconductor element 3 was placed and bonded thereto.

  The obtained semiconductor device having the configuration shown in FIG. 2A was used for a heat cycle test (A test, B test). As a result, no defects such as peeling were observed in all the joints in both the A test and the B test.

Example 4
As a configuration of the semiconductor device of the embodiment shown in FIG. 2B, a Mo material and a Cu foil metal circuit board 2 formed by rolling with a thickness of 300 μm provided in a required pattern on a ceramic substrate 1 of a Si ₃ N ₄ plate, The lower clad material 5 having a two-layer structure having a thickness of 150 μm is interposed by rolling and welding the Cu material, and the thickness of the junction between the metal circuit board 2 and the semiconductor element 3 made of SiC is also thick. A configuration in which a 200 μm Cu layer 6b is in contact with the element 3 and an annular upper clad material 6 having a structure in which the Mo layer 6a is press-contacted to the outer peripheral side of the Cu layer 6b immediately below the element 3 is employed.

  A Cu-based brazing material (2Sn-Cu) foil having a thickness of 50 μm is disposed on the ceramic substrate 1, and the lower clad material 5 of the two-layer structure is placed thereon, and a Cu-based brazing material (2Sn-Cu) having a thickness of 50 μm is further placed. ) A foil was placed, a 300 μm thick Cu foil material was placed, and these were simultaneously bonded and laminated. Then, a required pattern was formed by etching to form a metal circuit board 2.

  Next, in order to place the semiconductor element 3 at a required position on the metal circuit board 2, the annular upper clad material 6 was interposed and joined. Between the metal circuit board 2 and the annular Mo layer 6a and the Cu layer 6b of the annular upper cladding member 6, a Cu-based brazing filler metal (2Sn—Cu) foil having a thickness of 50 μm was disposed and the annular upper cladding member 6 was laminated. Furthermore, a brazing material foil (80Au—Sn) having a thickness of 50 μm was placed on the Cu layer 6b of the annular upper clad material 6, and the semiconductor element 3 was placed and bonded thereto.

  The obtained semiconductor device shown in FIG. 1B was used for the heat cycle test of Example 1. As a result, no defects such as peeling were observed in all the joints in both the A test and the B test.

  The semiconductor device according to the present invention is used in various power modules such as IGBTs and switching power supplies used for inverter control of electric vehicles, hybrid vehicles using internal combustion engines and motors, fuel cell vehicles, etc., for example, 120 ° C. or 350 ° C. from below freezing point. Demonstrates high heat resistance to withstand high-load thermal tests that repeat the heat cycle.

FIG. 1A is an explanatory diagram showing a configuration of an embodiment using an upper clad material having a two-layer structure of a semiconductor device of the present invention, and FIG. 1B is an explanatory diagram showing a configuration of an embodiment using an upper clad material and a lower clad material having a two-layer structure. . FIG. 2A is an explanatory view showing a configuration of an embodiment using an annular upper cladding material of the semiconductor device of the present invention, and FIG. 2B is an explanatory diagram showing a configuration of an embodiment using an annular upper cladding material and a two-layer lower cladding material.

Explanation of symbols

1 Ceramic substrate
2 Metal circuit board
3 Semiconductor elements
4 Upper cladding material
4a, 6a Mo layer
4b, 6b Cu layer
5 Lower clad material
6 Annular upper clad material

Claims (8)

A semiconductor device having a structure in which a metal circuit board is bonded onto a ceramic substrate and a semiconductor element is attached to a required portion of the metal circuit board, and a Cu layer is disposed between the metal circuit board and the semiconductor element on the element side A semiconductor device in which a two-layer upper clad material of a Mo layer and a Cu layer is interposed and fixed so that the Cu layer is in contact with the element so that the Mo layer is in contact with the circuit board. A semiconductor device having a structure in which a metal circuit board is bonded onto a ceramic substrate and a semiconductor element is attached to a required portion of the metal circuit board, and a Cu layer is disposed between the metal circuit board and the semiconductor element on the element side Device in which an annular upper clad material is disposed and fixed so that the Mo layer is in contact with the outer peripheral side of the Cu layer directly below the element. At the joint between the ceramic substrate directly below the semiconductor element and the metal circuit board, a two-layer lower clad material of the Mo layer and the Cu layer is disposed and fixed so that the Cu layer is in contact with the ceramic substrate and the Mo layer is in contact with the circuit board. The semiconductor device according to claim 1 or 2. 4. The semiconductor device according to claim 1, wherein the upper clad material is interposed and fixed only at a joint portion of the semiconductor element. 4. The semiconductor device according to claim 1, wherein the two layers of the upper clad material or the lower clad material are joined by pressure welding or brazing material. 4. The ceramic substrate, the metal circuit board, the semiconductor element, the upper clad material, and the lower clad material, any one or a plurality of or all of them are joined with a brazing material. The semiconductor device described. 7. The semiconductor device according to claim 5, wherein the brazing material is an Sn—Cu based brazing material. 8. The semiconductor device according to claim 7, wherein the Sn—Cu-based brazing material is 1 to 13 mass% Sn—Cu.