JP7337733B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP7337733B2 JP7337733B2 JP2020038055A JP2020038055A JP7337733B2 JP 7337733 B2 JP7337733 B2 JP 7337733B2 JP 2020038055 A JP2020038055 A JP 2020038055A JP 2020038055 A JP2020038055 A JP 2020038055A JP 7337733 B2 JP7337733 B2 JP 7337733B2
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- 239000004065 semiconductor Substances 0.000 title claims description 131
- 239000011347 resin Substances 0.000 claims description 108
- 229920005989 resin Polymers 0.000 claims description 108
- 238000007789 sealing Methods 0.000 claims description 99
- 238000012986 modification Methods 0.000 description 33
- 230000004048 modification Effects 0.000 description 33
- 229910000679 solder Inorganic materials 0.000 description 23
- 238000000034 method Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
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Description
し、前記溝は、前記第1の端部と接するように前記第1の端部に沿って延びる第1の溝を有し、前記第1の接続部は前記第1の溝の短手方向の一端部を含み、前記第2の接続部は前記第1の溝の延伸方向の一端部を含む。
以下、図面を参照して実施形態1について詳細に説明する。
図1は、実施形態1にかかる半導体パッケージ1の構成の一例を示す斜視図である。図1(a)は半導体パッケージ1の上面側を示しており、図1(b)は半導体パッケージ1の下面側を示している。
次に、図3を用いて、実施形態1の半導体パッケージ1の製造方法の例について説明する。図3は、実施形態1にかかる半導体パッケージ1の製造方法の手順の一例を示す断面図である。ここで、半導体チップ30は、通常の半導体製造技術によって製造され、ドレイン電極21、ソース電極22、ゲート電極23、及びシグナルソースピン24と接合される。封止樹脂部材10は、以下に示すように、例えば金型(上型Mt及び下型Mb)を用いたモールド技術によって成形される。
次に、図4を用いて、実施形態1の変形例1の半導体パッケージ1aについて説明する。図4は、実施形態1の変形例1にかかる半導体パッケージ1aの下面側を示す平面図である。変形例1の半導体パッケージ1aは、上述の実施形態1とは異なる構成の溝60を備える。
次に、図5を用いて、実施形態1の変形例2の半導体パッケージ1bについて説明する。図5は、実施形態1の変形例2にかかる半導体パッケージ1bの下面側を示す平面図である。変形例2の半導体パッケージ1bは、ドレイン電極21の実装面21mの端部21e,21wにも溝70e,70wを有する点が、上述の実施形態1とは異なる。
以下、図面を参照して実施形態2について詳細に説明する。実施形態2の半導体パッケージ2は、上述の実施形態1の半導体パッケージ1と仕様が異なる。
図6は、実施形態2にかかる半導体パッケージ2の構成の一例を示す斜視図である。図6(a)は半導体パッケージ2の上面側を示しており、図6(b)は半導体パッケージ2の下面側を示している。
次に、図8を用いて、実施形態2の変形例1の半導体パッケージ2aについて説明する。図8は、実施形態2の変形例1にかかる半導体パッケージ2aの下面側を示す平面図である。変形例1の半導体パッケージ2aは、上述の実施形態1の変形例1の半導体パッケージ1aが有する溝60と対応する溝160を備える。
次に、図9を用いて、実施形態2の変形例2の半導体パッケージ2bについて説明する。図9は、実施形態2の変形例2にかかる半導体パッケージ2bの下面側を示す平面図である。変形例2の半導体パッケージ2bは、上述の実施形態1の変形例2の半導体パッケージ1bが有する溝70e,70wと対応する溝170e,170wを備える。
Claims (17)
- 半導体チップと、
内部に前記半導体チップが封止される平板状の封止樹脂部材と、
前記封止樹脂部材の第1の主面に露出した第1の実装面を有する第1の電極と、
前記第1の主面に露出した第2の実装面を有する第2の電極と、
前記第1の主面に配置された溝と、を備え、
前記第1の実装面は、
前記第1の主面の内側領域に配置され、前記第2の電極と対向する第1の端部を有し、
前記溝は、
前記第1の端部に接続される第1の接続部と、
前記封止樹脂部材の側面に接続される第2の接続部と、を有し、
前記溝は、
前記第1の端部と接するように前記第1の端部に沿って延びる第1の溝を有し、
前記第1の接続部は前記第1の溝の短手方向の一端部を含み、
前記第2の接続部は前記第1の溝の延伸方向の一端部を含む、
半導体パッケージ。 - 前記第2の接続部は前記第1の溝の延伸方向の両端部を含む、
請求項1に記載の半導体パッケージ。 - 半導体チップと、
内部に前記半導体チップが封止される平板状の封止樹脂部材と、
前記封止樹脂部材の第1の主面に露出した第1の実装面を有する第1の電極と、
前記第1の主面に露出した第2の実装面を有する第2の電極と、
前記第1の主面に配置された溝と、を備え、
前記第1の実装面は、
前記第1の主面の内側領域に配置され、前記第2の電極と対向する第1の端部を有し、
前記溝は、
前記第1の端部に接続される第1の接続部と、
前記封止樹脂部材の側面に接続される第2の接続部と、を有し、
前記溝は、
前記第1の端部から離れた位置を前記第1の端部に沿って延びる主溝と、
前記主溝から前記第1の端部へと延びる副溝と、を含む第2の溝を有し、
前記第1の接続部は前記副溝の前記第1の端部へと延びた一端部を含み、
前記第2の接続部は前記主溝の延伸方向の一端部を含む、
半導体パッケージ。 - 前記第2の接続部は前記主溝の延伸方向の両端部を含む、
請求項3に記載の半導体パッケージ。 - 前記第1の実装面は前記第2の実装面よりも広い面積を有する、
請求項1乃至請求項4のいずれか1項に記載の半導体パッケージ。 - 前記第1の電極はドレイン電極であり、
前記第2の電極はソース電極である、
請求項1乃至請求項5のいずれか1項に記載の半導体パッケージ。 - 前記第1の実装面は、
前記内側領域に配置され、前記第1の主面の端部と対向する第2の端部を有し、
前記溝は、
前記第1の主面の端部から前記第2の端部へと延びる第3の溝を有し、
前記第1の接続部は前記第3の溝の前記第2の端部へと延びた一端部を含み、
前記第2の接続部は前記第3の溝の他端部を含む、
請求項1乃至請求項6のいずれか1項に記載の半導体パッケージ。 - 前記第1の端部は所定方向に延伸し、
前記第2の端部は、
前記第1の端部の延伸方向と交わる方向に延伸する、
請求項7に記載の半導体パッケージ。 - 前記第2の端部は、
前記第1の端部の延伸方向の両側に配置される、
請求項8に記載の半導体パッケージ。 - 前記第1の端部は所定方向に延伸し、
前記第2の端部は、
前記第1の端部の延伸方向に沿う方向に延伸する、
請求項7に記載の半導体パッケージ。 - 前記溝の深さは前記第2の電極の厚さ未満である、
請求項1乃至請求項10のいずれか1項に記載の半導体パッケージ。 - 前記溝は側面と底面とを有し、
前記側面と前記底面とは曲面で接続される、
請求項1乃至請求項11のいずれか1項に記載の半導体パッケージ。 - 前記第1の主面に露出した第3の実装面を有し、前記第2の電極側で前記第1の端部と対向する第3の電極を備える、
請求項1乃至請求項12のいずれか1項に記載の半導体パッケージ。 - 前記第1の実装面は前記第3の実装面よりも広い面積を有する、
請求項13に記載の半導体パッケージ。 - 前記第3の電極はゲート電極である、
請求項13または請求項14に記載の半導体パッケージ。 - 前記半導体チップは電力用半導体チップである、
請求項1乃至請求項15のいずれか1項に記載の半導体パッケージ。 - 表面実装型パッケージである、
請求項1乃至請求項16のいずれか1項に記載の半導体パッケージ。
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