JP7336767B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing a semiconductor light emitting device.

In recent years, crystal growth methods for nitride-based semiconductors have progressed rapidly, and blue and green light-emitting devices with high brightness using this material have been put to practical use. By combining conventional red light-emitting elements with these blue light-emitting elements and green light-emitting elements, all the three primary colors of light are obtained, and a full-color display device can be realized. That is, by mixing all the three primary colors of light, it becomes possible to obtain white light, which can be applied to illumination devices.

A semiconductor light-emitting device used as a light source for lighting is desirably capable of achieving high energy conversion efficiency and high light output in a high current density region, and is desirably stable in light distribution characteristics of emitted light. In order to solve these problems, Patent Document 1 proposes a semiconductor light-emitting device in which an n-type nanowire core, an intermediate active layer, and a p-type shell are grown on a semiconductor substrate, and a transparent conductive film such as ITO is formed on the shell. It is

Further, in Patent Document 2, in order to prevent light absorption in the transparent conductive film, a p-type semiconductor layer and a tunnel junction layer are formed on the outer periphery of the active layer, and the embedded semiconductor layer is used as a contact layer to flow current from the side surface of the nanowire core. is disclosed.

Further, Patent Document 3 discloses a technique of increasing the efficiency of a light-emitting element by providing a cover layer outside the active layer on the side surface of the nanowire.

Japanese Patent Publication No. 2016-518703 JP 2019-012744 A Japanese Patent Publication No. 2015-508941

The semiconductor light-emitting devices in which the active layer is formed on the periphery of the nanowire core disclosed in Patent Documents 1, 2, and 3 have fewer crystal defects and threading dislocations than those in which the active layer is formed on the entire surface of the sapphire substrate, and are of high quality. Therefore, it is possible to improve the external quantum efficiency at high current densities.

However, the crystal quality of the active layer deteriorates due to thermal degradation of the surface of the nanowires and the surface of the active layer caused by the selective growth of the nanowire core on the sapphire substrate and the subsequent fabrication of the active layer and p-type semiconductor layer. luminous efficiency may also decrease.

Therefore, the present invention has been devised in view of the above conventional problems, and is a semiconductor light emitting device capable of improving the external quantum efficiency by further improving the crystal quality of the active layer formed on the outer periphery of the nanowire. And it aims at providing the manufacturing method of a semiconductor light-emitting device.

In order to solve the above problems, the semiconductor light emitting device of the present invention includes a growth substrate and a columnar semiconductor layer formed on the growth substrate, wherein the columnar semiconductor layer has n a nanowire layer is formed, an active layer is formed around the n-type nanowire layer, a p-type semiconductor layer is formed around the active layer, and the inner surface is made of a nitride semiconductor material containing Al. A protective layer is provided on the bottom of the n-type nanowire layer , the inner surface protective layer contains at least Al, and the composition ratio of Al is 0.06 or less .

In such a semiconductor light emitting device of the present invention, the inner surface protective layer is provided in contact with the n-type nanowire layer, and the inner surface protective layer is made of a nitride semiconductor material containing Al. It is possible to suppress propagation of point defects generated inside to the active layer, thereby improving the crystal quality of the active layer and improving the external quantum efficiency.

In one aspect of the present invention, the film thickness of the inner surface protective layer is 1 nm or more and 100 nm or less.

In order to solve the above problems, a semiconductor light emitting device according to the present invention includes a growth substrate and a columnar semiconductor layer formed on the growth substrate, wherein the columnar semiconductor layer has a An n-type nanowire layer is formed, an active layer is formed around the n-type nanowire layer, a p-type semiconductor layer is formed around the active layer, and the outside is made of a nitride semiconductor material containing Al. A surface protective layer is provided to cover the outer periphery of the active layer, the outer surface protective layer contains at least Al, and the composition ratio of Al is 0.06 or less at maximum.

In one aspect of the present invention, a tunnel junction layer is formed outside the p-type semiconductor layer.

In order to solve the above problems, a semiconductor light emitting device according to the present invention includes a growth substrate and a columnar semiconductor layer formed on the growth substrate, wherein the columnar semiconductor layer has a An n-type nanowire layer is formed, an active layer is formed outside the n-type nanowire layer, a p-type semiconductor layer is formed around the active layer, and a tunnel junction layer is formed around the p-type semiconductor layer. is formed, an outer surface protective layer made of a nitride semiconductor material containing Al is provided to cover the outer periphery of the tunnel junction layer, the outer surface protective layer contains at least Al, and the composition of Al The ratio is characterized by a maximum of 0.06 or less.

In one aspect of the present invention, an embedded semiconductor layer that covers the columnar semiconductor layer is further provided.

In order to solve the above problems, the method for manufacturing a semiconductor light emitting device of the present invention includes a mask step of forming a mask layer having an opening on a growth substrate, and forming a columnar semiconductor layer in the opening using selective growth. the growth step includes forming an n-type nanowire layer; forming an active layer outside the n-type nanowire layer; and adding Al to the bottom of the n-type nanowire layer. and forming a p-type semiconductor layer outside the active layer , wherein the inner surface protective layer contains at least Al, The composition ratio of Al is characterized by a maximum of 0.06 or less .

The present invention can provide a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device capable of improving the external quantum efficiency by further improving the crystal quality of the active layer formed on the outer periphery of the nanowire.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram which shows the semiconductor light-emitting device 10 which concerns on 1st Embodiment, Fig.1 (a) shows the whole, and FIG.1(b) shows the structure of a columnar semiconductor layer part expanded. 2A is a mask forming process, FIG. 2B is a nanowire growing process, FIG. 2C is a columnar semiconductor layer growing process, and FIG. ) indicates the removing step, and FIG. 2(e) indicates the electrode forming step. 3A is a graph showing the emission intensity of the semiconductor light emitting device 10, FIG. 3A shows the relationship between the thickness of the inner surface protective layer 15 and the emission intensity, and FIG. It shows the relationship between the composition ratio and the emission intensity. FIG. 5 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 30 according to a second embodiment; FIG. 11 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 40 according to a third embodiment; FIG. 11 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 50 according to a fourth embodiment; FIG. 11 is a schematic diagram showing an enlarged structure of a columnar semiconductor layer portion of a semiconductor light emitting device 60 according to a fifth embodiment;

(First embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. 1A and 1B are schematic diagrams showing a semiconductor light emitting device 10 according to the first embodiment, FIG. 1A showing the whole, and FIG. 1B showing an enlarged structure of a columnar semiconductor layer portion. .

As shown in FIGS. 1A and 1B, a semiconductor light emitting device 10 includes a growth substrate 11, an underlying layer 12, a mask 13, an n-type nanowire layer 14, an inner surface protection layer 15, and an active layer 16. , a p-type semiconductor layer 17 , a tunnel junction layer 18 and a buried semiconductor layer 19 . Here, the n-type nanowire layer 14, the inner surface protection layer 15, the active layer 16, the p-type semiconductor layer 17 and the tunnel junction layer 18 are selectively grown in the direction perpendicular to the growth substrate 11 to form a pillar shape. , constitute the columnar semiconductor layer in the present invention.

As shown in FIG. 1A, a portion of the semiconductor light-emitting device 10 has an underlying layer 12 exposed, and cathode electrodes 20 and 21 are formed on the underlying layer 12 . Moreover, the embedded semiconductor layer 19 is left in a partial region above the columnar semiconductor layer, and the anode electrodes 22 and 23 are formed on the embedded semiconductor layer 19 in this region. In regions where anode electrodes 22 and 23 are not formed, embedded semiconductor layer 19 and tunnel junction layer 18 are removed until p-type semiconductor layer 17 is partially exposed.

The growth substrate 11 is a substantially flat member made of a material capable of crystal growth of a semiconductor material, and has a mask 13 formed on its main surface. The growth substrate 11 may be composed of a single material, or may be a single crystal substrate on which a plurality of semiconductor layers such as a buffer layer are grown. The growth substrate 11 may be a single-crystal substrate made of a material for growing a semiconductor single-crystal layer through a buffer layer. A sapphire substrate is preferred, but other heterogeneous substrates such as Si may be used. Also, for laser oscillation, a c-plane GaN substrate, on which cavity planes are easily formed by cleavage, may be used. The buffer layer is a layer formed between the single crystal substrate and the underlying layer 12 to alleviate the lattice mismatch between the two. When a c-plane sapphire substrate is used as the single crystal substrate, AlN is preferably used as the material, but GaN, AlGaN, or the like may also be used.

The underlying layer 12 is a single-crystal semiconductor layer formed on the growth substrate 11 and the buffer layer, and is preferably formed of non-doped GaN with a thickness of several μm. The underlying layer 12 may be composed of a single layer, or may be composed of multiple layers including an n-type semiconductor layer such as an n-type contact layer. The n-type contact layer is a semiconductor layer doped with an n-type impurity, such as Si-doped n-type Al _0.05 Ga _0.95 N. As shown in FIG. 1A, a portion of the underlayer 12 is exposed to form cathode electrodes 20 and 21 .

Mask 13 is a layer made of a dielectric material formed on the surface of underlying layer 12 . As a material for forming the mask 13, a material that makes crystal growth of a semiconductor difficult is selected from the mask 13. For example, SiO ₂ and SiN _x are suitable. A plurality of openings, which will be described later, are formed in the mask 13, and a semiconductor layer can be grown from the underlying layer 12 partially exposed through the openings.

The columnar semiconductor layer is a semiconductor layer crystal-grown in the opening provided in the mask 13 , and the substantially columnar semiconductor layer is formed vertically with respect to the main surface of the growth substrate 11 . Such a columnar semiconductor layer can be obtained by setting appropriate growth conditions according to the semiconductor material to be formed, and performing selective growth in which a specific crystal plane orientation is grown. In the example shown in FIG. 1, since a plurality of openings are formed in the mask 13 two-dimensionally and periodically, the columnar semiconductor layers are also formed two-dimensionally and periodically on the growth substrate 11 . Although an example in which the columnar semiconductor layers are arranged two-dimensionally and periodically is shown here, the number of columnar semiconductor layers may be one, and a plurality of columnar semiconductor layers may be formed aperiodically.

The n-type nanowire layer 14 is a columnar semiconductor layer selectively grown on the underlying layer 12 exposed through the opening of the mask 13, and is made of GaN doped with n-type impurities, for example. When GaN is used as the n-type nanowire layer 14, the n-type nanowire layer 14 selectively grown on the c-plane of the underlayer 12 has a substantially hexagonal prism shape with six m-planes formed as facets. 1(a) and 1(b), it seems that the n-type nanowire layer 14 is grown only in the region where the opening is formed. , forming an enlarged hexagonal prism around the opening. For example, when the opening is formed as a circle with a diameter of about 150 nm, the n-type nanowire layer 14 having a hexagonal prism shape with a height of about 1 to 2 mm and a hexagonal bottom surface inscribed in a circle with a diameter of about 240 nm is formed. can be done.

The inner surface protective layer 15 is a semiconductor layer made of a nitride semiconductor material containing Al, and is provided in contact with the n-type nanowire layer 14 to cover the outer periphery. It is known that when a nitride semiconductor layer contains a small amount of Al, point defects generated during crystal growth are less likely to propagate than in a GaN layer. Therefore, the inner surface protective layer 15 is a layer for suppressing the propagation of point defects that occur when the semiconductor layer is selectively grown on the underlying layer 12 from the opening of the mask 13 to the active layer 16. _AlyGazN (y+z=1) _. The inner surface protective layer 15 may be formed by non-doping, or may be formed by doping an n-type impurity such as Si.

As for the composition ratio of the inner surface protective layer 15, it is preferable that the value of y in the general formula is more than 0 and 0.06 or less, as will be described later. In addition, the film thickness of the inner surface protective layer 15 is preferably in the range of 1 nm to 30 nm, more preferably in the range of 1 nm to 5 nm, as will be described later. Al contained in the inner surface protective layer 15 is preferable from the viewpoint of suppressing propagation of defects and preventing mass transport at high temperatures. As shown in FIG. 1(b), an inner surface protective layer 15 is formed between the n-type nanowire layer 14 and the active layer 16 in this embodiment.

The active layer 16 is a semiconductor layer grown on the outer periphery _of the n-type nanowire layer 14. For example, a _{Ga0.85In0.15N} quantum well layer with a thickness of 5 nm and a GaN barrier layer with a thickness of 10 nm are arranged in five cycles. Stacked multiple quantum well active layers are included. Although a multiple quantum well active layer is mentioned here, a single quantum well structure or a bulk active layer may be used. Since the active layer 16 is formed on the side and top surfaces of the n-type nanowire layer 14, the area of the active layer 16 can be secured.

The p-type semiconductor layer 17 is a semiconductor layer grown outside the active layer 16, and is made of GaN doped with p-type impurities, for example. Since the p-type semiconductor layer 17 is formed on the side surface and the upper surface of the active layer 16, the n-type nanowire layer 14, the active layer 16 and the p-type semiconductor layer 17 constitute a double hetero structure, and the carriers are well transferred to the active layer 16. can be confined to improve the probability of radiative recombination.

The tunnel junction layer 18 is a semiconductor layer grown outside the p-type semiconductor layer 17. For example, the tunnel junction layer 18 includes a p+ layer heavily doped with p-type impurities on the inside and a heavily n-type impurity on the outside. It has a two-layer structure in which the n+ layer and the n+ layer are grown in order. The p+ layer is a semiconductor layer heavily doped with p-type impurities, and can be made of GaN with a thickness of 5 nm and an Mg concentration of 2×10 ²⁰ cm ⁻³ , for example. For the n+ layer, for example, GaN with a thickness of 10 nm and a Si concentration of 2×10 ²⁰ cm ⁻³ can be used. Since a tunnel junction is formed by the p+ layer and the n+ layer, the two layers of the p+ layer and the n+ layer constitute the tunnel junction layer 18 in the present invention.

The embedded semiconductor layer 19 is a semiconductor layer formed so as to cover the top surface and side surfaces of the columnar semiconductor layer and the mask 13 . As shown in FIG. 1A, the buried semiconductor layer 19 also covers the tunnel junction layer 18 above the columnar semiconductor layers in the regions where the anode electrodes 22 and 23 are formed. Above the columnar semiconductor layer in the regions where the anode electrodes 22 and 23 are not formed, the embedded semiconductor layer 19 and the tunnel junction layer 18 are removed to expose the upper portion of the p-type semiconductor layer 17 and the side surface of the tunnel junction layer 18. is in contact with the buried semiconductor layer 19 as shown in FIG.

The cathode electrodes 20 and 21 are electrodes formed in the regions where the base layer 12 is exposed, and are composed of a layered structure of a metal material and a pad electrode that are in ohmic contact with the outermost surface of the base layer 12 . The anode electrodes 22 and 23 are electrodes formed on a part of the embedded semiconductor layer 19, and are composed of a laminated structure of a metal material that makes ohmic contact with the outermost surface of the embedded semiconductor layer 19 and a pad electrode. Also, although not shown in FIG. 1, a known structure such as covering the surface of the semiconductor light emitting device 10 with a passivation film may be applied as necessary.

In order to lengthen the emission wavelength of the semiconductor light emitting device 10, the InN mole fraction of the active layer 16 must be increased. For example, when the diameter of the circumscribed circle of the n-type nanowire layer 14 is 300 nm, it is necessary to use a red active layer composition of Ga _0.6 In _0.4 N. may occur. In order to avoid this, it is possible to reduce the film thickness of the Ga _0.6 In _0.4 N well layer or to use GaInN as the material forming the n-type nanowire layer 14 . Similarly, when the wavelength of the semiconductor light emitting device 10 is shortened, AlGaN may be used as the n-type nanowire layer 14, or the well layer and barrier layer of the active layer 16 may be changed to AlGaN having different compositions. It is possible.

2A and 2B are schematic diagrams showing a method for manufacturing the semiconductor light emitting device 10. FIG. 2A is a mask forming step, FIG. 2B is a nanowire growing step, FIG. 2C is a columnar semiconductor layer growing step, FIG. 2(d) shows the removing process, and FIG. 2(e) shows the electrode forming process.

First, in the mask step shown in FIG. 2A, a buffer layer made of AlN, GaN and An underlayer 12 of Al0.05Ga0.95N is grown. Next, a mask 13 made of SiO ₂ is deposited on the underlying layer 12 by a sputtering method to a thickness of about 30 nm, and an opening having a diameter of about 150 nm is formed using a fine pattern forming method such as nanoimprinting lithography. The growth conditions for the buffer layer are, for example, TMA ( TriMethylAluminium ) and ammonia are used as material gases, the growth temperature is 1100° C., the V/III ratio is 100, hydrogen is used as carrier gas, and the pressure is 10 hPa. The growth conditions for the underlying layer 12 and the n-type semiconductor layer are as follows: TMG (TriMethylGallium), TMA, and ammonia are used as material gases, the growth temperature is 1050° C., the V/III ratio is 1000, hydrogen is used as the carrier gas, and the pressure is 500 hPa. be.

Next, in the nanowire growth step shown in FIG. 2B, an n-type nanowire layer 14 made of GaN is grown on the underlying layer 12 exposed from the opening by selective growth by MOCVD. The growth conditions for the n-type nanowire layer 14 are, for example, TMG, monosilane and ammonia as material gases, a growth temperature of 1050° C., a V/III ratio of 20, and a pressure of 100 hPa with hydrogen as a carrier gas.

Next, in the columnar semiconductor layer growth step shown in FIG. 2(c), an inner surface protective layer 15 containing Al with a thickness of 1 to 100 nm and a thickness of 5 nm are formed on the side and top surfaces of the n-type nanowire layer 14 using the MOCVD method. of Ga _0.85 In _0.15 N quantum well layers and 10 nm-thick GaN barrier layers stacked five times, a p-type semiconductor layer 17 made of GaN doped with p-type impurities, and a Mg layer 17 having a thickness of 5 nm. A tunnel junction layer 18 including a p+ layer made of GaN with a concentration of 2×10 ²⁰ cm ⁻³ and an n+ layer with a thickness of 10 nm and a Si concentration of 2× ^{10 20} cm ⁻³ is sequentially grown. Next, a buried semiconductor layer 19 made of n-type GaN is grown to fill the outer periphery and upper surface of the tunnel junction layer 18 with the buried semiconductor layer 19 .

The growth conditions for the inner surface protective layer 15 are, for example, a growth temperature of 800° C., a V/III ratio of 3000, a pressure of 1000 hPa using nitrogen as a carrier gas, and TMG, TMA and ammonia as source gases. The growth conditions for the active layer 16 are, for example, a growth temperature of 800° C., a V/III ratio of 3000, a pressure of 1000 hPa using nitrogen as a carrier gas, and TMG, TMI (Trimethylindium) and ammonia as source gases. The growth conditions for the p-type semiconductor layer 17 are, for example, a growth temperature of 950.degree. The growth conditions for the tunnel junction layer 18 are, for example, a growth temperature of 800° C., a V/III ratio of 3000, a pressure of 500 hPa using nitrogen as a carrier gas, and TMG, Cp2Mg, monosilane and ammonia as source gases. The embedded semiconductor layer 19 is grown under conditions such as a growth temperature of 900° C., a V/III ratio of 20, hydrogen as a carrier gas at a pressure of 200 hPa, and TMG, monosilane, and ammonia as source gases.

Next, in the removal step shown in FIG. 2D, the upper surfaces of the embedded semiconductor layer 19 and the tunnel junction layer 18 are selectively removed by dry etching to expose the upper surface of the p-type semiconductor layer 17. Next, as shown in FIG. In the regions where the cathode electrodes 20 and 21 are to be formed, the mask 13 is also removed to expose the upper surface of the underlying layer 12 .

Further, the p-type semiconductor layer 17 is exposed and then annealed at 600° C. in the air atmosphere to remove hydrogen from the p-type semiconductor layer 17 and the tunnel junction layer 18, thereby separating the p-type semiconductor layer 17 and the tunnel junction layer. An activation step of activating is performed. Annealing in an air atmosphere is shown here, but an atmosphere in which atomic hydrogen that can activate the p-type semiconductor layer 17 and the tunnel junction layer 18 does not exist may be used.

Finally, in the electrode forming step shown in FIG. Further, if necessary, annealing after electrode formation, formation of a passivation film, and element division are performed to obtain the semiconductor light emitting element 10 .

In the semiconductor light emitting device 10 of this embodiment, when a voltage is applied between the cathode electrodes 20 and 21 and the anode electrodes 22 and 23, the embedded semiconductor layer 19, the tunnel junction layer 18, the p-type semiconductor layer 17, the active layer 16, A current flows through the inner surface protective layer 15, the n-type nanowire layer 14, and the n-type semiconductor layer in that order, and light is generated in the active layer 16 by radiative recombination. Light emitted from the active layer 16 is extracted to the outside of the semiconductor light emitting device 10 .

FIG. 3(a) shows the relationship between the thickness of the inner surface protective layer 15 and the emission intensity, and FIG. 3(b) shows the relationship between the Al composition ratio of the inner surface protective layer 15 and the emission intensity. In the graph shown in FIG. 3A, AlGaN having an Al composition ratio of 0.06 is used as the inner surface protective layer 15, and in the graph shown in FIG. 3B, AlGaN is used as the inner surface protective layer 15. The film thickness is 30 nm. Therefore, the film thickness of 0 nm in FIG. 3A and the Al composition ratio of 0% in FIG.

As shown in FIG. 3(a), even when the thickness of the inner surface protective layer 15 is 60 nm or more, the emission intensity is higher than the case without the inner surface protective layer 15, and the external quantum efficiency is higher. It is considered that this is because point defects generated in the n-type nanowire layer 14 are reduced by the inner surface protective layer 15 and the crystal quality of the active layer 16 is improved. The emission intensity is maximum when the thickness of the inner surface protective layer 15 is 1 nm, and the emission intensity decreases as the thickness increases. If the film thickness of the inner surface protective layer 15 is less than 1 nm, it is difficult to form the inner surface protective layer 15 on the entire side surface of the n-type nanowire layer 14, which is not preferable. In addition, since the emission intensity decreases as the film thickness increases, the film thickness is preferably 30 nm or less, more preferably 5 nm or less.

As shown in FIG. 3B, when AlGaN is used as the inner surface protective layer 15, the emission intensity is higher and the external quantum efficiency is higher than when the Al composition ratio is 0 and the inner surface protective layer 15 is not provided. The emission intensity reaches a maximum when the Al composition ratio is about 4%, and the emission intensity decreases when the composition ratio exceeds that. If the Al composition ratio of the inner surface protective layer 15 is greater than 0, the light emission intensity is improved.

As shown in FIGS. 3A and 3B, in the semiconductor light emitting device 10 of this embodiment, the inner surface protective layer 15 is formed between the n-type nanowire layer 14 and the active layer 16, so that the n-type nanowire Point defects generated in the layer 14 are prevented from continuing to the active layer 16, and the crystal quality of the active layer 16 is improved, thereby improving the external quantum efficiency.

In addition, in the semiconductor light emitting device 10 of the present embodiment, the active layer 16 is formed outside the n-type nanowire layer 14 , and the tunnel junction layer 18 is formed around the active layer 16 and embedded with the embedded semiconductor layer 19 . . Therefore, the current injected from the anode electrodes 22 and 23 is injected from the sidewall of the p-type semiconductor layer 17 into the active layer 16 as a tunnel current from the buried semiconductor layer 19 via the tunnel junction layer 18 . Further, in the upper portion of the columnar semiconductor layer, the upper surface of the p-type semiconductor layer 17 in contact with the n-type buried semiconductor layer 19 is reverse biased, and current injection does not occur. The current injection by the tunnel current through the tunnel junction layer 18 has a small resistance and can be carried out satisfactorily. In addition, since the buried semiconductor layer 19, which is an n-type semiconductor layer, diffuses current more easily than a p-type semiconductor layer, the current is favorably diffused from the side surface of the columnar semiconductor layer to the vicinity of the bottom surface, and the tunnel junction layer 18 is formed. Current injection can be done from the whole.

As a result, the current injected from the anode electrodes 22 and 23 is well injected into the p-type semiconductor layer 17 not from the upper surface of the columnar semiconductor layer but from the entire side surface of the columnar semiconductor layer. It is possible to realize current density and improve external quantum efficiency.

In addition, since the side surfaces of the n-type nanowire layer 14 are m-planes formed by selective growth, the active layer 16 and the p-type semiconductor layer 17 formed on the outer periphery are also in contact with each other on the m-planes. Since the m-plane is a nonpolar plane and does not cause polarization, the luminous efficiency in the active layer 16 is high, and since all the side surfaces of the hexagonal prism are m-planes, the luminous efficiency of the semiconductor light-emitting device 10 can be improved. Furthermore, when the height of the columnar semiconductor layer is increased to 500 nm or more, the volume of the active layer 16 can be increased to about 3 to 10 times that of the conventional semiconductor light emitting device, and the density of injected carriers is reduced, resulting in efficient droop. can be greatly reduced.

Furthermore, since the embedded semiconductor layer 19 is made of a material having a bandgap larger than that of the active layer 16, the embedded semiconductor layer 19 is less likely to inject current into the columnar semiconductor layer using ITO or the like. can significantly reduce the light absorption of As a result, the absorption of light generated in the active layer 16 inside the semiconductor light emitting device 10 can be suppressed, and the external quantum efficiency for extracting light to the outside of the semiconductor light emitting device 10 can be improved.

As described above, in the semiconductor light emitting device 10 and the method for manufacturing the same of the present embodiment, the inner surface protective layer 15 is provided in contact with the n-type nanowire layer 14, and the inner surface protective layer 15 is a nitriding layer containing Al. Since the n-type nanowire layer 14 is composed of a solid semiconductor material, it is possible to suppress the propagation of point defects generated in the n-type nanowire layer 14 to the active layer 16, thereby improving the crystal quality of the active layer 16 and improving the external quantum efficiency. .

(Second embodiment)
Next, a second embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 4 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 30 according to the second embodiment. This embodiment differs from the first embodiment in that the inner surface protection layer 35 is formed in a nanowire shape instead of forming the n-type nanowire layer 14 from GaN.

As shown in FIG. 4, the semiconductor light emitting device 30 of this embodiment includes a growth substrate 11, an underlying layer 12, a mask 13, an inner surface protection layer 35, an active layer 16, a p-type semiconductor layer 17, It comprises a tunnel junction layer 18 and a buried semiconductor layer 19 . In this embodiment, the active layer 16 is formed on the outer periphery of the inner surface protective layer 35, the p-type semiconductor layer 17 is formed on the outer periphery of the active layer 16, and the tunnel junction layer is formed on the outer periphery of the p-type semiconductor layer 17. 18 is formed to have a columnar shape and constitute a columnar semiconductor layer.

The inner surface protective layer 35 is a columnar semiconductor layer selectively grown on the underlying layer 12 exposed from the opening of the mask 13, and is made of a nitride semiconductor material containing Al doped with an n-type impurity. . The inner surface protective layer 35 contains at least Al, and the composition ratio of Al is preferably in the range of 0.06 mol % or less at maximum.

In forming the inner surface protective layer 35 , AlGaN is selectively grown on the underlayer 12 exposed from the openings of the mask 13 instead of the nanowire growth step shown in FIG. 2B of the first embodiment. The growth conditions for the inner surface protective layer 35 are, for example, TMG, TMA and ammonia as material gases, a growth temperature of 1050° C., a V/III ratio of 20, and a pressure of 100 hPa with hydrogen as a carrier gas.

In the semiconductor light emitting device 30 of this embodiment, the inner surface protective layer 35 is made of a nitride semiconductor material containing Al instead of the n-type nanowire layer 14 . However, the nanowire-shaped inner surface protective layer 35 suppresses propagation of point defects that occur when the semiconductor layer is selectively grown on the underlying layer 12 from the opening of the mask 13 to the active layer 16 . It is possible to improve the quality of the light and improve the external quantum efficiency.

(Third Embodiment)
Next, a third embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 5 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 40 according to the third embodiment. This embodiment differs from the first embodiment in that an inner surface protective layer 45 is provided on the bottom of the n-type nanowire layer 14 .

As shown in FIG. 5, the semiconductor light emitting device 40 of this embodiment includes a growth substrate 11, an underlying layer 12, a mask 13, an inner surface protection layer 45, an n-type nanowire layer 14, an active layer 16, It comprises a p-type semiconductor layer 17 , a tunnel junction layer 18 and a buried semiconductor layer 19 . In the present embodiment, the inner surface protective layer 45 is formed on the bottom of the n-type nanowire layer 14 and is in contact with the n-type nanowire layer 14, and the active layer 16 is formed outside the n-type nanowire layer 14 to provide an active layer. A p-type semiconductor layer 17 is formed outside the layer 16, and a tunnel junction layer 18 is formed around the p-type semiconductor layer 17 to form a columnar shape, forming a columnar semiconductor layer.

The inner surface protective layer 45 is a semiconductor layer selectively grown on the underlying layer 12 exposed through the opening of the mask 13, and is made of a nitride semiconductor material containing Al doped with n-type impurities. The composition ratio of Al contained in the inner surface protective layer 35 is preferably in the range of more than 0 and 0.06 or less. The film thickness of the inner surface protective layer 45 is preferably in the range of 1 nm to 100 nm, more preferably in the range of 1 nm to 5 nm.

In forming the inner surface protective layer 45, AlGaN is selectively grown on the underlying layer 12 exposed from the openings of the mask 13 in the initial stage of the nanowire growth process shown in FIG. 2(b) of the first embodiment. The growth conditions for the inner surface protective layer 45 are, for example, TMG, TMA and ammonia as material gases, a growth temperature of 1050° C., a V/III ratio of 20, and a pressure of 100 hPa with hydrogen as a carrier gas.

After the inner surface protective layer 45 is formed, the supply of TMA, which is a raw material gas, is stopped, and the supply of TMG and ammonia is continued. The nanowire layer 14 can be formed into pillars.

In the semiconductor light emitting device 40 of this embodiment, the inner surface protective layer 45 is in contact with the n-type nanowire layer 14 and is provided between the underlying layer 12 and the n-type nanowire layer 14 . Therefore, since the inner surface protective layer 45 on the underlying layer 12 is composed of a nitride semiconductor material containing Al, point defects generated during selective growth are suppressed and propagate to the n-type nanowire layer 14 and the active layer 16. It is possible to reduce defects, improve the crystal quality of the active layer 16, and improve the external quantum efficiency.

(Fourth embodiment)
Next, a fourth embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 6 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 50 according to the fourth embodiment. This embodiment differs from the first embodiment in that an outer surface protection layer 55 is formed around the outer periphery of the active layer 16 in addition to providing the inner surface protection layer 15 inside the active layer 16 .

As shown in FIG. 6, the semiconductor light emitting device 50 of this embodiment includes a growth substrate 11, an underlying layer 12, a mask 13, an n-type nanowire layer 14, an inner surface protection layer 15, an active layer 16, It comprises an outer surface protection layer 55 , a p-type semiconductor layer 17 , a tunnel junction layer 18 and a buried semiconductor layer 19 . In this embodiment, the inner surface protective layer 15 is formed around the n-type nanowire layer 14, the active layer 16 is formed around the inner surface protective layer 15, and the outer surface protective layer 55 is formed around the active layer 16. is formed, the p-type semiconductor layer 17 is formed around the outer surface protection layer 55, and the tunnel junction layer 18 is formed around the p-type semiconductor layer 17 to form a columnar shape, forming a columnar semiconductor layer. are doing.

The outer surface protective layer 55 is a semiconductor layer formed in contact with the side surface and the upper surface of the active layer 16 to cover the outer periphery thereof, and is made of a nitride semiconductor material containing Al. If the outer surface protective layer 55 contains a small amount of Al, the thermal stability is higher than that of GaN containing no Al. As a result, when the p-type semiconductor layer 17 is crystal-grown at a relatively high temperature in a post-process, the active layer 16 crystal-grown at a relatively low temperature inside the outer surface protection layer 55 is protected and deformed by mass transport. and the diffusion of In contained in the well layer can be suppressed.

The composition ratio of Al contained in the outer surface protective layer 55 is preferably in the range of more than 0 and 0.06 or less. The film thickness of the outer surface protective layer 55 is preferably in the range of 1 nm to 30 nm, more preferably in the range of 1 nm to 5 nm. The outer surface protective layer 55 may be formed by non-doping, or may be formed by doping with a p-type impurity such as Mg. As shown in FIG. 6, in this embodiment, the inner surface protective layer 15 and the outer surface protective layer 55 are provided inside and outside the active layer 16, so that the active layer 16 is not asymmetrically strained. It is preferable that the inner surface protective layer 15 and the outer surface protective layer 55 have approximately the same composition ratio and film thickness.

In the semiconductor light emitting device 50 of this embodiment as well, the outer surface protective layer 15 is provided in contact with the n-type nanowire layer 14, and the outer surface protective layer 15 is made of a nitride semiconductor material containing Al. Propagation of point defects generated in the nanowire layer 14 to the active layer 16 can be suppressed, and the crystal quality and the external quantum efficiency of the active layer 16 can be improved.

(Fifth embodiment)
Next, a fifth embodiment of the invention will be described with reference to FIG. The description of the content that overlaps with the first embodiment is omitted. FIG. 7 is an enlarged schematic diagram showing the structure of the columnar semiconductor layer portion of the semiconductor light emitting device 60 according to the fifth embodiment. This embodiment differs from the first embodiment in that an outer surface protective layer 65 is formed around the outer periphery of the tunnel junction layer 18 in addition to providing the inner surface protective layer 15 inside the active layer 16. .

As shown in FIG. 7, a semiconductor light emitting device 60 of this embodiment includes a growth substrate 11, an underlying layer 12, a mask 13, an n-type nanowire layer 14, an inner surface protective layer 15, an active layer 16, It comprises a p-type semiconductor layer 17 , a tunnel junction layer 18 , an outer surface protective layer 65 and a buried semiconductor layer 19 . In this embodiment, the inner surface protective layer 15 is formed outside the n-type nanowire layer 14, the active layer 16 is formed around the inner surface protective layer 15, and the p-type semiconductor layer 17 is formed around the active layer 16. is formed, a tunnel junction layer 18 is formed outside the p-type semiconductor layer 17, and an outer surface protective layer 65 is formed around the tunnel junction layer 18 to form a columnar shape, forming a columnar semiconductor layer. are doing.

The outer surface protective layer 65 is a semiconductor layer formed in contact with the side surface and the upper surface of the tunnel junction layer 18 to cover the outer periphery thereof, and is made of a nitride semiconductor material containing Al. If the outer surface protective layer 65 contains a small amount of Al, the thermal stability is higher than that of GaN containing no Al. This protects the active layer 16, the p-type semiconductor layer 17, and the tunnel junction layer 18 crystal-grown inside the outer surface protection layer 65 when the embedded semiconductor layer 19 is crystal-grown at a relatively high temperature in a later process. In addition, diffusion of the p-type impurity such as Mg doped into the p-type semiconductor layer 17 into the buried semiconductor layer 19 can be suppressed.

The composition ratio of Al contained in the outer surface protective layer 65 is preferably in the range of 0.06 or less including Al. The film thickness of the outer surface protective layer 65 is preferably in the range of 1 nm or more and 30 nm or less, more preferably in the range of 1 nm or more and 5 nm or less. The outer surface protective layer 65 may be formed by non-doping, or may be formed by doping an n-type impurity such as Si.

In the semiconductor light emitting device 60 of the present embodiment as well, the inner surface protective layer 15 is provided in contact with the n-type nanowire layer 14, and the inner surface protective layer 15 is made of a nitride semiconductor material containing Al. Propagation of point defects generated in the nanowire layer 14 to the active layer 16 can be suppressed, and the crystal quality and the external quantum efficiency of the active layer 16 can be improved.

The present invention is not limited to the above-described embodiments, but can be modified in various ways within the scope of the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. is also included in the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 10, 30, 40, 50, 60... Semiconductor light-emitting element 11... Growth substrate 12... Base layer 13... Mask 14... N-type nanowire layer 15, 35, 45... Inner surface protective layer 16... Active layer 17... P-type semiconductor layer DESCRIPTION OF SYMBOLS 18... Tunnel junction layer 19... Embedded semiconductor layer 20, 21... Cathode electrode 22, 23... Anode electrode 55, 65... Outer surface protection

Claims (7)

A semiconductor light emitting device comprising a growth substrate and a columnar semiconductor layer formed on the growth substrate,
The columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed outside the n-type nanowire layer, and a p-type semiconductor layer formed outside the active layer,
an inner surface protective layer made of a nitride semiconductor material containing Al is provided on the bottom of the n-type nanowire layer ;
A semiconductor light-emitting device , wherein the inner surface protective layer contains at least Al, and the composition ratio of Al is 0.06 or less at maximum . The semiconductor light emitting device according to claim 1 ,
A semiconductor light-emitting device, wherein the film thickness of the inner surface protective layer is 1 nm or more and 100 nm or less. A semiconductor light emitting device comprising a growth substrate and a columnar semiconductor layer formed on the growth substrate,
The columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed outside the n-type nanowire layer, and a p-type semiconductor layer formed outside the active layer,
an outer surface protective layer made of a nitride semiconductor material containing Al is provided to cover the outer periphery of the active layer ;
A semiconductor light-emitting device , wherein the outer surface protective layer contains at least Al, and the composition ratio of Al is 0.06 or less at maximum . The semiconductor light emitting device according to any one of claims 1 to 3 ,
A semiconductor light-emitting device, wherein a tunnel junction layer is formed outside the p-type semiconductor layer. A semiconductor light emitting device comprising a growth substrate and a columnar semiconductor layer formed on the growth substrate,
The columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed around the n-type nanowire layer, a p-type semiconductor layer formed around the active layer , and the p-type semiconductor layer. A tunnel junction layer is formed on the outer periphery of the layer ,
an outer surface protective layer made of a nitride semiconductor material containing Al is provided to cover the outer periphery of the tunnel junction layer ;
A semiconductor light-emitting device , wherein the outer surface protective layer contains at least Al, and the composition ratio of Al is 0.06 or less at maximum . The semiconductor light emitting device according to any one of claims 1 to 5 ,
A semiconductor light emitting device, further comprising a buried semiconductor layer covering the columnar semiconductor layer. a masking step of forming a mask layer having an opening on a growth substrate; and a growing step of forming a columnar semiconductor layer in the opening using selective growth,
The growth step includes
forming an n-type nanowire layer; forming an active layer outside the n-type nanowire layer;
forming an inner surface protective layer made of a nitride semiconductor material containing Al on the bottom of the n-type nanowire layer ;
Forming a p-type semiconductor layer outside the active layer ,
A method for growing a semiconductor light emitting device , wherein the inner surface protective layer contains at least Al, and the composition ratio of Al is 0.06 or less at maximum .