JP7298667B2 - Capacitor-embedded component, mounting board provided with capacitor-embedded component, and method for manufacturing capacitor-embedded component - Google Patents

Description

An embodiment of the present disclosure relates to a capacitor-embedded component including a capacitor. The present disclosure also relates to a mounting board including a component with a built-in capacitor and a method of manufacturing the component with a built-in capacitor.

2. Description of the Related Art In recent years, as integrated circuits represented by semiconductor memories have become highly integrated, passive components used in the periphery of integrated circuits have also been required to be miniaturized. For example, Patent Document 1 proposes a thin film capacitor comprising a first conductive layer, a high dielectric thin film provided on the first conductive layer, and a second conductive layer provided on the high dielectric thin film. there is In thin film capacitors, by using a high dielectric constant thin film having a high dielectric constant as a dielectric, a small capacitor with a large capacity can be realized.

JP-A-6-89831

For miniaturization, it is preferable that the capacitor is configured integrally with other elements.

An embodiment of the present disclosure is a capacitor-embedded component, comprising: a substrate including a first surface and a second surface located opposite to the first surface; and a first surface located on the first surface of the substrate. a surface first conductive layer, a first surface first inorganic layer positioned on the first surface first conductive layer, and an upper conductive layer positioned on a portion of the first surface first inorganic layer; The upper conductive layer, and the first surface first conductive layer and the first surface first inorganic layer overlapping the upper conductive layer in plan view constitute a capacitor, and the capacitor-embedded component is the The capacitor-embedded component includes a first surface first organic layer located on the first surface first inorganic layer located on the first surface first conductive layer that does not overlap the upper conductive layer.

In the capacitor-embedded component according to one embodiment of the present disclosure, the first surface first organic layer may contain polyimide.

In the capacitor-embedded component according to one embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor when the evaluation length is 150 μm is 0.1 μm or more and 0.4 μm or less. may be

In the capacitor-embedded component according to one embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor is 0.2.2 μm or less when the evaluation length is 2.5 μm. There may be.

In the capacitor-embedded component according to one embodiment of the present disclosure, the side surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm. and the first surface first inorganic layer may at least partially cover the side surface of the first surface first conductive layer.

In the capacitor-embedded component according to one embodiment of the present disclosure, the substrate may contain glass.

In the capacitor-embedded component according to one embodiment of the present disclosure, the substrate is provided with a through hole, the capacitor-embedded component further includes an inductor electrically connected to the capacitor, the inductor being the first a first surface first conductive layer; a through electrode electrically connected to the first surface first conductive layer and positioned on the wall surface of the through hole; and a substrate electrically connected to the through electrode and and a second surface first conductive layer positioned on the second surface of.

A capacitor-embedded component according to one embodiment of the present disclosure comprises: a first-surface second conductive layer located on the first-surface first inorganic layer; the first surface first organic layer located on the layer and having an opening overlapping the first surface second conductive layer; and the first surface first organic layer on the first surface second conductive layer. a first surface third conductive layer at least partially located in said opening in a layer, said upper conductive layer of said capacitor being constituted by said first surface second conductive layer; When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface, the end portion of the first surface second conductive layer of the capacitor is the first surface first conductive layer. It may be positioned inside the edge of the layer.

A capacitor-embedded component according to an embodiment of the present disclosure includes: a first surface second conductive layer located on the first surface first inorganic layer; , in the first surface first organic layer in which an opening overlapping the first surface second conductive layer is formed, and in the opening of the first surface first organic layer on the first surface second conductive layer a first surface third conductive layer at least partially located, wherein the upper conductive layer of the capacitor is constituted by the first surface second conductive layer, and is aligned with the first surface of the substrate; When the first surface second conductive layer of the capacitor is viewed along the line direction, the first surface second conductive layer of the capacitor is at least partially aligned with the edge of the first surface first conductive layer. may overlap with

A capacitor-embedded component according to an embodiment of the present disclosure is located at least partially on the first surface first inorganic layer, and the first surface has an opening overlapping the first surface first inorganic layer. a first surface third conductive layer located in the opening of the first surface first organic layer on the first surface first inorganic layer, wherein the upper conductive layer of the capacitor; may be composed of the first surface third conductive layer.

An embodiment of the present disclosure is a mounting substrate including the capacitor-embedded component described above and an element mounted on the capacitor-embedded component.

An embodiment of the present disclosure includes the steps of providing a substrate including a first surface and a second surface opposite the first surface; forming a first surface first inorganic layer on the first surface first conductive layer; forming an upper conductive layer on a portion of the first surface first inorganic layer; forming a first surface first organic layer on the first surface first inorganic layer positioned on the first surface first conductive layer that does not overlap the upper conductive layer in plan view; In the method of manufacturing a capacitor-embedded component, the conductive layer, and the first-surface first conductive layer and the first-surface first inorganic layer overlapping the upper conductive layer in plan view form a capacitor.

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the first surface first organic layer may contain polyimide.

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor when the evaluation length is 150 μm is 0.1 μm or more and 0 0.4 μm or less.

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor is 0.22 μm or less when the evaluation length is 2.5 μm. may be

In the method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the side surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0 when the evaluation length is 150 μm. .4 μm or less, and the first surface first inorganic layer may at least partially cover the side surface of the first surface first conductive layer.

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the substrate may contain glass.

In the method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the substrate is provided with through holes, and the first surface first conductive layer and the first surface first conductive layer are electrically connected. and is electrically connected to the capacitor by a through-electrode located on the wall surface of the through-hole and a second-surface first conductive layer electrically connected to the through-electrode and located on the second surface. An inductor may be configured.

A method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure includes the steps of: forming at least partially on the upper conductive layer the first surface first organic layer having an opening overlapping the upper conductive layer; and forming a first surface third conductive layer in the opening of the first surface first organic layer on an upper conductive layer, the capacitor extending along a normal direction of the first surface of the substrate. When viewing the upper conductive layer of the capacitor, an end of the upper conductive layer of the capacitor may be located inside an end of the first surface first conductive layer.

A method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure includes the steps of: forming at least partially on the upper conductive layer the first surface first organic layer having an opening overlapping the upper conductive layer; and forming a first surface third conductive layer in the opening of the first surface first organic layer on an upper conductive layer, the capacitor extending along a normal direction of the first surface of the substrate. When viewing the upper conductive layer of the capacitor, the upper conductive layer of the capacitor may at least partially overlap an edge of the first surface first conductive layer.

In the method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the method for manufacturing a capacitor-embedded component includes forming the first surface first organic layer having an opening overlapping the first surface first inorganic layer of the capacitor. forming at least partially on the first surface first inorganic layer, wherein forming the upper conductive layer includes: forming the upper conductive layer on the first surface first inorganic layer of the capacitor; The upper conductive layer may be formed in the opening of the organic layer.

According to the embodiments of the present disclosure, miniaturization can be achieved.

1 is a cross-sectional view showing a component with a built-in capacitor according to one embodiment; FIG. FIG. 4 is a cross-sectional view showing an enlarged through-electrode of a component with a built-in capacitor; It is a top view which shows the 1st surface 1st conductive layer of a capacitor built-in component. FIG. 3 is a plan view showing a first inorganic layer and a second conductive layer on the first surface of the capacitor-embedded component; It is a top view which expands and shows a capacitor. It is a sectional view showing an enlarged capacitor. It is a sectional view showing a modification of a through-hole. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. It is a figure which shows the manufacturing process of a capacitor built-in component. FIG. 4 is a plan view showing a capacitor according to a first modified example; FIG. 4 is a cross-sectional view showing a capacitor according to a first modified example; FIG. 11 is a plan view showing a capacitor according to a second modified example; FIG. 10 is a cross-sectional view showing a capacitor according to a second modified example; It is a sectional view showing a modification of a through-hole. 1st surface It is sectional drawing which expands and shows an example of the upper surface of a 1st conductive layer. FIG. 2 is a cross-sectional view showing an example of a mounting substrate including a component with a built-in capacitor and an element; FIG. 3 is a diagram showing an example of a product on which a component with a built-in capacitor is mounted; FIG. 4 is a diagram showing evaluation results of leakage current in a capacitor and adhesiveness of a first inorganic layer on a first surface;

Hereinafter, a configuration of a capacitor-embedded component and a method of manufacturing the same according to an embodiment of the present disclosure will be described in detail with reference to the drawings. The embodiments shown below are examples of the embodiments of the present disclosure, and the present disclosure should not be construed as being limited to these embodiments. Also, in this specification, terms such as "substrate", "base material", "sheet" and "film" are not to be distinguished from each other based only on the difference in designation. For example, "substrate" and "base material" are concepts that include members that can be called sheets and films. Furthermore, terms used herein to specify shapes and geometric conditions and their degrees, such as terms such as "parallel" and "perpendicular", length and angle values, etc., are bound by strict meanings. However, it is interpreted to include the extent to which similar functions can be expected. In addition, in the drawings referred to in this embodiment, the same reference numerals or similar reference numerals may be assigned to the same portions or portions having similar functions, and repeated description thereof may be omitted. Also, the dimensional ratios in the drawings may differ from the actual ratios for convenience of explanation, and some of the configurations may be omitted from the drawings.

Capacitor-Built-In Component An embodiment of the present disclosure will be described below. First, the configuration of capacitor-embedded component 10 according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing a component 10 with a built-in capacitor.

A capacitor-embedded component 10 includes a substrate 12 , a capacitor 15 and an inductor 16 . The capacitor 15 is configured by part of the first wiring structure portion 30 provided on the first surface 13 side of the substrate 12 . The inductor 16 includes a portion of the first wiring structure portion 30 , a through electrode 22 provided in the through hole 20 of the substrate 12 , and a portion of the second wiring structure portion 40 provided on the second surface 14 side of the substrate 12 . It is composed of Each component of the capacitor built-in component 10 will be described below.

(substrate)
Substrate 12 includes a first side 13 and a second side 14 opposite first side 13 . Further, the substrate 12 is provided with a plurality of through holes 20 extending from the first surface 13 to the second surface 14 .

Substrate 12 includes an inorganic material having a certain insulating property. For example, the substrate 12 may be a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, a zirconia oxide (ZrO ₂ ) substrate, etc. Alternatively, these substrates are laminated. The substrate 12 may partially include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate.

Examples of the glass used for the substrate 12 include alkali-free glass. Alkali-free glass is glass that does not contain alkaline components such as sodium and potassium. Alkali-free glass includes, for example, boric acid instead of an alkaline component. Alkali-free glass also contains, for example, alkaline earth metal oxides such as calcium oxide and barium oxide. Examples of alkali-free glass include EN-A1 manufactured by Asahi Glass and Eagle XG manufactured by Corning. When the substrate 12 contains glass, the thickness T of the substrate 12 is, for example, 0.25 mm or more and 0.45 mm or less. Since the substrate 12 contains glass, the insulation of the substrate 12 can be improved compared to the case where the substrate 12 is made of silicon, thereby improving the withstand voltage characteristics of the capacitor 15 located on the substrate 12. can be done.

In FIG. 1 , symbol S1 represents the width of through hole 20 at the position where through hole 20 is connected to first surface 13 . The width S1 is, for example, 40 μm or more and 150 μm or less. Also, the ratio of the length of the through-hole 20 to the width S1 of the through-hole 20, that is, the aspect ratio of the through-hole 20 is, for example, 4 or more and 10 or less.

The through hole 20 formed in the substrate 12 may at least partially have a shape whose width decreases from the first surface 13 toward the second surface 14 of the substrate 12 . In the example shown in FIG. 1 , the through-hole 20 has a shape whose width decreases from the first surface 13 and the second surface 14 of the substrate 12 toward the central portion in the thickness direction of the substrate 12 . As a result, the width of the through-hole 20 is minimized at the central portion in the thickness direction of the substrate 12, as indicated by symbol S2 in FIG. Note that the "central portion" refers to an intermediate position in the thickness direction of the substrate 12, a range from the intermediate position to the first surface 13 side to 0.1×T, and 0.1 from the intermediate position to the second surface 14 side. Including the range up to ×T. Symbol T represents the thickness of substrate 12 as described above.

(through electrode)
FIG. 2 is an enlarged sectional view showing the through electrode 22 provided in the through hole 20. As shown in FIG. The through electrode 22 is a member positioned at least partially inside the through hole 20 and having electrical conductivity. In the present embodiment, the thickness of the through electrode 22 is smaller than the width of the through hole 20, so that there is a space inside the through hole 20 where the through electrode 22 does not exist. That is, the through electrode 22 is a so-called conformal via. The thickness of the through electrode 22 is, for example, 5 μm or more and 22 μm or less.

The method of forming the through electrode 22 is not particularly limited as long as the through electrode 22 has conductivity. For example, the through electrode 22 may be formed by a physical film forming method such as a vapor deposition method or a sputtering method, or may be formed by a chemical film forming method or a plating method. Further, the through electrode 22 may be composed of a single conductive layer, or may include a plurality of conductive layers. Here, as shown in FIG. 2, an example in which the through electrode 22 includes a first layer 221 and a second layer 222 will be described.

The first layer 221 is a layer at least partially located on the sidewall 21 of the through hole 20 and having electrical conductivity. The first layer 221 is formed on the side wall 21 by a physical film forming method such as a sputtering method or a vapor deposition method, a sol-gel method, or the like. Preferably, the first layer 221 is formed on the sidewalls 21 by a sputtering method. Thereby, the first layer 221 can be firmly adhered to the side wall 21 . The thickness of the first layer 221 is, for example, 0.05 μm or more and 1.0 μm or less. Another layer may be provided between the first layer 221 and the side wall 21 of the through hole 20 .

When the first layer 221 is formed by a physical film forming method, the material constituting the first layer 221 is metal such as titanium, chromium, nickel, copper, or an alloy using these metals, or a laminate of these. can be used. Further, when the first layer 221 is formed by the sol-gel method, zinc oxide or the like can be used as the material forming the first layer 221 . In addition to the sol-gel layer formed by the sol-gel method, the first layer 221 may further have an electroless plated layer containing a metal such as copper formed on the sol-gel layer by an electroless plating method. .

The second layer 222 is a conductive layer located on the first layer 221 . The second layer 222 contains, for example, copper as a main component, and more specifically contains 80% by mass or more of copper. Also, the second layer 222 may contain metals such as gold, silver, platinum, rhodium, tin, aluminum, nickel, and chromium, or alloys thereof. The second layer 222 is formed on the first layer 221 by electroplating. As a method for analyzing the composition of the second layer 222, for example, TEM (transmission electron microscope) or EDS (energy dispersive X-ray spectroscope) can be adopted. The thickness of the second layer 222 is, for example, 5 μm or more and 20 μm or less. Note that another conductive layer may be provided between the first layer 221 and the second layer 222 .

(First wiring structure part)
Next, the first wiring structure portion 30 will be described. The first wiring structure portion 30 has layers such as a conductive layer and an insulating layer provided on the first surface 13 side of the substrate 12 so as to configure an electrical circuit on the first surface 13 side of the substrate 12 . As will be described later, part of the first wiring structure portion 30 constitutes the capacitor 15 . A part of the first wiring structure 30 constitutes a part of the inductor 16 . In the present embodiment, the first wiring structure portion 30 includes a first surface first conductive layer 31, a first surface first inorganic layer 32, a first surface second conductive layer 33, a first surface first organic layer 34, It has a first surface third conductive layer 35 and a first surface second organic layer 36 .

[First surface first conductive layer]
The first surface first conductive layer 31 is a conductive layer located on the first surface 13 of the substrate 12 . The first surface first conductive layer 31 may be electrically connected to the through electrode 22 . In addition, the first surface first conductive layer 31 may be composed of a single layer having conductivity, or may include a plurality of layers having conductivity. For example, the first-surface first conductive layer 31 may include a first layer 221 and a second layer 222 that are laminated in order on the first surface 13 of the substrate 12, similar to the through electrodes 22 . Also, the first surface first conductive layer 31 may include only a part of the first layer 221 and the second layer 222 . The material forming the first surface first conductive layer 31 is the same as the material forming the through electrode 22 . The thickness of the first surface first conductive layer 31 is, for example, 100 nm or more and 20 μm or less, and may be 5 μm or more and 20 μm or less.

FIG. 3 is a plan view showing the through electrode 22 and the first surface first conductive layer 31 of the capacitor built-in component 10 as viewed from the first surface 13 side. The first surface first conductive layer 31 is provided on the first surface 13 side of the substrate 12 so as to constitute a part of the capacitor 15 and the inductor 16 . Note that layers such as the first surface first inorganic layer 32 laminated on the first surface first conductive layer 31 are omitted in FIG. Also, FIG. 1 corresponds to a cross-sectional view of the capacitor built-in component 10 shown in FIG. 3 or FIG. 4, which will be described later, taken along line AA.

[First surface first inorganic layer]
The first surface first inorganic layer 32 is a layer that is located at least partially on the first surface first conductive layer 31 and the first surface 13 of the substrate 12, contains an inorganic material, and has insulating properties. The inorganic material of the first surface first inorganic layer 32 preferably has a dielectric breakdown field of 6 MV/cm or more, more preferably 8 MV/cm or more. Silicon nitride such as SiN can be used as the inorganic material for the first surface first inorganic layer 32 . In addition, examples of inorganic materials for the first surface first inorganic layer 32 include silicon oxide, aluminum oxide, and tantalum pentoxide. The dielectric constant of the inorganic material of the first surface first inorganic layer 32 is, for example, 3 or more and 50 or less. Also, the thickness of the first surface first inorganic layer 32 is, for example, 50 nm or more and 400 nm or less. The first surface first inorganic layer 32 may be composed of a single layer or may include a plurality of layers.

Preferably, the leakage current in the inorganic material of the first surface first inorganic layer 32 is 1×10 ⁻⁸ A or less, more preferably 1×10 ⁻⁹ A or less, still more preferably 1×10 ⁻¹⁰ A or less, and particularly preferably 1×10 ⁻¹¹ A or less. Thereby, the electrical characteristics of the capacitor 15 including the first surface first inorganic layer 32 can be further improved.

The first surface first inorganic layer 32 may at least partially cover the edge 31 e and the side surface 312 of the first surface first conductive layer 31 . In other words, the first surface first inorganic layer 32 may be located not only on the top surface 311 of the first surface first conductive layer 31 but also on the side surface 312 . As a result, it is possible to prevent the first surface first conductive layer 31 from being damaged by the chemical used in the step of forming the first surface second conductive layer 33, the first surface first organic layer 34, and the like. It should be noted that "covering" means that, as shown in FIG. and the first surface first inorganic layer 32 overlap each other. In addition, the “upper surface” means the surface of the layers laminated on the substrate 12 that is located farther from the substrate 12 . In addition, the “lower surface” means the surface of the layers laminated on the substrate 12 that is located closer to the substrate 12 . In addition, "side surface" means a surface extending from the lower surface to the upper surface.

[First surface second conductive layer]
The first surface second conductive layer 33 is a conductive layer located on the first surface first inorganic layer 32 . As shown in FIG. 1 , the end portion 33 e of the first surface second conductive layer 33 is located on the first surface first inorganic layer 32 . The above-described first surface first conductive layer 31, the above-described first surface first inorganic layer 32 located on the first surface first conductive layer 31, and the first surface first inorganic layer 32 located on the first surface first inorganic layer 32 A capacitor 15 is configured by the surface second conductive layer 33 . Thus, in the present embodiment, the dielectric of the capacitor 15 is composed of the first surface first inorganic layer 32, and the lower conductive layer facing the dielectric from the substrate 12 side is the first surface first conductive layer. 31 and the upper conductive layer facing the dielectric from the side opposite to the substrate 12 is constituted by a first surface second conductive layer 33 .

The first-surface second conductive layer 33 includes a first layer 221 and a second layer 222 that are laminated in order on the first-surface first inorganic layer 32, like the through electrodes 22 and the first-surface first conductive layer 31. may include a plurality of conductive layers of The material forming the first surface second conductive layer 33 is the same as the material forming the through electrode 22 and the first surface first conductive layer 31 . The thickness of the first surface second conductive layer 33 is, for example, 100 nm or more and 20 μm or less.

FIG. 4 is a plan view showing the first surface first conductive layer 31, the first surface first inorganic layer 32, and the first surface second conductive layer 33 of the capacitor built-in component 10 when viewed from the first surface 13 side. be. In FIG. 4, layers such as a first surface first organic layer 34 and a first surface third conductive layer 35, which are laminated on the first surface second conductive layer 33, are omitted. In addition, in FIG. 4, the constituent elements covered with the first surface first inorganic layer 32 are indicated by dotted lines.

As shown in FIG. 4, the first surface first inorganic layer 32 may cover the first surface 13 of the substrate 12 and the first surface first conductive layer 31 over a wide area. For example, the first surface first inorganic layer 32 may cover at least the end portion 31 e of the first surface first conductive layer 31 constituting the capacitor 15 .

As shown in FIG. 5, openings 32a are formed in the first inorganic layer 32 on the first surface. The openings 32a are formed at the positions of the through holes 20, the connection positions between the first surface first conductive layer 31 and the first surface third conductive layer 35, and the like.

[First surface first organic layer]
The first surface first organic layer 34 is a layer that is located on the first surface first inorganic layer 32 and on the first surface second conductive layer 33, contains an organic material, and has insulating properties. As the organic material of the first surface first organic layer 34, polyimide, epoxy, or the like can be used. The organic material of the first surface first organic layer 34 preferably has a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and even more preferably 0.001 or less. By forming the first surface first organic layer 34 using an organic material having a small dielectric loss tangent, it is possible to suppress the electric signal that should pass through the capacitor 15 and the inductor 16 from passing through the first surface first organic layer 34. be able to. As a result, the band of the capacitor built-in component 10 including the capacitor 15 and the inductor 16 can be widened to the high frequency side.

As shown in FIG. 1, in the first surface first organic layer 34 located on the first surface second conductive layer 33 of the capacitor 15, an opening 34a overlapping the first surface second conductive layer 33 is formed. there is

[First surface, third conductive layer]
The first surface third conductive layer 35 is a conductive layer located on the first surface first conductive layer 31 or the first surface second conductive layer 33 . In the example shown in FIG. 1 , the first surface third conductive layer 35 is electrically connected to the first surface first conductive layer 31 forming the lower conductive layer of the capacitor 15 . Including the portion of layer 34 located in opening 34a. In addition, the first surface third conductive layer 35 has an opening 34 a in the first surface first organic layer 34 so as to be electrically connected to the first surface second conductive layer 33 constituting the upper conductive layer of the capacitor 15 . Including the part located in

The first surface third conductive layer 35 may include a plurality of conductive layers such as a first layer 221 and a second layer 222 that are laminated in order, like the through electrodes 22 and the first surface first conductive layer 31. good. The material forming the first surface third conductive layer 35 is the same as the material forming the through electrode 22 and the first surface first conductive layer 31 .

[First surface second organic layer]
The first surface second organic layer 36 is located on the first surface first organic layer 34 and the first surface third conductive layer 35, and is a layer containing an organic material and having insulating properties. Like the first surface first organic layer 34, the first surface second organic layer 36 preferably has a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and still more preferably 0.001 or less. Including materials. As the organic material for the first surface second organic layer 36, polyimide, epoxy, or the like can be used similarly to the first surface first organic layer 34. FIG.

(Second wiring structure part)
Next, the second wiring structure portion 40 will be described. The second wiring structure portion 40 has layers such as a conductive layer and an insulating layer provided on the second surface 14 side of the substrate 12 so as to form an electrical circuit on the second surface 14 side. A part of the second wiring structure 40 , a part of the first wiring structure 30 and the through electrode 22 constitute the inductor 16 . In the present embodiment, the second wiring structure portion 40 has a second surface first conductive layer 41 and a second surface first organic layer 43 .

[Second surface first conductive layer]
The second surface first conductive layer 41 is a conductive layer located on the second surface 14 of the substrate 12 . The second surface first conductive layer 41 may be electrically connected to the through electrode 22 .

The second surface first conductive layer 41 includes a first layer 221 and a second layer 222 which are laminated in order on the second surface 14 of the substrate 12 , like the through electrodes 22 and the first surface first conductive layer 31 . Multiple conductive layers may be included. The material forming the second surface first conductive layer 41 is the same as the material forming the through electrode 22 . The thickness of the second surface first conductive layer 41 is, for example, 100 nm or more and 20 μm or less.

[Second surface first organic layer]
The second surface first organic layer 43 is a layer that is located on the second surface first conductive layer 41 and the second surface 14 of the substrate 12, contains an organic material, and has insulating properties. Like the first surface first organic layer 34 and the first surface second organic layer 36, the second surface first organic layer 43 is preferably 0.003 or less, more preferably 0.002 or less, still more preferably 0. Contains organic materials having a loss tangent of 0.001 or less. As the organic material for the second surface first organic layer 43, polyimide, epoxy, or the like can be used similarly to the first surface first organic layer 34 and the first surface second organic layer 36. FIG.

(Capacitor)
Next, the capacitor 15 will be described in detail with reference to FIGS. 5 and 6. FIG. FIG. 5 is a plan view showing an enlarged capacitor 15. As shown in FIG. 6 is a cross-sectional view of the capacitor 15 cut along line BB in FIG. 5 and 6, the first surface first organic layer 34, the first surface third conductive layer 35, and the first surface second organic layer 36 are omitted.

As shown in FIG. 6, the upper surface 311 of the first surface first conductive layer 31 of the capacitor 15 may have an uneven shape. As a result, the area of the upper surface 311 facing the first surface second conductive layer 33 can be increased, and the capacitance of the capacitor 15 can be increased, as compared with the case where the upper surface 311 is flat. In addition, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced. The average surface roughness of the upper surface 311 of the first surface first conductive layer 31 is, for example, 0.1 μm or more and 0.4 μm or less. The average surface roughness is, for example, the arithmetic mean surface roughness specified in JIS B 0601:2001. The average surface roughness is measured within a square area having a side length of L1, as shown in FIGS. Length L1 is, for example, 150 μm.

As shown in FIG. 6, the side surface 312 of the first surface first conductive layer 31 of the capacitor 15 may also have an uneven shape like the top surface 311 . The side surface 312 of the first surface first conductive layer 31 is the edge of the first surface first conductive layer 31 when the first surface first conductive layer 31 is viewed along the normal direction of the first surface 13 of the substrate 12 . This is the portion that defines the portion 31e. Since the side surface 312 has an uneven shape, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced by, for example, an anchor effect. This is because the uneven shape of the side surface 312 locks the first surface first inorganic layer 32 to the displacement of the first surface first inorganic layer 32 in contact with the side surface 312 in the normal direction of the first surface 13 of the substrate 12 . This is because it can be suppressed by The average surface roughness of the side surface 312 of the first surface first conductive layer 31 is the same as the average surface roughness of the side surface 312, and is, for example, 0.1 μm or more and 0.4 μm or less.

As will be described later, the uneven shape of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 is formed in the step of removing unnecessary portions of the first layer 221 of the first surface first conductive layer 31 by etching. The upper surface 311 and the side surfaces 312 are exposed to the etchant and scraped.

As shown in FIG. 5, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the edge of the first surface second conductive layer 33 of the capacitor 15 The portion 33 e is located inside the end portion 31 e of the first surface first conductive layer 31 . For example, as shown in FIG. 5, when the first surface second conductive layer 33 of the capacitor 15 has a substantially rectangular shape including four corners 31f, the ends 33e forming the four sides are , located inside the end portion 31 e of the first surface first conductive layer 31 . In other words, when viewing the first surface second conductive layer 33 of the capacitor 15 along the normal direction of the first surface 13 of the substrate 12 , the first surface second conductive layer 33 is the first surface first conductive layer 31 side 312 of the . Advantages of configuring the first surface second conductive layer 33 in this way will be described below. The term “inner side” means the center side of capacitor 15 in plan view.

In the step of forming the first surface first inorganic layer 32 , the first surface first inorganic layer 32 is less likely to be formed on the side surface 312 of the first surface first conductive layer 31 than on the top surface 311 . Therefore, the thickness of the first surface first inorganic layer 32 on the side surface 312 is smaller than the thickness of the first surface first inorganic layer 32 on the top surface 311 . Also, it is conceivable that the first surface first inorganic layer 32 is not formed on a portion of the side surface 312 and, therefore, the first surface first conductive layer 31 is exposed. Therefore, when the first surface second conductive layer 33 extends to a position overlapping the side surface 312 of the first surface first conductive layer 31 , in other words, the first surface second conductive layer 33 extends to the first surface on the side surface 312 . When the surface first inorganic layer 32 is covered, the risk of the first surface second conductive layer 33 coming into contact with the exposed first surface first conductive layer 31 increases.

In contrast, in the present embodiment, the end portion 33e of the first surface second conductive layer 33 of the capacitor 15 is located inside the end portion 31e of the first surface first conductive layer 31 . Therefore, it is possible to reduce the risk that the first surface second conductive layer 33 contacts the side surface 312 of the first surface first conductive layer 31 and causes an electrical short.

(Modified example of through hole)
FIG. 7 is a cross-sectional view showing a modified example of the through hole 20. As shown in FIG. As shown in FIG. 7 , capacitor-embedded component 10 may include organic layer 26 positioned closer to the center of through-hole 20 than through-electrode 22 . Note that the “center side” means that the distance between the organic layer 26 and the side wall 21 is greater than the distance between the through electrode 22 and the side wall 21 inside the through hole 20 . Organic layer 26 preferably comprises an organic material having a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and even more preferably 0.001 or less. As an organic material for the organic layer 26, polyimide, epoxy, or the like can be used. By configuring the organic layer 26 using an organic material with a small dielectric loss tangent, it is possible to suppress part of the electrical signal that should pass through the capacitor 15 and the inductor 16 from passing through the organic layer 26 . As a result, the band of the capacitor built-in component 10 including the capacitor 15 and the inductor 16 can be widened to the high frequency side.

Also, although not shown, the through electrode 22 may be a filled via filled in the through hole 20 . In this case, the through electrode 22 extends at least partially to the center point of the through hole 20 in the surface direction of the first surface 13 .

Method for Manufacturing Capacitor-Built-In Component An example of a method for manufacturing the capacitor-embedded component 10 will now be described with reference to FIGS. 8 to 15. FIG.

(Through hole forming step)
First, the substrate 12 is prepared. Next, a resist layer is provided on at least one of the first surface 13 and the second surface 14 . After that, openings are provided in the resist layer at positions corresponding to the through holes 20 . Next, by processing the substrate 12 in the openings of the resist layer, through holes 20 can be formed in the substrate 12 as shown in FIG. As a method for processing the substrate 12, a dry etching method such as a reactive ion etching method or a deep reactive ion etching method, a wet etching method, or the like can be used.

The through holes 20 may be formed in the substrate 12 by irradiating the substrate 12 with a laser. In this case, the resist layer may not be provided. As a laser for laser processing, an excimer laser, Nd:YAG laser, femtosecond laser, or the like can be used. When an Nd:YAG laser is employed, a fundamental wave with a wavelength of 1064 nm, a second harmonic with a wavelength of 532 nm, a third harmonic with a wavelength of 355 nm, or the like can be used.

Alternatively, laser irradiation and wet etching can be combined as appropriate. Specifically, first, an altered layer is formed in a region of the substrate 12 where the through hole 20 is to be formed by laser irradiation. Subsequently, the substrate 12 is immersed in hydrogen fluoride or the like to etch the altered layer. Through holes 20 can thus be formed in the substrate 12 . Alternatively, the through holes 20 may be formed in the substrate 12 by blasting the substrate 12 with an abrasive.

By processing the substrate 12 from both the first surface 13 side and the second surface 14 side, a through hole 20 having a shape whose width decreases toward the central portion in the thickness direction of the substrate 12 as shown in FIG. 8 is formed. can do.

(Through electrode forming step)
Next, the through electrodes 22 are formed on the sidewalls 21 of the through holes 20 . In this embodiment, simultaneously with the through electrode 22, the first surface first conductive layer 31 is formed on part of the first surface 13 of the substrate 12, and the second surface conductive layer 31 is formed on part of the second surface 14 of the substrate 12. An example of forming the first conductive layer 41 will be described.

First, as shown in FIG. 9, a first layer 221 is formed on the first surface 13, the second surface 14, and the sidewalls 21 of the substrate 12 by a physical film forming method, a sol-gel method, an electroless plating method, or the like. The first layer 221 is formed preferably by a physical deposition method, particularly preferably by a sputtering method. As a result, the first layer 221 can be firmly adhered to the first surface 13 , the second surface 14 and the sidewalls 21 of the substrate 12 . A physical film forming method such as a sputtering method or a vapor deposition method is preferably performed from both the first surface 13 side and the second surface 14 side. In this case, the side wall 21 of the through-hole 20 is adhered with the conductive substance flying from the first surface 13 side and the conductive substance flying from the second surface 14 side.

Subsequently, as shown in FIG. 10, a resist layer 37 is partially formed on the first layer 221 . As a material for the resist layer 37, a photosensitive material such as a dry film resist containing acrylic resin can be used.

Subsequently, as shown in FIG. 11, a second layer 222 is formed by electroplating on the first layer 221 not covered with the resist layer 37 . For example, the substrate 12 is immersed in an electrolytic plating solution containing copper. Also, a current is passed through the first layer 221 . This allows the second layer 222 to be deposited on the first layer 221 .

(Resist and conductive layer removal step)
After that, as shown in FIG. 12, the resist layer 37 is removed. Subsequently, as shown in FIG. 13, the portion of the first layer 221 covered with the resist layer 37, in other words, the portion of the first layer 221 exposed from the second layer 222 is wet-etched, for example. Remove by In this manner, the through electrode 22 including the first layer 221 and the second layer 222, the first surface first conductive layer 31 and the second surface first conductive layer 41 can be formed. As a result, the second surface first conductive layer 41, the through electrode 22 electrically connected to the second surface first conductive layer 41, and the first surface first conductive layer electrically connected to the through electrode 22 31 can be constructed. Note that a step of annealing the conductive layer such as the second layer 222 may be performed.

By the way, in the step of removing the portion of the first layer 221 covered with the resist layer 37 by wet etching, the second layer 222 is also exposed to the etchant, so the surface of the second layer 222 is also partially etched. be done. As a result, as described above, the top surface 311 and the side surfaces 312 of the first surface first conductive layer 31 are uneven, and the average surface roughness of the top surface 311 and the side surfaces 312 increases.

The longer the second layer 222 is exposed to the etchant, the greater the average surface roughness of the top surface 311 and side surfaces 312 . By the way, in the present embodiment, the first surface first conductive layer 31 is formed integrally with the through electrode 22 that constitutes a part of the inductor 16 . In order to improve electrical characteristics such as high-frequency characteristics of the inductor 16, it is preferable to increase the thickness of the first layer 221 and the second layer 222 forming the inductor 16 to reduce the electrical resistance of the inductor 16. FIG. As the thickness of the first layer 221 increases, the time required to etch away the first layer 221 increases, and the time during which the second layer 222 is exposed to the etchant increases. As a result, the average surface roughness of the top surface 311 and side surfaces 312 of the first surface first conductive layer 31 also increases. By increasing the average surface roughness of the top surface 311 and side surfaces 312 of the first surface first conductive layer 31 to some extent, the area of the top surface 311 facing the first surface second conductive layer 33 is increased, and the capacitance of the capacitor 15 is increased. can be increased.

When the first layer 221 contains chromium and the second layer 222 contains copper, an aqueous solution of potassium permanganate, for example, can be used as an etchant for removing the first layer 221 . Further, when the first layer 221 contains titanium and the second layer 222 contains copper, for example, a titanium etchant Ti3991 manufactured by Meltex can be used as the etchant.

If the average surface roughness of the upper surface 311 of the first surface first conductive layer 31 becomes too large, the variation in the thickness of the first surface first inorganic layer 32 formed on the upper surface 311 increases. A portion of the first surface first conductive layer 31 may be exposed from the first surface first inorganic layer 32 . In addition, considering this point that the leakage current of the capacitor 15 provided with the first surface first inorganic layer 32 may increase, as described above, the average of the upper surface 311 of the first surface first conductive layer 31 It is preferable to set the surface roughness to 0.4 μm or less.

(Step of forming first inorganic layer on first surface and second conductive layer on first surface)
Next, as shown in FIG. 14 , the first surface first inorganic layer 32 is formed on the second layer 222 of the first surface first conductive layer 31 and on the first surface 13 of the substrate 12 . As a method for forming the first surface first inorganic layer 32, for example, plasma CVD, sputtering, atomic layer deposition, or the like can be adopted. Further, as shown in FIG. 14, a first surface second conductive layer 33 is formed on a portion of the first surface first inorganic layer 32 . As a result, the first surface first conductive layer 31, the first surface first inorganic layer 32 on the first surface first conductive layer 31, and the first surface second conductive layer on the first surface first inorganic layer 32 33 can be configured. The process of forming the first surface second conductive layer 33 is the same as the process of forming the first surface first conductive layer 31, so the description thereof is omitted.

The timing of patterning the first surface first inorganic layer 32 so that the first surface first inorganic layer 32 has the shape shown in FIG. 14 is arbitrary. For example, the first surface first inorganic layer 32 may be patterned before forming the first surface second conductive layer 33 on the first surface first inorganic layer 32, and the first surface second conductive layer 33 may be formed. After that, the first surface first inorganic layer 32 may be patterned. Also, although not shown, after forming a first surface first organic layer 34 shown in FIG. The first inorganic layer 32 may be patterned.

(Step of forming first organic layer on first surface)
Next, as shown in FIG. 15, a first surface first organic layer 34 is formed on a portion of the first surface second conductive layer 33 and a portion of the first surface first inorganic layer 32 . For example, first, a first surface film (not shown) having a photosensitive layer containing an organic material and a substrate is attached to the first surface 13 side of the substrate 12 . Subsequently, the first surface side film is subjected to exposure processing and development processing. As a result, the first surface first organic layer 34 made of the photosensitive layer of the first surface side film and having the openings 34a overlapping the first surface second conductive layer 33 or the first surface first conductive layer 31 is formed. It can be formed on the first surface 13 side of the substrate 12 . At this time, similarly to the case of the first surface first organic layer 34, as shown in FIG. A surface first organic layer 43 may be formed.

The opening 34a of the first surface first organic layer 34 is located at the position where the first surface third conductive layer 35 and the first surface first conductive layer 31 are connected, and the first surface third conductive layer 35 and the first surface It is formed at a position where it is connected to the second conductive layer 33 or the like.

The method of forming the first surface first organic layer 34 and the second surface first organic layer 43 is not limited to the method using a film. For example, first, a liquid containing an organic material such as polyimide is applied by spin coating or the like and dried to form an organic layer. Subsequently, the first surface first organic layer 34 and the second surface first organic layer 43 can be formed by subjecting the organic layer to exposure processing and development processing.

In addition, by causing part of the first surface first organic layer 34 and part of the second surface first organic layer 43 to reach the inside of the through hole 20, as shown in FIG. You may form the organic layer 26 in . Note that the organic layer 26 may be formed inside the through-hole 20 in a process different from that of the first surface first organic layer 34 and the second surface first organic layer 43 .

After that, although not shown, a first surface third conductive layer 35 is formed on the first surface first organic layer 34 . The first-surface third conductive layer 35 is also formed in the opening 34a of the first-surface first organic layer 34, whereby the first-surface third conductive layer 35 is connected to the first-surface first organic layer 34 through the opening 34a. It can be connected to the conductive layer 31 or the first surface second conductive layer 33 . Also, the first surface second organic layer 36 is formed on part of the first surface first organic layer 34 and on part of the first surface third conductive layer 35 . In this way, the capacitor built-in component 10 shown in FIG. 1 can be obtained.

The effects brought about by this embodiment will be described below.

In this embodiment, the upper surface 311 of the first surface first conductive layer 31 of the capacitor 15 has an uneven shape. As a result, the area of the upper surface 311 facing the first surface second conductive layer 33 can be increased, and the capacitance of the capacitor 15 can be increased, as compared with the case where the upper surface 311 is flat. As a result, it is possible to provide the capacitor-embedded component 10 including the small-sized, large-capacity capacitor 15 . Also, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 of the capacitor 15 can be enhanced. This prevents the first surface first inorganic layer 32 from peeling off from the first surface first conductive layer 31 , thereby increasing the reliability of the capacitor 15 .

The side surface 312 of the first surface first conductive layer 31 of the capacitor 15 also has an uneven shape like the top surface 311 . Therefore, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced by the anchor effect. Thereby, the reliability of the capacitor 15 can be further improved.

Various modifications can be made to the above-described embodiment. Modifications will be described below with reference to the drawings as necessary. In the following description and the drawings used in the following description, the same reference numerals as those used for the corresponding portions in the above-described embodiment are used for the parts that can be configured in the same manner as in the above-described embodiment, Duplicate explanations are omitted. Further, when it is clear that the effects obtained in the above-described embodiment can also be obtained in the modified example, the explanation thereof may be omitted.

(First Modification of Capacitor)
In the embodiment described above, as shown in FIG. An example in which the end portion 33e of the surface second conductive layer 33 is located inside the end portion 31e of the first surface first conductive layer 31 is shown. However, the positional relationship between the first surface first conductive layer 31 and the first surface second conductive layer 33 is not limited to the example shown in FIG.

FIG. 16 is a plan view showing the capacitor 15 of the capacitor-embedded component 10 according to this modification. 17 is a cross-sectional view of the capacitor 15 cut along the line CC of FIG. 16. As shown in FIG. 16 and 17, the first surface first organic layer 34, the first surface third conductive layer 35, and the first surface second organic layer 36 are omitted.

In this modification, as shown in FIG. 16, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the first surface second conductive layer 33 at least partially overlaps the edge 31 e of the first surface first conductive layer 31 . In other words, when viewing the first surface second conductive layer 33 of the capacitor 15 along the normal direction of the first surface 13 of the substrate 12 , the first surface second conductive layer 33 is the first surface first conductive layer 31 overlaps the side surface 312 of the . Advantages of configuring the first surface second conductive layer 33 in this way will be described below.

As a method for forming the first surface second conductive layer 33 on a portion of the first surface first inorganic layer 32, the following method can be used. First, the first surface second conductive layer 33 is provided over a wide area on the first surface first inorganic layer 32 , and then a resist layer is provided on the first surface second conductive layer 33 . Thereafter, the resist layer is patterned by photolithography to partially leave the resist layer on the first surface second conductive layer 33 . Subsequently, the portion of the first surface second conductive layer 33 that is not covered with the resist layer is removed by etching.

By the way, the resolution of the photolithographic method is limited. Therefore, even if an attempt is made to form a rectangular resist layer, it is difficult to obtain a resist layer having ideally sharp corners. As a result, as shown in FIG. 16, the corner 33f of the first surface second conductive layer 33 having a shape corresponding to the resist layer also has a curved shape. The degree of curvature at the corner 33f varies depending on the etching time and the like. Therefore, when the corner 33f of the first surface second conductive layer 33 overlaps with the first surface first conductive layer 31, the first surface second conductive layer 33 of the first surface second conductive layer 33 faces the first surface first conductive layer 31. The area of the part where the As a result, the capacitance of the capacitor 15 tends to vary as well.

In contrast, in this modification, the first surface second conductive layer 33 at least partially overlaps the end portion 31e of the first surface first conductive layer 31 . For example, when the first-surface second conductive layer 33 has a substantially rectangular shape in plan view, of the end portions 33e of the first-surface second conductive layer 33, the end portions 33e forming a pair of opposing sides It is positioned outside the end portion 31 e of the surface first conductive layer 31 . Thereby, it is possible to prevent the curved corner 33 f of the first surface second conductive layer 33 from overlapping the first surface first conductive layer 31 . As a result, variation in the area of the portion of the first surface second conductive layer 33 that faces the first surface first conductive layer 31 is suppressed, and variation in capacitance of the capacitor 15 is suppressed. can be done. The “outer side” means the side away from the center of the capacitor 15 in plan view. A distance d between the end portion 31e of the first surface first conductive layer 31 and the end portion 33e of the first surface second conductive layer 33 in plan view is, for example, 20 μm or more and 500 μm or less.

(Second Modification of Capacitor)
FIG. 18 is a plan view showing the capacitor 15 of the capacitor-embedded component 10 according to this modification. 19 is a cross-sectional view of the capacitor 15 taken along the line DD in FIG. 18. As shown in FIG. In this modification, the upper conductive layer facing the first surface first inorganic layer 32 which is the dielectric of the capacitor 15 from the side opposite to the substrate 12 is composed of the first surface third conductive layer 35 . 18 and 19, the first surface second organic layer 36 is omitted.

A method of manufacturing the capacitor 15 according to this modification will be described. In this modification, after forming the first surface first inorganic layer 32, the step of forming the first surface first organic layer 34 is performed. Specifically, the first surface first organic layer 34 having the openings 34 a overlapping the first surface first inorganic layer 32 of the capacitor 15 is at least partially covered with the first surface first inorganic layer 32 of the capacitor 15 . to form. At this time, the opening 34a of the first surface first organic layer 34 is formed inside the first surface first conductive layer 31, as shown in FIGS.

Thereafter, a first surface third conductive layer 35 is formed on the first surface first organic layer 34 and in the opening 34a. Thereby, the first surface third conductive layer 35 can be laminated on the first surface first inorganic layer 32 inside the opening 34a. The first surface third conductive layer 35 formed on the first surface first inorganic layer 32 inside the opening 34 a functions as the upper conductive layer of the capacitor 15 .

When the first surface third conductive layer 35 has a substantially rectangular shape in a plan view, the first surface third conductive layer 35 preferably has an end portion of the first surface third conductive layer 35 as shown in FIG. End portions 35e forming a pair of opposing sides of 35e are formed so as to be positioned on the first surface first organic layer 34 rather than inside the opening 34a. This can prevent the curved corner 35f of the first surface third conductive layer 35 from overlapping the first surface first conductive layer 31 . As a result, variation in the area of the portion of the first surface third conductive layer 35 that faces the first surface first conductive layer 31 via the first surface first inorganic layer 32 is suppressed, and the capacitor 15 capacitance variation can be suppressed. Preferably, as shown in FIG. 18, of the end portions 35e of the first-surface third conductive layer 35, the end portions 35e forming a pair of opposing sides are closer to each other than the end portions 31e of the first-surface first conductive layer 31. are also located outside.

(Modified example of through hole)
In the above-described embodiment, an example is shown in which the width of the through hole 20 in the surface direction of the substrate 12 decreases from the first surface 13 and the second surface 14 of the substrate 12 toward the central portion in the thickness direction of the substrate 12. rice field. However, the present invention is not limited to this, and as shown in FIG. 20, the width of the through hole 20 may decrease from the first surface 13 side toward the second surface 14 side.

(Modified example of average surface roughness)
In the above-described embodiment, as the average surface roughness of the top surface 311 and the side surface 312 of the first surface first conductive layer 31, the arithmetic mean surface roughness defined in JIS B 0601:2001 is used. . A square area with a side length of 150 μm is shown as an example of the measurement range of the average surface roughness. That is, an example is shown in which the size of the area scanned by the measuring device during measurement is 150 μm. In addition, the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 calculated by scanning an area of 150 μm based on JIS B 0601:2001 is preferably 0.1 μm or more and An example of 0.4 μm or less is shown. However, the method of measuring the average surface roughness and the preferred range are not limited to the above examples. An example of measuring the average surface roughness of the top surface 311 and the side surface 312 of the first surface first conductive layer 31 by a method different from the above method will be described below. Such separate measurement methods may be employed in place of the measurement methods described above, or may be employed in addition to the measurement methods described above. Further, in the following description, the dimension of the area scanned by the measuring instrument when measuring the surface roughness is also referred to as the evaluation length.

First, the state of the top surface 311 and the side surface 312 of the first surface first conductive layer 31 assumed in this modified example will be described. FIG. 21 is a cross-sectional view showing an enlarged example of the upper surface 311 of the first surface first conductive layer 31. As shown in FIG. As shown in FIG. 21, the top surface 311 of the first surface first conductive layer 31 has an uneven shape with a first period P1 and an uneven shape with a second period smaller than the first period P1. The first period P1 is, for example, the period of the uneven shape caused by variations in the thickness of the plating layer formed by the plating method among the layers constituting the first surface first conductive layer 31 . The first period P1 is, for example, 0.4 μm or more and 1.0 μm or less. The second period P2 is, for example, the period of the uneven shape formed by exposing the surface of the first surface first conductive layer 31 to the etchant and scraping it. The second period P2 is, for example, 0.05 μm or more and 0.4 μm or less.

As a result of repeated studies by the inventor of the present invention, the average surface roughness caused by the uneven shape of the second period P2 is higher than the average surface roughness caused by the uneven shape of the first period P1. It was found that there is a high correlation between the adhesion of the first surface first inorganic layer 32 to the layer 31 and the capacity of the capacitor 15 . In addition, it was found that the evaluation length should preferably be smaller than 150 μm in the case of the present embodiment, in order to measure the average surface roughness caused by the uneven shape of the second period P2. Based on these findings, in this modified example, as the average surface roughness, the arithmetic mean surface roughness specified in JIS R 1683: 2007 is adopted, and the evaluation length is proposed to be 2.5 μm. do. This makes it possible to calculate an average surface roughness having a higher correlation with the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 and the capacitance of the capacitor 15 .

Based on JIS R 1683:2007, the average surface roughness of the top surface 311 and the side surface 312 of the first conductive layer 31 calculated when measuring with an evaluation length of 2.5 μm is preferably 0.5 μm. It is 22 μm or less, more preferably 0.2 μm or less. Thereby, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced. Also, the capacity of the capacitor 15 can be increased. Also, based on JIS R 1683:2007, the average surface roughness of the upper surface 311 and the side surface 312 of the first conductive layer 31, which is calculated when measuring with an evaluation length of 2.5 μm, is preferably It is 0.075 μm or more, more preferably 0.80 μm or more.

An atomic force microscope can be used as a measuring instrument for calculating the arithmetic mean surface roughness defined in JIS R 1683:2007. For example, a roughness measurement function based on JISR1683, which is installed in AFM5000 manufactured by Hitachi High-Technologies Corporation, can be used.

As the average surface roughness of the top surface 311 and side surfaces 312 of the first surface first conductive layer 31, the arithmetic average surface roughness of the top surfaces 311 and side surfaces 312 of a plurality of, for example, ten first surface first conductive layers 31 is calculated as described above. may be measured using a measuring instrument and their average value may be adopted.

Mounting Board FIG. 22 is a sectional view showing an example of a mounting board 60 including the capacitor built-in component 10 and the element 50 mounted on the capacitor built-in component 10 . The element 50 is an LSI chip such as a logic IC or memory IC. Also, the element 50 may be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic device in which mechanical elements, sensors, actuators, electronic circuits, etc. are integrated on one substrate. As shown in FIG. 22, element 50 has terminals 51 electrically connected to a conductive layer such as first surface third conductive layer 35 of capacitor-embedded component 10 .

Examples of Products Mounted with Conducting Electrode Board FIG. 23 is a diagram showing an example of a product on which the capacitor built-in component 10 according to the embodiment of the present disclosure can be mounted. The capacitor-embedded component 10 according to the embodiment of the present disclosure can be used in various products. For example, it is installed in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smart phone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, and the like.

(Other embodiments)
Since the dielectric constant and the dielectric loss are generally in a trade-off relationship, it is difficult to increase the dielectric constant excessively. In order to realize a small-sized and large-capacity capacitor, it is necessary to devise from a different point of view.

Another embodiment of the present disclosure aims to provide a capacitor-embedded component that can effectively solve such problems.

One embodiment of the present disclosure comprises a substrate including a first surface and a second surface opposite the first surface, and a capacitor located on the first surface of the substrate, the capacitor comprising: a first surface first conductive layer located on the first surface of the substrate; a first surface first inorganic layer located on the first surface first conductive layer; and a first surface first inorganic layer on the first surface and an upper conductive layer located in the upper surface of the capacitor, the average surface roughness of the upper surface of the first conductive layer on the first surface of the capacitor when the evaluation length is 150 μm is 0.1 μm or more and 0.4 μm or less It is a component with a built-in capacitor.

In the capacitor-embedded component according to one embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor is 0.2.2 μm or less when the evaluation length is 2.5 μm. There may be.

In the capacitor-embedded component according to one embodiment of the present disclosure, the side surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm. and the first surface first inorganic layer may at least partially cover the side surface of the first surface first conductive layer.

In the capacitor-embedded component according to one embodiment of the present disclosure, the first surface first conductive layer of the capacitor has a thickness of 0.05 μm or more and 1.0 μm or less and is conductive; a second layer having a thickness of 5 μm or more and 20 μm or less, positioned on the first layer, and having conductivity.

In the capacitor-embedded component according to one embodiment of the present disclosure, the first layer may contain titanium or chromium.

In the capacitor-embedded component according to one embodiment of the present disclosure, the second layer may contain copper.

In the capacitor-embedded component according to one embodiment of the present disclosure, the substrate may contain glass.

In the capacitor-embedded component according to one embodiment of the present disclosure, the substrate is provided with a through hole, the capacitor-embedded component further includes an inductor electrically connected to the capacitor, the inductor being the first a first surface first conductive layer; a through electrode electrically connected to the first surface first conductive layer and including the first layer and the second layer located on the wall surface of the through hole; a second surface first conductive layer electrically connected to an electrode and including the first layer and the second layer located on the second surface of the substrate.

A capacitor-embedded component according to one embodiment of the present disclosure comprises: a first-surface second conductive layer located on the first-surface first inorganic layer; a first surface first organic layer located on a layer and having an opening overlapping the first surface second conductive layer; and the first surface first organic layer on the first surface second conductive layer. a first surface third conductive layer at least partially located in the opening of the substrate, wherein the upper conductive layer of the capacitor is constituted by the first surface second conductive layer of the substrate; When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface, the end portion of the first surface second conductive layer of the capacitor is the first surface first conductive layer. It may be positioned inside the edge of the layer.

A capacitor-embedded component according to an embodiment of the present disclosure includes: a first surface second conductive layer located on the first surface first inorganic layer; , a first surface first organic layer formed with an opening overlapping with the first surface second conductive layer; a partially located first surface third conductive layer, wherein the upper conductive layer of the capacitor is constituted by the first surface second conductive layer, and is aligned with the first surface of the substrate; When the first surface second conductive layer of the capacitor is viewed along the line direction, the first surface second conductive layer of the capacitor is at least partially aligned with the edge of the first surface first conductive layer. may overlap with

A capacitor-embedded component according to an embodiment of the present disclosure is located at least partially on the first-surface first inorganic layer, and includes a first-surface first surface portion having an opening overlapping the first-surface first inorganic layer. 1 organic layer, and a first surface third conductive layer located in the opening of the first surface first organic layer on the first surface first inorganic layer, wherein the upper conductive layer of the capacitor may be composed of the first surface third conductive layer.

An embodiment of the present disclosure is a mounting substrate including the capacitor-embedded component described above and an element mounted on the capacitor-embedded component.

One embodiment of the present disclosure includes the steps of providing a substrate including a first surface and a second surface opposite the first surface; forming a resist layer partially on the first layer; and forming a conductive second layer on the first layer not covered by the resist layer by electroplating. forming a layer; removing the resist layer; removing a portion of the first layer exposed from the second layer by etching; forming an inorganic layer; and forming an upper conductive layer on the first inorganic layer, the first conductive layer including the first layer and the second layer; , the first surface first inorganic layer on the second layer of the first surface first conductive layer and the upper conductive layer on the first surface first inorganic layer constitute a capacitor, and the capacitor wherein the average surface roughness of the upper surface of the first conductive layer of 1 is 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm.

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor is 0.22 μm or less when the evaluation length is 2.5 μm. may be

In the method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the side surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0 when the evaluation length is 150 μm. .4 μm or less, and the first surface first inorganic layer may at least partially cover the side surface of the first surface first conductive layer.

In the method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the first layer has a thickness of 0.05 μm or more and 1.0 μm or less, and the second layer has a thickness of 5 μm or more and 20 μm or less. may

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the substrate may contain glass.

In the method of manufacturing a capacitor-embedded component according to an embodiment of the present disclosure, the substrate is provided with a through hole, and the first layer and the second layer are formed on the wall surface of the through hole and the second layer of the substrate. Through electrodes are also formed on two surfaces and include the first conductive layer on the first surface, the first layer and the second layer on the wall surface of the through hole, and the first conductive layer on the second surface. The layer and the second surface first conductive layer including the second layer may form an inductor electrically connected to the capacitor.

A method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure includes the steps of: forming a first surface first organic layer having an opening overlapping with the upper conductive layer at least partially on the upper conductive layer; and forming a first surface third conductive layer in the opening of the first surface first organic layer on the conductive layer, and forming the capacitor along the normal direction of the first surface of the substrate. When viewing the upper conductive layer of the capacitor, an end of the upper conductive layer of the capacitor may be located inside an end of the first surface first conductive layer.

A method for manufacturing a capacitor-embedded component according to an embodiment of the present disclosure includes the steps of: forming a first surface first organic layer having an opening overlapping with the upper conductive layer at least partially on the upper conductive layer; and forming a first surface third conductive layer in the opening of the first surface first organic layer on the conductive layer, and forming the capacitor along the normal direction of the first surface of the substrate. When viewing the upper conductive layer of the capacitor, the upper conductive layer of the capacitor may at least partially overlap an edge of the first surface first conductive layer.

In the method for manufacturing a capacitor-embedded component according to one embodiment of the present disclosure, the method for manufacturing a capacitor-embedded component includes forming at least a first surface first organic layer having an opening overlapping with the first surface first inorganic layer of the capacitor. The step of partially forming the upper conductive layer on the first surface first inorganic layer may further include forming the upper conductive layer on the first surface first inorganic layer of the capacitor. The upper conductive layer may be formed in the opening of the organic layer.

According to embodiments of the present disclosure, the capacitance of the capacitor can be increased.

Next, the embodiments of the present disclosure will be described in more detail with reference to examples, but the embodiments of the present disclosure are not limited to the description of the following examples as long as they do not exceed the gist thereof.

(first measurement)
Samples 1 to 15 each having a capacitor 15 having a first surface first conductive layer 31, a first surface first inorganic layer 32, and a first surface second conductive layer 33 laminated in order from the substrate 12 side were produced. . As the first surface first conductive layer 31, one including a first layer 221 functioning as a seed layer and a copper second layer 222 formed on the first layer 221 by electroplating was used. As the first surface first inorganic layer 32, a layer of silicon nitride (SiN) formed by plasma CVD was used. Also, before forming the first surface first inorganic layer 32 on the first surface first conductive layer 31, the average surface roughness of the first surface first conductive layer 31 was measured. The average surface roughness was measured within a square area having a side length L1 of 150 µm, in accordance with JIS B 0601:2001. The average surface roughness of the first surface first conductive layer 31 reflects the roughness of the surface of the first layer 221 roughened when the unnecessary first layer 221 is removed by etching. FIG. 24 shows the measurement results of the thickness of the first surface first inorganic layer 32 and the average surface roughness of the first surface first conductive layer 31 of each sample.

Subsequently, the leakage current of the capacitor 15 of each sample was measured. The measurement results are also shown in FIG.

Also, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 was evaluated based on a cross-cut peeling test. The evaluation results are also shown in FIG.

As shown in FIG. 24, in samples 5, 10 and 15, the leakage current exceeded 1×10 ⁻⁸ A, and therefore the judgment was made “bad”. In Samples 5, 10 and 15, the average surface roughness of the first surface first conductive layer 31 exceeded 0.4 μm, which is considered to have caused the leakage current to increase.

As shown in FIG. 24, in samples 4, 9 and 14, the first surface first inorganic layer 32 was peeled off from the first surface first conductive layer 31, and therefore the judgment was made "bad". In samples 4, 9 and 14, the average surface roughness of the first surface first conductive layer 31 is less than 0.1 μm. It is considered that the adhesion of the film was low.

As shown in FIG. 24, in samples 1 to 3, 6 to 8 and 11 to 13, the leakage current is 1×10 ⁻⁸ A or less, and the leakage current from the first surface first conductive layer 31 is 1 No peeling of the inorganic layer 32 occurred. Therefore, the judgment was made "good". In samples 1 to 3, 6 to 8, and 11 to 13, the average surface roughness of the first conductive layer 31 on the first surface was 0.1 μm or more and 0.4 μm or less, so that adhesion was achieved while suppressing leakage current. It is thought that the quality could be improved.

(Second measurement)
The first surface of each sample was measured in the same manner as in the first measurement above, except that the average surface roughness was measured with an evaluation length of 2.5 μm in accordance with JIS R 1683: 2007. The average surface roughness of the first conductive layer 31 was measured. In addition, leakage current and adhesion of each sample were evaluated in the same manner as in the first measurement described above. The results are also shown in FIG.

As shown in FIG. 24, in samples 5, 10, and 15 in which the leakage current exceeded 1×10 ⁻⁸ A, the first surface first conductive layer 31 was calculated when the evaluation length was 2.5 μm. had an average surface roughness exceeding 0.24 μm. On the other hand, when the average surface roughness of the first conductive layer 31 on the first surface calculated when the evaluation length is 2.5 μm is 0.22 μm or less, the leakage current is 1×10 ⁻⁸ A or less. More specifically, it was 1×10 ⁻⁹ A or less.

As shown in FIG. 24, in samples 4, 9, and 14 in which peeling of the first surface first inorganic layer 32 from the first surface first conductive layer 31 occurred, when the evaluation length was set to 2.5 μm, The calculated average surface roughness of the first surface first conductive layer 31 was 0.70 μm or less. On the other hand, when the average surface roughness of the first surface first conductive layer 31 calculated when the evaluation length was 2.5 μm was 0.75 μm or more, the first surface first conductive layer 31 No peeling of the first inorganic layer 32 on the first surface occurred.

10 Capacitor built-in component 12 Substrate 13 First surface 14 Second surface 15 Capacitor 16 Inductor 20 Through hole 21 Side wall 22 Through electrode 221 First layer 222 Second layer 26 Organic layer 30 First wiring structure portion 31 First surface first conduction Layer 311 top surface 312 side surface 32 first surface first inorganic layer 33 first surface second conductive layer 34 first surface first organic layer 35 first surface third conductive layer 36 first surface second organic layer 37 resist layer 40 2 wiring structure part 41 second surface first conductive layer 43 second surface first organic layer 50 element 51 terminal 60 mounting substrate

Claims (19)

A component with a built-in capacitor,
a substrate including a first surface and a second surface opposite the first surface;
a first surface first conductive layer located on the first surface of the substrate;
a first surface first inorganic layer located on the first surface first conductive layer;
an upper conductive layer located on a portion of the first surface first inorganic layer;
The upper conductive layer, and the first surface first conductive layer and the first surface first inorganic layer overlapping the upper conductive layer in a plan view constitute a capacitor,
The capacitor built-in component includes a first surface first organic layer positioned on the first surface first inorganic layer positioned on the first surface first conductive layer that does not overlap the upper conductive layer in a plan view,
The average surface roughness of the upper surface of the first surface first conductive layer that does not overlap the upper conductive layer in plan view is 0.22 μm or less when the evaluation length is 2.5 μm,
A capacitor-embedded component, wherein the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor is 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm. 2. The capacitor-embedded component according to claim 1, wherein said first surface first organic layer includes polyimide. 3. The capacitor-embedded component according to claim 1 , wherein the upper surface of said first surface first conductive layer of said capacitor has an average surface roughness of 0.22 [mu]m or less when an evaluation length is 2.5 [mu]m. The side surface of the first conductive layer on the first surface of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm,
4. The capacitor-embedded component according to claim 1, wherein said first surface first inorganic layer at least partially covers said side surface of said first surface first conductive layer. 5. The capacitor-embedded component according to claim 1 , wherein said substrate contains glass. The substrate is provided with a through hole,
The capacitor-embedded component further comprises an inductor electrically connected to the capacitor,
The inductor is electrically connected to the first surface first conductive layer and the first surface first conductive layer, and is electrically connected to the through electrode located on the wall surface of the through hole and the through electrode. and a second surface first conductive layer located on the second surface of the substrate. The capacitor built-in component is
a first surface second conductive layer positioned on the first surface first inorganic layer;
said first surface first organic layer positioned at least partially on said first surface second conductive layer and having an opening formed therein overlapping said first surface second conductive layer;
a first surface third conductive layer at least partially located in the opening of the first surface first organic layer on the first surface second conductive layer;
the upper conductive layer of the capacitor is composed of the first surface second conductive layer,
When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the end portion of the first surface second conductive layer of the capacitor 7. The capacitor-embedded component according to claim 1, wherein the capacitor-embedded component is located inside the edge of the first conductive layer. The capacitor built-in component is
a first surface second conductive layer positioned on the first surface first inorganic layer;
said first surface first organic layer positioned at least partially on said first surface second conductive layer and having an opening formed therein overlapping said first surface second conductive layer;
a first surface third conductive layer at least partially located in the opening of the first surface first organic layer on the first surface second conductive layer;
the upper conductive layer of the capacitor is composed of the first surface second conductive layer,
When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the first surface second conductive layer of the capacitor is at least partially aligned with the first surface of the substrate. 7. The capacitor-embedded component according to any one of claims 1 to 6 , which overlaps with the edge of the first conductive layer on one side. The capacitor built-in component is
a first surface first organic layer having an opening formed at least partially on the first surface first inorganic layer and overlapping the first surface first inorganic layer;
a first surface third conductive layer located in the opening of the first surface first organic layer on the first surface first inorganic layer;
7. The capacitor-embedded component according to claim 1, wherein said upper conductive layer of said capacitor is composed of said first surface third conductive layer. a capacitor-embedded component according to any one of claims 1 to 9 ;
and an element mounted on the capacitor-embedded component. providing a substrate including a first side and a second side opposite the first side;
forming a first surface first conductive layer on the first surface of the substrate;
forming a first surface first inorganic layer on the first surface first conductive layer;
forming an upper conductive layer on a portion of the first surface first inorganic layer;
forming a first surface first organic layer on the first surface first inorganic layer positioned on the first surface first conductive layer that does not overlap the upper conductive layer in plan view;
The upper conductive layer, and the first surface first conductive layer and the first surface first inorganic layer overlapping the upper conductive layer in a plan view constitute a capacitor,
The step of forming the first surface first conductive layer includes:
forming a conductive first layer on the first surface of the substrate;
forming a resist layer partially on the first layer;
forming a conductive second layer by electroplating on the first layer not covered by the resist layer;
annealing the second layer;
removing the resist layer;
removing by etching a portion of the first layer that is exposed from the second layer;
The average surface roughness of the upper surface of the first surface first conductive layer that does not overlap the upper conductive layer in plan view is 0.22 μm or less when the evaluation length is 2.5 μm,
A method of manufacturing a capacitor-embedded component, wherein the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor is 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm. 12. The method of manufacturing a capacitor-embedded component according to claim 11 , wherein said first surface first organic layer includes polyimide. 13. The capacitor-embedded component according to claim 11 , wherein the upper surface of said first surface first conductive layer of said capacitor has an average surface roughness of 0.22 μm or less when an evaluation length is 2.5 μm. Production method. The side surface of the first conductive layer on the first surface of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm,
14. The method of manufacturing a capacitor-embedded component according to claim 11 , wherein said first surface first inorganic layer at least partially covers said side surface of said first surface first conductive layer. 15. The method of manufacturing a capacitor-embedded component according to claim 11 , wherein said substrate contains glass. The substrate is provided with a through hole,
a through electrode electrically connected to the first surface first conductive layer and the first surface first conductive layer and positioned on a wall surface of the through hole; a through electrode electrically connected to the through electrode; 16. The method of manufacturing a capacitor-embedded component according to claim 11 , wherein an inductor electrically connected to said capacitor is constituted by said second-surface first conductive layer located on said surface. The method for manufacturing the capacitor-embedded component includes:
forming the first surface first organic layer having an opening overlying the upper conductive layer at least partially on the upper conductive layer;
forming a first surface third conductive layer in the opening of the first surface first organic layer on the upper conductive layer;
When the upper conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the end of the upper conductive layer of the capacitor is positioned from the end of the first surface first conductive layer. 17. The method of manufacturing a capacitor-embedded component according to claim 11 , wherein the . The method for manufacturing the capacitor-embedded component includes:
forming the first surface first organic layer having an opening overlying the upper conductive layer at least partially on the upper conductive layer;
forming a first surface third conductive layer in the opening of the first surface first organic layer on the upper conductive layer;
When the upper conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the upper conductive layer of the capacitor extends at least partially from an edge of the first surface first conductive layer. 17. The method for manufacturing a capacitor-embedded component according to claim 11 , wherein the capacitor-embedded component overlaps with the part. The method for manufacturing the capacitor-embedded component includes:
forming at least partially on the first surface first inorganic layer the first surface first organic layer having an opening overlapping the first surface first inorganic layer of the capacitor;
12. The step of forming the upper conductive layer forms the upper conductive layer in the opening of the first surface first organic layer on the first surface first inorganic layer of the capacitor. 17. The method of manufacturing a capacitor-embedded component according to any one of 16 .

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