JP2018182283A - Built-in capacitor component, mounting board with built-in capacitor component, and manufacturing method of built-in capacitor component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a built-in capacitor component with a small size and a high capacity.SOLUTION: A built-in capacitor component 10 includes: a substrate 12 including a first surface 13 and a second surface 14 positioned on the side opposite to the first surface; and a capacitor 15 positioned on the first surface of the substrate. The capacitor includes: a first surface first conductive layer 31 positioned on the first surface of the substrate; a first surface first inorganic layer 32 positioned on the first surface first conductive layer; and an upper conductive layer (first surface second conductive layer) 33 positioned on the first surface first inorganic layer. When an evaluation length on an upper surface of the first surface first conductive layer of the capacitor is 150 μm, an average surface roughness is 0.1 μm or more and 0.4 μm or less.SELECTED DRAWING: Figure 1

Description

  Embodiments of the present disclosure relate to a capacitor built-in component including a capacitor. In addition, the present disclosure relates to a mounting substrate including a capacitor built-in component, and a method of manufacturing the capacitor built-in component.

  In recent years, as integrated circuits represented by semiconductor memories are highly integrated, miniaturization of passive components used around integrated circuits is also required. For example, Patent Document 1 proposes a thin film capacitor including a first conductive layer, a high dielectric constant thin film provided on the first conductive layer, and a second conductive layer provided on the high dielectric constant thin film. There is. In a thin film capacitor, by using a high dielectric constant thin film having a high dielectric constant as a dielectric, a small-sized, large-capacity capacitor can be realized.

Japanese Patent Laid-Open No. 6-89831

  Since the dielectric constant and dielectric loss of a dielectric are generally in a trade-off relationship, it is difficult to excessively increase the dielectric constant of the dielectric. In order to realize a small-sized, large-capacity capacitor, devices from different viewpoints are required.

  An embodiment of the present disclosure aims to provide a capacitor built-in component that can effectively solve such a problem.

  One embodiment of the present disclosure includes a substrate including a first surface and a second surface located opposite to the first surface, and a capacitor located on the first surface of the substrate, the capacitor being A first surface first conductive layer located on the first surface of the substrate, a first surface first inorganic layer located on the first surface first conductive layer, and a surface on the first surface first inorganic layer And the upper surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm. It is a capacitor built-in component.

  In the capacitor built-in component according to one embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor in the case of the evaluation length of 2.5 μm is 0.2.2 μm or less It may be.

  In the capacitor built-in component according to one embodiment of the present disclosure, the average surface roughness of the side surface of the first surface first conductive layer of the capacitor in the case where the evaluation length is 150 μm is 0.1 μm or more and 0.4 μm or less The first surface first inorganic layer may at least partially cover the side surface of the first surface first conductive layer.

  In the capacitor built-in component according to one embodiment of the present disclosure, the first surface first conductive layer of the capacitor has a thickness of 0.05 μm or more and 1.0 μm or less, and a conductive first layer; And a second layer located on the first layer and having conductivity and having a thickness of 5 μm or more and 20 μm or less.

  In the capacitor built-in component according to an embodiment of the present disclosure, the first layer may include titanium or chromium.

  In the capacitor built-in component according to an embodiment of the present disclosure, the second layer may include copper.

  In the capacitor built-in component according to an embodiment of the present disclosure, the substrate may include glass.

  In the capacitor built-in component according to one embodiment of the present disclosure, the substrate is provided with a through hole, and the capacitor built-in component further includes an inductor electrically connected to the capacitor; A first surface conductive layer, a through electrode including the first layer and the second layer electrically connected to the first surface first conductive layer and located on the wall surface of the through hole; A second surface first conductive layer electrically connected to an electrode and including the first layer and the second layer located on the second surface of the substrate may be included.

  In the capacitor built-in component according to an embodiment of the present disclosure, the capacitor built-in component includes a first surface second conductive layer located on the first surface first inorganic layer, and at least partially the first surface second conductive A first surface first organic layer which is located on a layer and in which an opening overlapping the first surface second conductive layer is formed, and the first surface first organic layer on the first surface second conductive layer A first surface third conductive layer positioned at least partially in the opening, the upper conductive layer of the capacitor being constituted by the first surface second conductive layer, and When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface, the end of the first surface second conductive layer of the capacitor is the first surface first conductive It may be located inside the end of the layer.

  A component with a built-in capacitor according to an embodiment of the present disclosure is a first surface second conductive layer located on the first surface first inorganic layer, and at least partially located on the first surface second conductive layer. A first surface first organic layer in which an opening overlapping the first surface second conductive layer is formed, and at least the opening of the first surface first organic layer on the first surface second conductive layer And a first surface third conductive layer partially positioned, wherein the upper conductive layer of the capacitor is constituted by the first surface second conductive layer, and the method of the first surface of the substrate is provided. When the first surface second conductive layer of the capacitor is viewed along the line direction, the first surface second conductive layer of the capacitor is at least partially an end portion of the first surface first conductive layer And may overlap.

  A capacitor-embedded component according to an embodiment of the present disclosure is a first surface at least partially located on the first surface first inorganic layer and having an opening overlapping the first surface first inorganic layer. And a first surface third conductive layer located in the opening of the first surface first organic layer on the first surface first inorganic layer, and the upper conductive layer of the capacitor May be comprised by said 1st surface 3rd conductive layer.

  One embodiment of the present disclosure is a mounting substrate including the capacitor built-in component described above and an element mounted on the capacitor built-in component.

  One embodiment of the present disclosure includes the steps of: providing a substrate including a first surface and a second surface located opposite the first surface; and having conductivity on the first surface of the substrate. A step of forming a layer, a step of partially forming a resist layer on the first layer, a second layer having conductivity by an electrolytic plating method on the first layer not covered by the resist layer A step of forming a layer, a step of removing the resist layer, a step of removing a portion of the first layer exposed from the second layer by etching, and a step of forming a first surface on the second layer Forming a first inorganic layer, and forming an upper conductive layer on the first surface first inorganic layer, and a first surface first conductive layer including the first layer and the second layer; The first surface first inorganic layer on the second layer of the first surface first conductive layer, and the first surface first non-conductive layer The upper conductive layer on the layer constitutes a capacitor, and the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor when the evaluation length is 150 μm is 0.1 μm or more and 0 It is a manufacturing method of a capacitor built-in part which is .4 μm or less.

  In the method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor in the case of the evaluation length of 2.5 μm is 0.22 μm or less It may be

  In the method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, an average surface roughness of the side surface of the first surface first conductive layer of the capacitor when the evaluation length is 150 μm is 0.1 μm or more and 0 The first surface first inorganic layer may at least partially cover the side surface of the first surface first conductive layer.

  In the method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, the thickness of the first layer is 0.05 μm or more and 1.0 μm or less, and the thickness of the second layer is 5 μm or more and 20 μm or less May be

  In the method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, the substrate may include glass.

  In the method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, the substrate is provided with a through hole, and the first layer and the second layer are formed on the wall surface of the through hole and the second layer of the substrate. The first surface, the first conductive layer, the through electrode including the first layer and the second layer on the wall surface of the through hole, and the first surface on the second surface. An inductor electrically connected to the capacitor may be configured by the layer and the second surface first conductive layer including the second layer.

  In a method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, a first surface first organic layer having an opening overlapping with the upper conductive layer is formed at least partially on the upper conductive layer; Forming a first surface third conductive layer in the opening of the first surface first organic layer on a conductive layer, and further including the step of forming the capacitor in a direction normal to the first surface of the substrate. When looking at the upper conductive layer, the end of the upper conductive layer of the capacitor may be located inside the end of the first surface first conductive layer.

  In a method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, a first surface first organic layer having an opening overlapping with the upper conductive layer is formed at least partially on the upper conductive layer; Forming a first surface third conductive layer in the opening of the first surface first organic layer on a conductive layer, and further including the step of forming the capacitor in a direction normal to the first surface of the substrate. The upper conductive layer of the capacitor may at least partially overlap the end of the first surface first conductive layer.

  In the method of manufacturing a capacitor built-in component according to an embodiment of the present disclosure, the method of manufacturing the capacitor built-in component includes at least a first surface first organic layer having an opening overlapping the first surface first inorganic layer of the capacitor. The method further comprises the step of partially forming the first surface on the first inorganic layer, wherein in the step of forming the upper conductive layer, the first surface on the first surface first inorganic layer of the capacitor is formed. The upper conductive layer may be formed in the opening of the organic layer.

  According to embodiments of the present disclosure, the capacitance of the capacitor can be increased.

It is sectional drawing which shows the capacitor built-in components which concern on one Embodiment. It is sectional drawing which expands and shows the penetration electrode of capacitor built-in components. It is a top view which shows the 1st surface 1st conductive layer of capacitor built-in components. It is a top view which shows the 1st surface 1st inorganic layer and 1st surface 2nd conductive layer of capacitor built-in components. It is a top view which expands and shows a capacitor. It is sectional drawing which expands and shows a capacitor. It is sectional drawing which shows one modification of a through-hole. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a figure which shows the manufacturing process of capacitor built-in components. It is a top view showing the capacitor concerning the 1st modification. It is sectional drawing which shows the capacitor which concerns on a 1st modification. It is a top view showing the capacitor concerning the 2nd modification. It is sectional drawing which shows the capacitor which concerns on a 2nd modification. It is sectional drawing which shows one modification of a through-hole. It is sectional drawing which expands and shows an example of the upper surface of a 1st surface 1st conductive layer. It is a sectional view showing an example of a mounting substrate provided with a capacitor built-in part and an element. It is a figure which shows the example of the product by which a capacitor built-in component is mounted. It is a figure which shows the result of having evaluated the leakage current in a capacitor, and the adhesiveness of a 1st surface 1st inorganic layer.

  Hereinafter, the configuration of a capacitor built-in component according to an embodiment of the present disclosure and a method of manufacturing the same will be described in detail with reference to the drawings. Note that the embodiments described below are examples of embodiments of the present disclosure, and the present disclosure is not construed as being limited to these embodiments. Moreover, in the present specification, terms such as “substrate”, “substrate”, “sheet” and “film” are not distinguished from one another based on only the difference in designation. For example, “substrate” or “substrate” is a concept including members such as sheets and films. Furthermore, as used herein, the terms such as "parallel" and "orthogonal", values of length and angle, etc., which specify the shape and geometrical conditions and their degree, are strictly bound. Instead, it shall be interpreted including the range to which the same function can be expected. In the drawings referred to in this embodiment, the same portions or portions having similar functions may be denoted by the same reference numerals or similar reference numerals, and repeated description thereof may be omitted. Further, the dimensional ratio of the drawings may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawings.

Capacitor-embedded Component Hereinafter, an embodiment of the present disclosure will be described. First, the configuration of capacitor built-in component 10 according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing a capacitor built-in component 10.

  The capacitor built-in component 10 includes a substrate 12, a capacitor 15 and an inductor 16. The capacitor 15 is configured by a part of the first wiring structure portion 30 provided on the first surface 13 side of the substrate 12. The inductor 16 is a part of the first wiring structure portion 30, the through electrode 22 provided in the through hole 20 of the substrate 12, and one of the second wiring structure portion 40 provided on the second surface 14 side of the substrate 12. It is composed of parts. Hereinafter, each component of capacitor built-in component 10 will be described.

(substrate)
The substrate 12 includes a first surface 13 and a second surface 14 opposite to the first surface 13. Further, the substrate 12 is provided with a plurality of through holes 20 extending from the first surface 13 to the second surface 14.

The substrate 12 contains an inorganic material having a certain insulating property. For example, the substrate 12 may be a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, a silicon substrate, a silicon carbide substrate, an alumina (Al ₂ O ₃ ) substrate, an aluminum nitride (AlN) substrate, a zirconia (ZrO ₂ ) substrate, etc. Or, these substrates are laminated. The substrate 12 may partially include a substrate made of a conductive material such as an aluminum substrate or a stainless steel substrate.

  Examples of the glass used for the substrate 12 include non-alkali glass and the like. Non-alkali glass is glass which does not contain an alkali component such as sodium or potassium. The alkali-free glass contains, for example, boric acid in place of the alkali component. Further, the non-alkali glass contains, for example, an alkaline earth metal oxide such as calcium oxide or barium oxide. As an example of non-alkali glass, EN-A1 made from Asahi Glass, Eagle XG made from Corning, etc. can be mentioned. When the substrate 12 includes glass, the thickness T of the substrate 12 is, for example, 0.25 mm or more and 0.45 mm or less. When the substrate 12 contains glass, the insulation of the substrate 12 can be enhanced as compared to the case where the substrate 12 is made of silicon, thereby improving the withstand voltage characteristics of the capacitor 15 located on the substrate 12. Can.

  In FIG. 1, reference symbol S1 represents the width of the through hole 20 at a position where the through hole 20 is connected to the first surface 13. The width S1 is, for example, 40 μm or more and 150 μm or less. The ratio of the length of the through hole 20 to the width S1 of the through hole 20, that is, the aspect ratio of the through hole 20 is, for example, 4 or more and 10 or less.

  The through holes 20 formed in the substrate 12 may have a shape in which the width decreases at least partially from the first surface 13 to the second surface 14 of the substrate 12. In the example shown in FIG. 1, the through hole 20 has a shape in which the width decreases from the first surface 13 and the second surface 14 of the substrate 12 toward the central portion in the thickness direction of the substrate 12. As a result, the width of the through hole 20 is minimized at the central portion in the thickness direction of the substrate 12 as indicated by the symbol S2 in FIG. The “central portion” means an intermediate position in the thickness direction of the substrate 12 and a range from the intermediate position to the first surface 13 side to 0.1 × T, and from the intermediate position to the second surface 14 side. It includes the range up to × T. The symbol T represents the thickness of the substrate 12 as described above.

(Through electrode)
FIG. 2 is a cross-sectional view showing the through electrode 22 provided in the through hole 20 in an enlarged manner. The through electrode 22 is a member located at least partially inside the through hole 20 and having conductivity. In the present embodiment, the thickness of the through electrode 22 is smaller than the width of the through hole 20. Therefore, there is a space in the through hole 20 in which the through electrode 22 does not exist. That is, the through electrode 22 is a so-called conformal via. The thickness of the through electrode 22 is, for example, 5 μm or more and 22 μm or less.

  The method for forming the through electrode 22 is not particularly limited as long as the through electrode 22 has conductivity. For example, the through electrode 22 may be formed by a physical film forming method such as a vapor deposition method or a sputtering method, or may be formed by a chemical film forming method or a plating method. Also, the through electrode 22 may be composed of a single layer having conductivity, or may include a plurality of layers having conductivity. Here, as shown in FIG. 2, an example in which the through electrode 22 includes the first layer 221 and the second layer 222 will be described.

  The first layer 221 is a layer located at least partially on the side wall 21 of the through hole 20 and having conductivity. The first layer 221 is formed on the side wall 21 by a physical film forming method such as a sputtering method or a vapor deposition method, a sol-gel method, or the like. Preferably, the first layer 221 is formed on the side wall 21 by sputtering. Thereby, the first layer 221 can be firmly adhered to the side wall 21. The thickness of the first layer 221 is, for example, 0.05 μm or more and 1.0 μm or less. Another layer may be provided between the first layer 221 and the side wall 21 of the through hole 20.

  When the first layer 221 is formed by a physical film formation method, the material constituting the first layer 221 may be a metal such as titanium, chromium, nickel, copper, an alloy using these, or a laminate of these. It can be used. In addition, when the first layer 221 is formed by a sol-gel method, zinc oxide or the like can be used as a material forming the first layer 221. In addition to the sol-gel layer formed by the sol-gel method, the first layer 221 may further have an electroless plating layer containing a metal such as copper formed on the sol-gel layer by the electroless plating method. .

  The second layer 222 is a layer located on the first layer 221 and having conductivity. The second layer 222 contains, for example, copper as a main component, and more specifically, contains 80% by mass or more of copper. The second layer 222 may also contain a metal such as gold, silver, platinum, rhodium, tin, aluminum, nickel, chromium or an alloy using these. The second layer 222 is formed on the first layer 221 by electrolytic plating. As a method of analyzing the composition of the second layer 222, for example, a TEM (transmission electron microscope) or an EDS (energy dispersive X-ray spectrometer) can be employed. The thickness of the second layer 222 is, for example, 5 μm or more and 20 μm or less. Note that another conductive layer may be provided between the first layer 221 and the second layer 222.

(First wiring structure part)
Next, the first wiring structure unit 30 will be described. The first wiring structure portion 30 has a layer such as a conductive layer or an insulating layer provided on the first surface 13 side so as to constitute an electrical circuit on the first surface 13 side of the substrate 12. As described later, the capacitor 15 is configured by a part of the first wiring structure portion 30. Further, a part of the inductor 16 is configured by a part of the first wiring structure portion 30. In the present embodiment, the first wiring structure portion 30 includes the first surface first conductive layer 31, the first surface first inorganic layer 32, the first surface second conductive layer 33, the first surface first organic layer 34, The first surface third conductive layer 35 and the first surface second organic layer 36 are provided.

[First surface first conductive layer]
The first surface first conductive layer 31 is a conductive layer located on the first surface 13 of the substrate 12. The first surface first conductive layer 31 may be electrically connected to the through electrode 22. The first surface first conductive layer 31 may be composed of a single layer having conductivity, or may include a plurality of layers having conductivity. For example, the first surface first conductive layer 31 may include the first layer 221 and the second layer 222 sequentially stacked on the first surface 13 of the substrate 12 in the same manner as the through electrode 22. In addition, the first surface first conductive layer 31 may include only a portion of the conductive layer of the first layer 221 and the second layer 222. The material forming the first surface first conductive layer 31 is the same as the material forming the through electrode 22. The thickness of the first surface first conductive layer 31 may be, for example, 100 nm or more and 20 μm or less, and may be 5 μm or more and 20 μm or less.

  FIG. 3 is a plan view showing the case where the through electrode 22 and the first surface first conductive layer 31 of the capacitor built-in component 10 are viewed from the first surface 13 side. The first surface first conductive layer 31 is provided on the first surface 13 side of the substrate 12 so as to constitute the capacitor 15 and a part of the inductor 16 and the like. In FIG. 3, layers such as the first surface first inorganic layer 32 stacked on the first surface first conductive layer 31 are omitted. Moreover, FIG. 1 is corresponded to sectional drawing at the time of cut | disconnecting the capacitor built-in components 10 shown in FIG. 3 or FIG. 4 mentioned later along line AA.

[First surface first inorganic layer]
The first surface first inorganic layer 32 is a layer which is located at least partially on the first surface first conductive layer 31 and the first surface 13 of the substrate 12, contains an inorganic material, and has an insulating property. The inorganic material of the first surface first inorganic layer 32 preferably has a breakdown electric field of 6 MV / cm or more, more preferably 8 MV / cm or more. As an inorganic material of the first surface first inorganic layer 32, silicon nitride such as SiN can be used. Other examples of the inorganic material of the first surface first inorganic layer 32 include silicon oxide, aluminum oxide, tantalum pentoxide and the like. The relative dielectric constant of the inorganic material of the first surface first inorganic layer 32 is, for example, 3 or more and 50 or less. The thickness of the first surface first inorganic layer 32 is, for example, 50 nm or more and 400 nm or less. The first surface first inorganic layer 32 may be composed of a single layer or may include a plurality of layers.

Preferably, the leakage current in the inorganic material of the first surface first inorganic layer 32 is 1 × 10 ⁻⁸ A or less, more preferably 1 × 10 ⁻⁹ A or less, still more preferably 1 × 10 ^−10. It is A or less, and particularly preferably 1 × 10 ⁻¹¹ A or less. Thereby, the electrical characteristics of the capacitor 15 including the first surface first inorganic layer 32 can be further improved.

  The first surface first inorganic layer 32 may at least partially cover the end 31 e and the side surface 312 of the first surface first conductive layer 31. In other words, the first surface first inorganic layer 32 may be located not only on the upper surface 311 of the first surface first conductive layer 31 but also on the side surface 312. Thus, damage to the first surface first conductive layer 31 due to the chemical solution used in the step of forming the first surface second conductive layer 33, the first surface first organic layer 34, and the like can be suppressed. In addition, as shown in FIG. 1, when the capacitor built-in component 10 is seen along the normal line direction of the 1st surface 13 of the board | substrate "end", the edge part 31e of the 1st surface 1st conductive layer 31 is seen. And the first surface first inorganic layer 32 overlap. Further, “upper surface” means a surface of the layers stacked on the substrate 12 that is located on the side far from the substrate 12. Further, the “lower surface” means a surface of the layers stacked on the substrate 12 that is located closer to the substrate 12. Also, "side surface" means a surface that extends from the lower surface to the upper surface.

[First surface second conductive layer]
The first surface second conductive layer 33 is a conductive layer located on the first surface first inorganic layer 32. As shown in FIG. 1, the end 33 e of the first surface second conductive layer 33 is located on the first surface first inorganic layer 32. The first surface first conductive layer 31 described above, the above described first surface first inorganic layer 32 located on the first surface first conductive layer 31, and the first surface located on the first surface first inorganic layer 32 The surface second conductive layer 33 and the capacitor 15 are configured. Thus, in the present embodiment, the dielectric of the capacitor 15 is constituted by the first surface first inorganic layer 32, and the lower conductive layer facing the dielectric from the substrate 12 side is the first surface first conductive layer. A first surface second conductive layer 33 is formed of the first surface second conductive layer 33, which is formed of the first surface second conductive layer 31 and is opposed to the dielectric 12 from the side opposite to the substrate 12.

  The first surface second conductive layer 33 is, like the through electrode 22 and the first surface first conductive layer 31, the first layer 221, the second layer 222, and the like sequentially stacked on the first surface first inorganic layer 32. And multiple conductive layers may be included. The material forming the first surface second conductive layer 33 is the same as the material forming the through electrode 22 or the first surface first conductive layer 31. The thickness of the first surface second conductive layer 33 is, for example, 100 nm or more and 20 μm or less.

  FIG. 4 is a plan view showing a case where the first surface first conductive layer 31, the first surface first inorganic layer 32, and the first surface second conductive layer 33 of the capacitor built-in component 10 are viewed from the first surface 13 side. is there. In FIG. 4, layers such as a first surface first organic layer 34 and a first surface third conductive layer 35 described later stacked on the first surface second conductive layer 33 are omitted. Moreover, in FIG. 4, the component covered by the 1st surface 1st inorganic layer 32 is represented by the dotted line.

  As shown in FIG. 4, the first surface first inorganic layer 32 may cover the first surface 13 of the substrate 12 and the first surface first conductive layer 31 over a wide area. For example, the first surface first inorganic layer 32 may cover at least an end 31 e of the first surface first conductive layer 31 constituting the capacitor 15.

  As shown in FIG. 5, an opening 32 a is formed in the first surface first inorganic layer 32. The opening 32 a is formed at the position of the through hole 20 and the connection position of the first surface first conductive layer 31 and the first surface third conductive layer 35.

[First surface first organic layer]
The first surface first organic layer 34 is a layer located on the first surface first inorganic layer 32 and the first surface second conductive layer 33, containing an organic material, and having an insulating property. As an organic material of the first surface first organic layer 34, polyimide, epoxy or the like can be used. The organic material of the first surface first organic layer 34 preferably has a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and still more preferably 0.001 or less. By forming the first surface first organic layer 34 using an organic material having a small dielectric loss tangent, it is possible to suppress an electric signal to be transmitted through the capacitor 15 and the inductor 16 from passing through the first surface first organic layer 34 be able to. Thus, the band of the capacitor built-in component 10 including the capacitor 15 and the inductor 16 can be expanded to the high frequency side.

  As shown in FIG. 1, in the first surface first organic layer 34 located on the first surface second conductive layer 33 of the capacitor 15, an opening 34a overlapping the first surface second conductive layer 33 is formed. There is.

[First surface third conductive layer]
The first surface third conductive layer 35 is a conductive layer located on the first surface first conductive layer 31 or the first surface second conductive layer 33. In the example shown in FIG. 1, the first surface third conductive layer 35 is electrically connected to the first surface first conductive layer 31 constituting the lower conductive layer of the capacitor 15. It includes a portion located in the opening 34 a of the layer 34. In addition, the first surface third conductive layer 35 is electrically connected to the first surface second conductive layer 33 forming the upper conductive layer of the capacitor 15 and the opening 34 a of the first surface first organic layer 34. Including the part located at

  Similarly to the through electrode 22 and the first surface first conductive layer 31, the first surface third conductive layer 35 may include a plurality of conductive layers such as the first layer 221 and the second layer 222 sequentially stacked. Good. The material forming the first surface third conductive layer 35 is the same as the material forming the through electrode 22 or the first surface first conductive layer 31.

[First surface second organic layer]
The first surface second organic layer 36 is a layer located on the first surface first organic layer 34 and the first surface third conductive layer 35, containing an organic material and having an insulating property. The first surface second organic layer 36 is, similarly to the first surface first organic layer 34, an organic having a dielectric loss tangent of preferably 0.003 or less, more preferably 0.002 or less, and still more preferably 0.001 or less. Contains the material. As the organic material of the first surface second organic layer 36, polyimide, epoxy or the like can be used as in the case of the first surface first organic layer 34.

(2nd wiring structure part)
Next, the second wiring structure unit 40 will be described. The second wiring structure portion 40 has a layer such as a conductive layer or an insulating layer provided on the second surface 14 side so as to constitute an electrical circuit on the second surface 14 side of the substrate 12. An inductor 16 is configured by a part of the second wiring structure part 40, a part of the above-described first wiring structure part 30, and the through electrode 22. In the present embodiment, the second wiring structure portion 40 includes the second surface first conductive layer 41 and the second surface first organic layer 43.

[Second surface first conductive layer]
The second surface first conductive layer 41 is a layer located on the second surface 14 of the substrate 12 and having conductivity. The second surface first conductive layer 41 may be electrically connected to the through electrode 22.

  The second surface first conductive layer 41 is, like the through electrode 22 and the first surface first conductive layer 31, such as the first layer 221 and the second layer 222 sequentially stacked on the second surface 14 of the substrate 12. A plurality of conductive layers may be included. The material forming the second surface first conductive layer 41 is the same as the material forming the through electrode 22. The thickness of the second surface first conductive layer 41 is, for example, 100 nm or more and 20 μm or less.

[Second surface first organic layer]
The second surface first organic layer 43 is a layer located on the second surface first conductive layer 41 and the second surface 14 of the substrate 12 and containing an organic material and having an insulating property. Similarly to the first surface first organic layer 34 and the first surface second organic layer 36, the second surface first organic layer 43 is preferably 0.003 or less, more preferably 0.002 or less, still more preferably 0. It includes an organic material having a dielectric loss tangent of .001 or less. As the organic material of the second surface first organic layer 43, polyimide, epoxy or the like can be used as in the case of the first surface first organic layer 34 and the first surface second organic layer 36.

(Capacitor)
Next, the capacitor 15 will be described in detail with reference to FIGS. 5 and 6. FIG. 5 is a plan view showing the capacitor 15 in an enlarged manner. 6 is a cross-sectional view of the capacitor 15 taken along the line B-B in FIG. In addition, in FIG.5 and FIG.6, the above-mentioned 1st surface 1st organic layer 34, the 1st surface 3rd conductive layer 35, and the 1st surface 2nd organic layer 36 are abbreviate | omitted.

  As shown in FIG. 6, the upper surface 311 of the first surface first conductive layer 31 of the capacitor 15 may have an uneven shape. Thus, the area of the upper surface 311 opposite to the first surface second conductive layer 33 can be increased and the capacitance of the capacitor 15 can be increased, as compared with the case where the upper surface 311 is flat. Further, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced. The average surface roughness of the upper surface 311 of the first surface first conductive layer 31 is, for example, 0.1 μm or more and 0.4 μm or less. The average surface roughness is, for example, an arithmetic average surface roughness defined in JIS B 0601: 2001. The average surface roughness is measured in a square area having a side length L1 as shown in FIGS. 5 and 6. The length L1 is, for example, 150 μm.

  As shown in FIG. 6, the side surface 312 of the first surface first conductive layer 31 of the capacitor 15 may have an uneven shape as well as the upper surface 311. The side surface 312 of the first surface first conductive layer 31 is an end of the first surface first conductive layer 31 when the first surface first conductive layer 31 is viewed along the normal direction of the first surface 13 of the substrate 12 It is a part which defines the part 31e. When the side surface 312 has an uneven shape, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced by, for example, an anchor effect. Because the displacement of the first surface first inorganic layer 32 in contact with the side surface 312 in the normal direction of the first surface 13 of the substrate 12, the uneven shape of the side surface 312 locks the first surface first inorganic layer 32. It is because it can suppress by doing. The average surface roughness of the side surface 312 of the first surface first conductive layer 31 is equal to the average surface roughness of the side surface 312, and is, for example, 0.1 μm or more and 0.4 μm or less.

  In the step of removing unnecessary portions of the first layer 221 of the first surface first conductive layer 31 by etching, as described above, the above-described concavo-convex shape on the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 The upper surface 311 and the side surface 312 are generated by being exposed to the etching solution and scraped off.

  As shown in FIG. 5, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the end of the first surface second conductive layer 33 of the capacitor 15 The portion 33 e is located inside the end 31 e of the first surface first conductive layer 31. For example, as shown in FIG. 5, when the first surface second conductive layer 33 of the capacitor 15 has a substantially rectangular shape including four corner portions 31f, all the end portions 33e constituting the four sides are The first surface first conductive layer 31 is located inside the end 31 e of the first conductive layer 31. In other words, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the first surface second conductive layer 33 is the first surface first conductive layer 31. Do not overlap with the side surface 312 of the Hereinafter, advantages of configuring the first surface second conductive layer 33 in this manner will be described. "Inside" means the center side of the capacitor 15 in a plan view.

  In the step of forming the first surface first inorganic layer 32, the first surface first inorganic layer 32 is less likely to be formed on the side surface 312 of the first surface first conductive layer 31 than the upper surface 311. Therefore, the thickness of the first surface first inorganic layer 32 on the side surface 312 is smaller than the thickness of the first surface first inorganic layer 32 on the upper surface 311. In addition, it is conceivable that the first surface first inorganic layer 32 is not formed on a part of the side surface 312, and thus the first surface first conductive layer 31 is exposed. Therefore, when the first surface second conductive layer 33 extends to a position overlapping the side surface 312 of the first surface first conductive layer 31, in other words, the first surface second conductive layer 33 is formed on the first surface on the side surface 312. When the surface first inorganic layer 32 is covered, the risk of the first surface second conductive layer 33 coming into contact with the exposed first surface first conductive layer 31 becomes high.

  On the other hand, in the present embodiment, the end 33 e of the first surface second conductive layer 33 of the capacitor 15 is located inside the end 31 e of the first surface first conductive layer 31. Therefore, the risk that the first surface second conductive layer 33 contacts the side surface 312 of the first surface first conductive layer 31 to cause an electrical short can be reduced.

(Modified example of through hole)
FIG. 7 is a cross-sectional view showing a modification of the through hole 20. As shown in FIG. As shown in FIG. 7, the capacitor built-in component 10 may include the organic layer 26 positioned closer to the center of the through hole 20 than the through electrode 22. The “center side” means that the distance between the organic layer 26 and the side wall 21 is larger than the distance between the through electrode 22 and the side wall 21 in the through hole 20. The organic layer 26 preferably includes an organic material having a dielectric loss tangent of 0.003 or less, more preferably 0.002 or less, and still more preferably 0.001 or less. As the organic material of the organic layer 26, polyimide, epoxy or the like can be used. By forming the organic layer 26 using an organic material with a small dielectric loss tangent, it is possible to suppress that part of the electric signal to be transmitted through the capacitor 15 and the inductor 16 passes through the organic layer 26. Thus, the band of the capacitor built-in component 10 including the capacitor 15 and the inductor 16 can be expanded to the high frequency side.

  Further, although not shown, the through electrode 22 may be a filled via filled in the through hole 20. In this case, the through electrode 22 extends at least partially to the center point of the through hole 20 in the surface direction of the first surface 13.

Method of Manufacturing Capacitor Built-In Part Hereinafter, an example of a method of manufacturing the capacitor built-in part 10 will be described with reference to FIGS. 8 to 15.

(Through-hole forming process)
First, the substrate 12 is prepared. Next, a resist layer is provided on at least one of the first surface 13 and the second surface 14. Thereafter, an opening is provided at a position corresponding to the through hole 20 in the resist layer. Next, by processing the substrate 12 at the opening of the resist layer, as shown in FIG. 8, the through holes 20 can be formed in the substrate 12. As a method of processing the substrate 12, a dry etching method such as a reactive ion etching method or a deep reactive ion etching method, a wet etching method, or the like can be used.

  The through holes 20 may be formed in the substrate 12 by irradiating the substrate 12 with a laser. In this case, the resist layer may not be provided. As a laser for laser processing, an excimer laser, an Nd: YAG laser, a femtosecond laser or the like can be used. When an Nd: YAG laser is employed, a fundamental wave having a wavelength of 1064 nm, a second harmonic having a wavelength of 532 nm, a third harmonic having a wavelength of 355 nm, or the like can be used.

  Moreover, laser irradiation and wet etching can also be combined suitably. Specifically, first, an altered layer is formed in a region of the substrate 12 where the through hole 20 is to be formed by laser irradiation. Subsequently, the substrate 12 is immersed in hydrogen fluoride or the like to etch the altered layer. Thus, the through holes 20 can be formed in the substrate 12. In addition, the through holes 20 may be formed in the substrate 12 by a blast process in which an abrasive is sprayed on the substrate 12.

  By processing the substrate 12 from both the first surface 13 side and the second surface 14 side, a through hole 20 having a shape whose width decreases toward the central portion in the thickness direction of the substrate 12 shown in FIG. 8 is formed can do.

(Through electrode formation process)
Next, the through electrode 22 is formed on the side wall 21 of the through hole 20. In the present embodiment, the first surface first conductive layer 31 is formed on a portion of the first surface 13 of the substrate 12 simultaneously with the through electrode 22, and the second surface is formed on a portion of the second surface 14 of the substrate 12. An example of forming the first conductive layer 41 will be described.

  First, as shown in FIG. 9, the first layer 221 is formed on the first surface 13, the second surface 14 and the side wall 21 of the substrate 12 by physical film forming method, sol-gel method, electroless plating method or the like. The first layer 221 is preferably formed by physical deposition, particularly preferably by sputtering. As a result, the first layer 221 can be firmly adhered to the first surface 13, the second surface 14 and the side wall 21 of the substrate 12. The physical film forming method such as the sputtering method or the vapor deposition method is preferably performed from both the first surface 13 side and the second surface 14 side. In this case, the conductive substance flying from the first surface 13 side and the conductive substance flying from the second surface 14 adhere to the side wall 21 of the through hole 20.

  Subsequently, as shown in FIG. 10, a resist layer 37 is partially formed on the first layer 221. As a material of the resist layer 37, a photosensitive material such as a dry film resist containing an acrylic resin may be used.

  Subsequently, as shown in FIG. 11, the second layer 222 is formed on the first layer 221 not covered by the resist layer 37 by electrolytic plating. For example, the substrate 12 is immersed in an electrolytic plating solution containing copper. In addition, current flows in the first layer 221. Thereby, the second layer 222 can be deposited on the first layer 221.

(Resist and conductive layer removal process)
Thereafter, as shown in FIG. 12, the resist layer 37 is removed. Subsequently, as shown in FIG. 13, a portion of the first layer 221 covered by the resist layer 37, in other words, a portion of the first layer 221 exposed from the second layer 222 may be wet etched, for example. Remove by Thus, the through electrode 22 including the first layer 221 and the second layer 222, the first surface first conductive layer 31 and the second surface first conductive layer 41 can be formed. Thus, the second surface first conductive layer 41, the through electrode 22 electrically connected to the second surface first conductive layer 41, and the first surface first conductive layer electrically connected to the through electrode 22. 31 can be configured. Note that a step of annealing a conductive layer such as the second layer 222 may be performed.

  By the way, in the step of removing the portion of the first layer 221 covered by the resist layer 37 by wet etching, the second layer 222 is also exposed to the etching solution, so the surface of the second layer 222 is also partially scraped. Be As a result, as described above, the uneven shape is formed on the upper surface 311 and the side surface 312 of the first surface first conductive layer 31, and the average surface roughness of the upper surface 311 and the side surface 312 is increased.

  The longer the second layer 222 is exposed to the etchant, the larger the average surface roughness of the top surface 311 and the side surface 312. By the way, in the present embodiment, the first surface first conductive layer 31 is formed integrally with the through electrode 22 which constitutes a part of the inductor 16. In order to improve the electrical characteristics such as high frequency characteristics of the inductor 16, it is preferable to increase the thickness of the first layer 221 and the second layer 222 constituting the inductor 16 to reduce the electrical resistance of the inductor 16. As the thickness of the first layer 221 increases, the time required to remove the first layer 221 by etching increases, and the time during which the second layer 222 is exposed to the etching solution also increases. As a result, the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 also increases. By increasing the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 to a certain extent, the area of the upper surface 311 facing the first surface second conductive layer 33 is increased, and the capacitance of the capacitor 15 is increased. Can be increased.

  When the first layer 221 contains chromium and the second layer 222 contains copper, for example, an aqueous solution of potassium permanganate can be used as an etchant for removing the first layer 221. Further, in the case where the first layer 221 contains titanium and the second layer 222 contains copper, for example, Ti3991 made of titanium etching solution Meltex can be used as an etching solution.

  When the average surface roughness of the upper surface 311 of the first surface first conductive layer 31 is too large, the variation in the thickness of the first surface first inorganic layer 32 formed on the upper surface 311 becomes large, and as a result, There is a possibility that a portion in which the first surface first conductive layer 31 is exposed from the first surface first inorganic layer 32 may occur. In addition, in consideration of this point that the leakage current of the capacitor 15 including the first surface first inorganic layer 32 may increase, the average of the upper surface 311 of the first surface first conductive layer 31 is taken as described above. The surface roughness is preferably 0.4 μm or less.

(Step of forming first surface first inorganic layer and first surface second conductive layer)
Next, as shown in FIG. 14, the first surface first inorganic layer 32 is formed on the second layer 222 of the first surface first conductive layer 31 and the first surface 13 of the substrate 12. As a method of forming the first surface first inorganic layer 32, for example, plasma CVD, sputtering, atomic layer deposition, or the like can be employed. Further, as shown in FIG. 14, the first surface second conductive layer 33 is formed on a portion of the first surface first inorganic layer 32. Thus, the first surface first conductive layer 31, the first surface first inorganic layer 32 on the first surface first conductive layer 31, and the first surface second conductive layer on the first surface first inorganic layer 32. 33 can be configured. The step of forming the first surface second conductive layer 33 is the same as the step of forming the first surface first conductive layer 31, and thus the description thereof is omitted.

  In addition, the timing which patterns the 1st surface 1st inorganic layer 32 so that the 1st surface 1st inorganic layer 32 may become a shape shown in FIG. 14 is arbitrary. For example, the first surface first inorganic layer 32 may be patterned before the first surface second conductive layer 33 is formed on the first surface first inorganic layer 32, and the first surface second conductive layer 33 is formed. After that, the first surface first inorganic layer 32 may be patterned. Although not shown, after the first surface first organic layer 34 shown in FIG. 14 described later is formed on the first surface second conductive layer 33, the first surface first organic layer 34 is used as a mask for the first surface. The first inorganic layer 32 may be patterned.

(Step of Forming First Surface First Organic Layer)
Next, as shown in FIG. 15, the first surface first organic layer 34 is formed on a portion of the first surface second conductive layer 33 and a portion of the first surface first inorganic layer 32. For example, first, a first surface side film (not shown) having a photosensitive layer containing an organic material and a base is attached to the first surface 13 side of the substrate 12. Subsequently, the first surface film is subjected to exposure processing and development processing. As a result, the first surface first organic layer 34 formed of the photosensitive layer of the first surface side film and having the opening 34a overlapping the first surface second conductive layer 33 or the first surface first conductive layer 31 is obtained. It can be formed on the first surface 13 side of the substrate 12. At this time, as in the case of the first surface first organic layer 34, as shown in FIG. 15, the second surface 14 of the substrate 12 and the second surface of the second conductive layer 41 are secondly formed. The surface first organic layer 43 may be formed.

  The opening 34a of the first surface first organic layer 34 is a position where the first surface third conductive layer 35 and the first surface first conductive layer 31 are connected, the first surface third conductive layer 35 and the first surface It is formed at a position where the second conductive layer 33 is connected and the like.

  In addition, the formation method of the 1st surface 1st organic layer 34 and the 2nd surface 1st organic layer 43 is not restricted to the method of using a film. For example, first, a liquid containing an organic material such as polyimide is applied by spin coating or the like and dried to form an organic layer. Subsequently, the first surface first organic layer 34 and the second surface first organic layer 43 can be formed by subjecting the organic layer to exposure processing and development processing.

  Further, as shown in FIG. 15, by causing part of the first surface first organic layer 34 and part of the second surface first organic layer 43 to reach the inside of the through hole 20, as shown in FIG. The organic layer 26 may be formed on The organic layer 26 may be formed inside the through hole 20 in a process separate from the first surface first organic layer 34 and the second surface first organic layer 43.

  Thereafter, although not shown, the first surface third conductive layer 35 is formed on the first surface first organic layer 34. The first surface third conductive layer 35 is also formed in the opening 34a of the first surface first organic layer 34, whereby the first surface third conductive layer 35 can be formed on the first surface first via the opening 34a. It can be connected to the conductive layer 31 or the first surface second conductive layer 33. The first surface second organic layer 36 is formed on a portion of the first surface first organic layer 34 and a portion of the first surface third conductive layer 35. Thus, the capacitor built-in component 10 shown in FIG. 1 can be obtained.

  Hereinafter, the operation brought about by the present embodiment will be described.

  In the present embodiment, the upper surface 311 of the first surface first conductive layer 31 of the capacitor 15 has an uneven shape. Thus, the area of the upper surface 311 opposite to the first surface second conductive layer 33 can be increased and the capacitance of the capacitor 15 can be increased, as compared with the case where the upper surface 311 is flat. By this, it is possible to provide a capacitor built-in component 10 including the small-sized, large-capacity capacitor 15. Further, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 of the capacitor 15 can be enhanced. Thereby, it is possible to suppress peeling of the first surface first inorganic layer 32 from the first surface first conductive layer 31, and to improve the reliability of the capacitor 15.

  Further, the side surface 312 of the first surface first conductive layer 31 of the capacitor 15 also has a concavo-convex shape like the upper surface 311. For this reason, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced by the anchor effect. Thereby, the reliability of the capacitor 15 can be further enhanced.

  Note that various modifications can be made to the embodiment described above. Hereinafter, modifications will be described with reference to the drawings as needed. In the following description and the drawings used in the following description, for the parts that can be configured in the same manner as the above-described embodiment, the same reference numerals used for the corresponding parts in the above-described embodiment will be used. Duplicate descriptions will be omitted. In addition, in the case where it is clear that the operational effects obtained in the above-described embodiment can be obtained also in the modified example, the description may be omitted.

(First Modification of Capacitor)
In the embodiment described above, as shown in FIG. 5, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the first An example is shown in which the end 33 e of the surface second conductive layer 33 is located inside the end 31 e of the first surface first conductive layer 31. However, the positional relationship between the first surface first conductive layer 31 and the first surface second conductive layer 33 is not limited to the example shown in FIG.

  FIG. 16 is a plan view showing the capacitor 15 of the capacitor built-in part 10 according to the present modification. FIG. 17 is a cross-sectional view of the capacitor 15 taken along the line C-C in FIG. In FIG. 16 and FIG. 17, the first surface first organic layer 34, the first surface third conductive layer 35, and the first surface second organic layer 36 are omitted.

  In this modification, as shown in FIG. 16, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the first surface second conductive layer Reference numeral 33 at least partially overlaps the end 31 e of the first surface first conductive layer 31. In other words, when the first surface second conductive layer 33 of the capacitor 15 is viewed along the normal direction of the first surface 13 of the substrate 12, the first surface second conductive layer 33 is the first surface first conductive layer 31. And the side surface 312 of the Hereinafter, advantages of configuring the first surface second conductive layer 33 in this manner will be described.

  As a method of forming the first surface second conductive layer 33 on a part of the first surface first inorganic layer 32, the following method may be used. First, the first surface second conductive layer 33 is provided on the first surface first inorganic layer 32 over a wide area, and then a resist layer is provided on the first surface second conductive layer 33. Thereafter, the resist layer is patterned by photolithography to leave a resist layer partially on the first surface second conductive layer 33. Subsequently, the portion of the first surface second conductive layer 33 which is not covered by the resist layer is removed by etching.

  By the way, the resolution of the photolithography method is limited. For this reason, even if it is going to form a rectangular-shaped resist layer, it is difficult to obtain a resist layer having a shape with sharp corners. As a result, as shown in FIG. 16, the corner 33f of the first surface second conductive layer 33 having a shape corresponding to the resist layer also has a curved shape. The degree of curvature at the corner 33f varies depending on the etching time and the like. Therefore, when the corner 33 f of the first surface second conductive layer 33 overlaps the first surface first conductive layer 31, the first surface second conductive layer 33 of the first surface second conductive layer 33 faces the first surface first conductive layer 31. It is easy to cause variation in the area of the As a result, the capacitance of the capacitor 15 tends to vary.

  On the other hand, in the present modification, the first surface second conductive layer 33 at least partially overlaps the end 31 e of the first surface first conductive layer 31. For example, in the case where the first surface second conductive layer 33 has a substantially rectangular shape in a plan view, the end 33e constituting the pair of opposing sides of the end 33e of the first surface second conductive layer 33 is the first It is located outside the end 31 e of the surface first conductive layer 31. Thereby, it can suppress that the curved corner part 33f of the 1st surface 2nd conductive layer 33 overlaps with the 1st surface 1st conductive layer 31. As shown in FIG. As a result, the variation in the area of the portion of the first surface second conductive layer 33 facing the first surface first conductive layer 31 is suppressed, and the variation in capacitance of the capacitor 15 is suppressed. Can. Note that “outside” means the side away from the center of the capacitor 15 in plan view. The distance d between the end 31 e of the first surface first conductive layer 31 and the end 33 e of the first surface second conductive layer 33 in a plan view is, for example, 20 μm or more and 500 μm or less.

(Second Modification of Capacitor)
FIG. 18 is a plan view showing the capacitor 15 of the capacitor built-in part 10 according to the present modification. FIG. 19 is a cross-sectional view of the capacitor 15 taken along line D-D in FIG. In the present modification, the upper conductive layer facing the first surface first inorganic layer 32 which is the dielectric of the capacitor 15 from the opposite side to the substrate 12 is constituted by the first surface third conductive layer 35. In addition, in FIG.18 and FIG.19, the 1st surface 2nd organic layer 36 is abbreviate | omitted.

  A method of manufacturing the capacitor 15 according to the present modification will be described. In the present modification, after the first surface first inorganic layer 32 is formed, the step of forming the first surface first organic layer 34 is performed. Specifically, the first surface first organic layer 34 having the opening 34 a overlapping the first surface first inorganic layer 32 of the capacitor 15 is at least partially formed on the first surface first inorganic layer 32 of the capacitor 15. To form. At this time, the opening 34a of the first surface first organic layer 34 is formed on the inner side of the first surface first conductive layer 31, as shown in FIGS.

  Thereafter, the first surface third conductive layer 35 is formed on the first surface first organic layer 34 and the opening 34 a. Thereby, the first surface third conductive layer 35 can be stacked on the first surface first inorganic layer 32 inside the opening 34 a. The first surface third conductive layer 35 formed on the first surface first inorganic layer 32 inside the opening 34 a functions as the upper conductive layer of the capacitor 15.

  If the first surface third conductive layer 35 has a substantially rectangular shape in plan view, the first surface third conductive layer 35 is preferably an end portion of the first surface third conductive layer 35 as shown in FIG. It forms so that the edge part 35e which comprises a pair of edge | side which opposes among 35e may be located on the 1st surface 1st organic layer 34 instead of the inside of the opening part 34a. Thereby, it can suppress that the curved corner part 35f of the 1st surface 3rd conductive layer 35 overlaps with the 1st surface 1st conductive layer 31. As shown in FIG. This suppresses variation in the area of the portion of the first surface third conductive layer 35 facing the first surface first conductive layer 31 via the first surface first inorganic layer 32, thereby preventing the capacitor The variation of the capacitance of 15 can be suppressed. Preferably, as shown in FIG. 18, the end 35 e forming the pair of opposing sides of the end 35 e of the first surface third conductive layer 35 is closer to the end 31 e of the first surface first conductive layer 31. Also located outside.

(Modified example of through hole)
In the above embodiment, an example is shown in which the width of the through hole 20 in the surface direction of the substrate 12 decreases from the first surface 13 and the second surface 14 of the substrate 12 toward the central portion in the thickness direction of the substrate 12 The However, the present invention is not limited to this, and as shown in FIG. 20, the width of the through hole 20 may be smaller as it goes from the first surface 13 side to the second surface 14 side.

(Modified example of average surface roughness)
In the above-described embodiment, an example is shown in which the arithmetic average surface roughness defined in JIS B 0601: 2001 is adopted as the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31. . Further, as an example of the measurement range of the average surface roughness, a square area having a side length of 150 μm was shown. That is, an example is shown in which the size of the area scanned by the measuring instrument during measurement is 150 μm. Further, the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 calculated by scanning a 150 μm area based on JIS B 0601: 2001 is preferably 0.1 μm or more and preferably An example of 0.4 μm or less is shown. However, the measuring method and the preferred range of the average surface roughness are not limited to the above-mentioned examples. Hereinafter, an example of measuring the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 by a method different from the above-described method will be described. Such a separate measurement method may be employed instead of the above-mentioned measurement method, or may be adopted in addition to the above-mentioned measurement method. Also, in the following description, the dimension of the area scanned by the measuring instrument in the measurement of the surface roughness is also referred to as the evaluation length.

  First, the states of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 assumed in the present modification will be described. FIG. 21 is a cross-sectional view showing an example of the upper surface 311 of the first surface first conductive layer 31 in an enlarged manner. As shown in FIG. 21, the top surface 311 of the first surface first conductive layer 31 has a concavo-convex shape having a first period P1 and a concavo-convex shape having a second period smaller than the first period P1. The first period P1 is, for example, a period of the uneven shape due to the variation in the thickness of the plating layer formed by the plating method among the layers constituting the first surface first conductive layer 31. The first period P1 is, for example, 0.4 μm or more and 1.0 μm or less. The second period P2 is, for example, a period of a concavo-convex shape formed by exposing the surface of the first surface first conductive layer 31 to the etching solution and scraping it. The second period P2 is, for example, 0.05 μm or more and 0.4 μm or less.

  When the inventor of the present invention has conducted research, the first surface first conductivity is the average surface roughness due to the uneven shape of the second period P2 rather than the average surface roughness due to the uneven shape of the first period P1. It was found that the correlation between the adhesion of the first surface first inorganic layer 32 to the layer 31 and the capacitance of the capacitor 15 was high. Moreover, in order to measure average surface roughness resulting from the uneven | corrugated shape of 2nd period P2, it discovered that it was preferable to make evaluation length smaller than 150 micrometers in the case of the above-mentioned this embodiment. Based on these findings, in this modification, it is proposed that the arithmetic average surface roughness defined in JIS R 1683: 2007 be adopted as the average surface roughness, and that the evaluation length be 2.5 μm. Do. Thereby, it is possible to calculate the average surface roughness having a higher correlation with the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 and the capacitance of the capacitor 15.

  The average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31 which is calculated based on JIS R 1683: 2007 when the measurement is performed with an evaluation length of 2.5 μm is preferably 0. It is 22 μm or less, more preferably 0.2 μm or less. Thereby, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 can be enhanced. Also, the capacitance of the capacitor 15 can be increased. In addition, the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31, which is calculated based on JIS R 1683: 2007 when measurement is performed with an evaluation length of 2.5 μm, is preferably It is 0.075 μm or more, more preferably 0.80 μm or more.

  An atomic force microscope can be used as a measuring device for calculating the arithmetic mean surface roughness defined in JIS R 1683: 2007. For example, it is possible to use a roughness measurement function based on JIS R 1683 mounted on AFM 5000 manufactured by Hitachi High-Technologies Corporation.

  As the average surface roughness of the upper surface 311 and the side surface 312 of the first surface first conductive layer 31, the arithmetic average surface roughness of the upper surface 311 and the side surface 312 of the plurality of, for example, ten first surface first conductive layers 31 is It may measure using a measuring instrument, and may adopt those average values.

Mounting Substrate FIG. 22 is a cross-sectional view showing an example of the mounting substrate 60 including the capacitor built-in component 10 and the element 50 mounted on the capacitor built-in component 10. The element 50 is an LSI chip such as a logic IC or a memory IC. The element 50 may also be a MEMS (Micro Electro Mechanical Systems) chip. A MEMS chip is an electronic device in which mechanical component parts, sensors, actuators, electronic circuits, etc. are integrated on one substrate. As shown in FIG. 22, the element 50 has a terminal 51 electrically connected to a conductive layer such as the first surface third conductive layer 35 of the capacitor built-in component 10.

Example of Product on Which Passing Electrode Substrate is Mounted FIG. 23 is a diagram illustrating an example of a product on which the capacitor built-in component 10 according to the embodiment of the present disclosure may be mounted. The capacitor built-in component 10 according to an embodiment of the present disclosure may be utilized in various products. For example, it is mounted on a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smart phone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180 and the like.

  Next, the embodiments of the present disclosure will be more specifically described by way of examples. However, the embodiments of the present disclosure are not limited to the descriptions of the following examples as long as the gist of the embodiments is not exceeded.

(First measurement)
Samples 1 to 15 were prepared, each including the capacitor 15 having the first surface first conductive layer 31, the first surface first inorganic layer 32, and the first surface second conductive layer 33 stacked in order from the above-described substrate 12 side. . As the first surface first conductive layer 31, one including the first layer 221 functioning as a seed layer and the second layer 222 of copper formed on the first layer 221 by electrolytic plating was used. As the first surface first inorganic layer 32, a layer of silicon nitride (SiN) formed by plasma CVD was used. Moreover, before forming the 1st surface 1st inorganic layer 32 on the 1st surface 1st conductive layer 31, the average surface roughness of the 1st surface 1st conductive layer 31 was measured. The measurement of the average surface roughness was performed in accordance with JIS B 0601: 2001 within a square area having a side length L1 of 150 μm. The average surface roughness of the first surface first conductive layer 31 reflects the surface roughness of the first layer 221 which is roughened when the unnecessary first layer 221 is removed by etching. The measurement results of the thickness of the first surface first inorganic layer 32 and the average surface roughness of the first surface first conductive layer 31 in each sample are shown in FIG.

  Subsequently, the leakage current of the capacitor 15 of each sample was measured. The measurement results are also shown in FIG.

  Further, the adhesion of the first surface first inorganic layer 32 to the first surface first conductive layer 31 was evaluated based on the cross-cut peeling test. The evaluation results are shown in FIG.

As shown in FIG. 24, in the samples 5, 10 and 15, the leakage current exceeded 1 × 10 ⁻⁸ A, and the judgment was therefore “bad”. In Samples 5, 10 and 15, the average surface roughness of the first surface first conductive layer 31 exceeds 0.4 μm, which is considered to result in an increase in leakage current.

  As shown in FIG. 24, in the samples 4, 9 and 14, peeling of the first surface first inorganic layer 32 from the first surface first conductive layer 31 has occurred, and therefore the determination is “bad”. In Samples 4, 9 and 14, the average surface roughness of the first surface first conductive layer 31 is less than 0.1 μm, and hence the first surface first inorganic layer 32 relative to the first surface first conductive layer 31. It is considered that the adhesion of

As shown in FIG. 24, in Samples 1 to 3, 6 to ⁸ and 11 to 13, the leakage current is 1 × 10 ⁻⁸ A or less, and the first surface from the first surface first conductive layer 31 1 Peeling of the inorganic layer 32 did not occur. Therefore, the determination is "good". In the samples 1 to 3, 6 to 8 and 11 to 13, when the average surface roughness of the first surface first conductive layer 31 is 0.1 μm or more and 0.4 μm or less, the adhesion is suppressed while suppressing the leakage current. It is thought that it was possible to improve sex.

(Second measurement)
The first surface of each sample in the same manner as the first measurement described above, except that the measurement of the average surface roughness was performed at an evaluation length of 2.5 μm in accordance with JIS R 1683: 2007. The average surface roughness of the first conductive layer 31 was measured. Further, the leak current and the adhesion of each sample were evaluated in the same manner as the first measurement described above. The results are shown in FIG.

As shown in FIG. 24, in the samples 5, 10 and 15 in which the leakage current exceeds 1 × 10 ⁻⁸ A, the first surface first conductive layer 31 calculated when the evaluation length is 2.5 μm. The average surface roughness of the above was over 0.24 μm. On the other hand, when the average surface roughness of the first surface first conductive layer 31 calculated when the evaluation length is 2.5 μm is 0.22 μm or less, the leakage current is 1 × 10 ⁻⁸ A or less More specifically, it was 1 × 10 ⁻⁹ A or less.

  As shown in FIG. 24, in the samples 4, 9 and 14 in which peeling of the first surface first inorganic layer 32 from the first surface first conductive layer 31 occurred, the evaluation length was 2.5 μm. The calculated average surface roughness of the first surface first conductive layer 31 was 0.70 μ or less. On the other hand, when the average surface roughness of the first surface first conductive layer 31 calculated when the evaluation length is 2.5 μm is 0.75 μm or more, the first surface from the first surface first conductive layer 31 There was no peeling of the first side first inorganic layer 32.

DESCRIPTION OF REFERENCE NUMERALS 10 capacitor built-in component 12 substrate 13 first surface 14 second surface 15 capacitor 16 inductor 20 through hole 21 side wall 22 through electrode 221 first layer 222 second layer 26 organic layer 30 first wiring structure portion 31 first surface first conductivity Layer 311 upper surface 312 side surface 32 first surface first inorganic layer 33 first surface second conductive layer 34 first surface first organic layer 35 first surface third conductive layer 36 first surface second organic layer 37 resist layer 40 first layer 2 wiring structure portion 41 second surface first conductive layer 43 second surface first organic layer 50 element 51 terminal 60 mounting substrate

Claims (21)

A substrate including a first surface and a second surface opposite to the first surface;
A capacitor located on the first surface of the substrate;
The capacitor includes a first surface first conductive layer located on the first surface of the substrate, a first surface first inorganic layer located on the first surface first conductive layer, and the first surface first conductive layer. An upper conductive layer located on the inorganic layer;
The component with a built-in capacitor, wherein the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor in the case of the evaluation length of 150 μm is 0.1 μm or more and 0.4 μm or less.   The capacitor built-in component according to claim 1, wherein the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor in the case of the evaluation length of 2.5 μm is 0.22 μm or less. The side surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm,
The capacitor built-in component according to claim 1, wherein the first surface first inorganic layer at least partially covers the side surface of the first surface first conductive layer.   The first surface first conductive layer of the capacitor has a thickness of 0.05 μm or more and 1.0 μm or less, and a conductive first layer, and a thickness of 5 μm or more and 20 μm or less, The capacitor built-in component according to any one of claims 1 to 3, further comprising: a second layer located on the first layer and having conductivity.   The capacitor built-in part according to claim 4, wherein the first layer contains titanium or chromium.   The capacitor built-in part according to claim 4 or 5, wherein the second layer contains copper.   The capacitor built-in component according to any one of claims 1 to 6, wherein the substrate comprises glass. The substrate is provided with a through hole,
The capacitor built-in component further includes an inductor electrically connected to the capacitor,
The inductor is electrically connected to the first surface first conductive layer, and the first surface first conductive layer, and includes the first layer and the second layer located on the wall surface of the through hole. The electrode according to claim 4, further comprising: an electrode; and a second surface first conductive layer electrically connected to the through electrode and including the first layer and the second layer located on the second surface of the substrate. 6. A capacitor built-in component according to any one of 6. to 6. The capacitor built-in component is
A first surface second conductive layer located on the first surface first inorganic layer;
A first surface first organic layer located at least partially on the first surface second conductive layer and having an opening overlapping the first surface second conductive layer;
A first surface third conductive layer at least partially located in the opening of the first surface first organic layer on the first surface second conductive layer;
The upper conductive layer of the capacitor is constituted by the first surface second conductive layer,
When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the end portion of the first surface second conductive layer of the capacitor is the first surface The capacitor built-in component according to any one of claims 1 to 8, which is located inside an end of the first conductive layer. The capacitor built-in component is
A first surface second conductive layer located on the first surface first inorganic layer;
A first surface first organic layer located at least partially on the first surface second conductive layer and having an opening overlapping the first surface second conductive layer;
A first surface third conductive layer at least partially located in the opening of the first surface first organic layer on the first surface second conductive layer;
The upper conductive layer of the capacitor is constituted by the first surface second conductive layer,
When the first surface second conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the first surface second conductive layer of the capacitor at least partially The capacitor built-in component according to any one of claims 1 to 8, overlapping an end of the first surface first conductive layer. The capacitor built-in component is
A first surface first organic layer at least partially located on the first surface first inorganic layer and in which an opening overlapping the first surface first inorganic layer is formed;
A first surface third conductive layer located in the opening of the first surface first organic layer on the first surface first inorganic layer;
The capacitor built-in component according to any one of claims 1 to 8, wherein the upper conductive layer of the capacitor is constituted by the first surface third conductive layer. A capacitor built-in component according to any one of claims 1 to 11,
And a device mounted on the capacitor built-in component. Preparing a substrate including a first surface and a second surface located opposite the first surface;
Forming a conductive first layer on the first surface of the substrate;
Forming a resist layer partially on the first layer;
Forming a conductive second layer on the first layer not covered with the resist layer by electrolytic plating;
Removing the resist layer;
Removing a portion of the first layer exposed from the second layer by etching;
Forming a first surface first inorganic layer on the second layer;
Forming an upper conductive layer on the first surface first inorganic layer;
A first surface first conductive layer including the first layer and the second layer; a first surface first inorganic layer on the second layer of the first surface first conductive layer; and The upper conductive layer on one inorganic layer constitutes a capacitor,
The manufacturing method of a capacitor built-in part whose average surface roughness in case evaluation length is 150 micrometers is 0.1 micrometer or more and 0.4 micrometers or less of the upper surface of the 1st field 1st conductive layer of the capacitor.   The method of manufacturing a capacitor built-in component according to claim 13, wherein the average surface roughness of the upper surface of the first surface first conductive layer of the capacitor in the case of the evaluation length of 2.5 μm is 0.22 μm or less. . The side surface of the first surface first conductive layer of the capacitor has an average surface roughness of 0.1 μm or more and 0.4 μm or less when the evaluation length is 150 μm,
The method of manufacturing a capacitor built-in component according to claim 13, wherein the first surface first inorganic layer at least partially covers the side surface of the first surface first conductive layer. The thickness of the first layer is 0.05 μm or more and 1.0 μm or less,
The method of manufacturing a capacitor built-in component according to any one of claims 13 to 15, wherein a thickness of the second layer is 5 μm or more and 20 μm or less.   The method for manufacturing a capacitor built-in component according to any one of claims 13 to 16, wherein the substrate comprises glass. The substrate is provided with a through hole,
The first layer and the second layer are also formed on the wall surface of the through hole and the second surface of the substrate,
The first surface includes a first conductive layer, a through electrode including the first layer and the second layer on the wall surface of the through hole, and the first layer and the second layer on the second surface. The method for manufacturing a capacitor built-in component according to any one of claims 13 to 17, wherein an inductor electrically connected to the capacitor is configured by the second surface first conductive layer. The method of manufacturing the capacitor built-in component is
Forming a first surface first organic layer having an opening overlapping the upper conductive layer at least partially on the upper conductive layer;
Forming a first surface third conductive layer in the opening of the first surface first organic layer on the upper conductive layer;
When the upper conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the end of the upper conductive layer of the capacitor is from the end of the first conductive layer. The method for manufacturing a capacitor built-in part according to any one of claims 13 to 18, wherein the method is also located inside. The method of manufacturing the capacitor built-in component is
Forming a first surface first organic layer having an opening overlapping the upper conductive layer at least partially on the upper conductive layer;
Forming a first surface third conductive layer in the opening of the first surface first organic layer on the upper conductive layer;
When the upper conductive layer of the capacitor is viewed along the normal direction of the first surface of the substrate, the upper conductive layer of the capacitor is at least partially an end of the first surface first conductive layer The method for manufacturing a capacitor built-in part according to any one of claims 13 to 18, wherein the part is overlapped with the part. The method of manufacturing the capacitor built-in component is
Forming a first surface first organic layer having an opening overlapping the first surface first inorganic layer of the capacitor at least partially on the first surface first inorganic layer;
In the step of forming the upper conductive layer, the upper conductive layer is formed in the opening of the first surface first organic layer on the first surface first inorganic layer of the capacitor. A manufacturing method of a capacitor built-in part given in any 1 paragraph of 18.