JP7284619B2 - game machine - Google Patents

Description

The present invention relates to a game machine such as a pachinko machine, an arrangement ball machine, a mammoth ball game machine, and a slot machine, and more particularly to a game machine capable of reducing program processing load and program capacity .

2. Description of the Related Art As a conventional game machine such as a pachinko machine, for example, a game machine as described in Patent Document 1 is known. This game machine uses a bit number larger than the basic number of bits, thereby devising the data arrangement of the ROM.

JP 2014-208154 A

However, the gaming machine described above has a problem that it is not possible to reduce the processing load of the program and reduce the program capacity .

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a game machine capable of reducing the processing load of a program and reducing the program capacity .

The above objects of the present invention are achieved by the following means. In addition, although the inside of parenthesis is attached with the reference code|symbol of embodiment mentioned later, this invention is not limited to this.

According to the gaming machine according to the invention of claim 1, game means capable of executing a symbol variation game (for example, a main control CPU 600a shown in FIG. 7),
ROM (for example, main control ROM 600b shown in FIG. 7) in which a plurality of data related to the symbol variation game are stored;
Data reading means (for example, the main control CPU 600a shown in FIG. 7) that reads specific data specified from the plurality of data to a storage means (for example, a general-purpose register 600a1 shown in FIG. 15);
a first address address information storage means (for example, refer to the HL register shown in FIGS. 16(a) and 16(b)) for storing first address information relating to the address of the area in which the specific data is stored;
a second address address information storage means (see, for example, the TP register 600a4 shown in FIGS. 16A and 16B) for storing second address information relating to the address addresses of the areas in which the plurality of data are stored;
a measurement process for measuring a predetermined value related to a game value to be provided to a game based on establishment of a predetermined condition in a predetermined game program;
Lottery processing for performing a lottery as to whether or not to generate a special game state;
a command transmission process related to command transmission;
The data reading means (for example, the main control CPU 600a shown in FIG. 7)
Based on the first address information and the second address information, the specific address where the specific data is stored is referenced, and the specific data is stored in the storage means (for example, the general-purpose register 600a1 shown in FIG. 15). is readable to
The ROM (for example, the main control ROM 600b shown in FIG. 7) is
a first storage area that can be specified by the second address information (for example, a normal data area 600bc of the main control ROM 600b shown in FIG. 9B);
a second storage area that cannot be specified by the second address information (for example, a measurement data area 600bc of the main control ROM 600b shown in FIG. 9B),
A first process (for example, a game process such as a lottery process) that performs a process using data stored in the first storage area (for example, a normal data area 600bc of the main control ROM 600b shown in FIG. 9B); ,
Second processing (for example, the number of winning balls, the number of non-winning processing to measure the total number of game balls fired into the game area including
Transition from the first process (for example, a game process such as a lottery process) to the second process (for example, a process for measuring the total number of game balls shot into the game area including the number of prize balls and the number of non-win prizes) , the second address information is transferred from the second address information storage means (for example, see the TP register 600a4 shown in FIGS. 16(a) and 16(b)) to a predetermined storage area (for example, FIG. 9(a) Execute the second address address information saving process to save to the measurement stack area 600cg) of the main control RAM 600c shown in
Transition from the second process (for example, the process of measuring the total number of game balls shot into the game area including the number of winning balls and the number of non-winning balls, etc.) to the first process (for example, the game process such as lottery processing) 16 ( a) and (b) (see TP register 600a4 shown in FIG. 23(b), FIG. 24, and FIG. 25) to execute the second address information return processing (see, for example, "POP TP" shown in FIGS. 23(b), 24, and 25),
The predetermined game program includes a plurality of call instructions capable of calling predetermined modules,
the plurality of call instructions include a first call instruction (e.g., CALL instruction), a second call instruction (e.g., CALL_M instruction), and a third call instruction (e.g., CALL_S instruction);
the first call instruction (for example, CALL instruction) has no restriction on the address address of the module to be called among the plurality of call instructions (see, for example, paragraph [0143] of the specification);
The second call instruction (for example, CALL_M instruction) has a program code data amount smaller than that of the first call instruction (for example, CALL instruction), and among the plurality of call instructions, the module to be called the address is within a predetermined range (see, for example, paragraphs [0141] and [0143] of the specification);
the third call instruction (for example, CALL_S instruction) has the smallest amount of program code data among the plurality of call instructions (see, for example, paragraph [0121] of the specification);
The predetermined game program includes a normal program used during game processing (for example, a program stored in the normal program area 600ba shown in FIG. 9B) and a measurement program used for the measurement processing. (For example, a program stored in the measurement program area 600be shown in FIG. 9B),
The command transmission process is a normal program called by the third call instruction (for example, CALL_S instruction) from the normal program (for example, the program stored in the normal program area 600ba shown in FIG. 9B). as a module in the program,
The third call instruction (for example, CALL_S instruction) that calls the command transmission process is executed in the normal program (for example, the program stored in the normal program area 600ba shown in FIG. 9B) for a predetermined time. The frequency of use in the game program in the interrupt process executed based on the timer interrupt signal generated every time is higher than the frequency used in the game program from the initial process to the main loop process where the interrupt process is called. (See, for example, paragraph [0140] of the specification).
According to the gaming machine according to the invention of claim 2, game means capable of executing a symbol variation game (for example, a main control CPU 600a shown in FIG. 7),
ROM (for example, main control ROM 600b shown in FIG. 7) in which a plurality of data related to the symbol variation game are stored;
Data reading means (for example, the main control CPU 600a shown in FIG. 7) that reads specific data specified from the plurality of data to a storage means (for example, a general-purpose register 600a1 shown in FIG. 15);
a first address address information storage means (for example, refer to the HL register shown in FIGS. 16(a) and 16(b)) for storing first address information relating to the address of the area in which the specific data is stored;
a second address address information storage means (see, for example, the TP register 600a4 shown in FIGS. 16A and 16B) for storing second address information relating to the address addresses of the areas in which the plurality of data are stored;
a measurement process for measuring a predetermined value related to a game value to be provided to a game based on establishment of a predetermined condition in a predetermined game program;
Lottery processing for performing a lottery as to whether or not to generate a special game state;
a command transmission process related to command transmission ;
The data reading means (for example, the main control CPU 600a shown in FIG. 7)
Based on the first address information and the second address information, the specific address where the specific data is stored is referenced, and the specific data is stored in the storage means (for example, the general-purpose register 600a1 shown in FIG. 15). is readable to
The ROM (for example, the main control ROM 600b shown in FIG. 7) is
a first storage area that can be specified by the second address information (for example, a normal data area 600bc of the main control ROM 600b shown in FIG. 9B);
a second storage area that cannot be specified by the second address information (for example, a measurement data area 600bc of the main control ROM 600b shown in FIG. 9B),
A first process (for example, a game process such as a lottery process) that performs a process using data stored in the first storage area (for example, a normal data area 600bc of the main control ROM 600b shown in FIG. 9B); ,
Second processing (for example, the number of winning balls, the number of non-winning processing to measure the total number of game balls fired into the game area including
The first process (for example, a game process such as a lottery process) includes a first game process (for example, a special symbol variation variation pattern command generation process described in the program shown in FIG. 26(a)) related to the symbol variation game. 2 game processing (for example, special symbol variation variation pattern command transmission processing described in the program shown in FIG. 26 (a)) and
From the first game process (for example, the process excluding the "CALL_S_CMDOUT" program described in the program shown in FIG. 26(a)) to the second game process (for example, " CALL_S_CMDOUT” program example), the data stored in the storage means (for example, the general-purpose register 600a1 shown in FIG. 15) is stored in a predetermined storage area (for example, the main control RAM 600c shown in FIG. 9A). (for example, see "PUSH ALL" shown in FIG. 26(a)) is executed, but the second address information is saved to the normal stack area 600cc). The second data is saved from means (for example, see TP register 600a4 shown in FIGS. 16(a) and 16(b)) to a predetermined storage area (for example, normal stack area 600cc of main control RAM 600c shown in FIG. 9(a)). Address address information save processing (see, for example, "PUSH TP" shown in FIG. 23(b)) is not executed,
From the second game process (for example, a program example of "CALL_S_CMDOUT" described in the program shown in FIG. 26(a)) to the first game process (for example, "CALL_S_CMDOUT" described in the program shown in FIG. 26(a) ), the data saved in the predetermined storage area (for example, the normal stack area 600cc of the main control RAM 600c shown in FIG. 9A) is transferred to the storage means (for example, 15) is executed (for example, see "POP ALL" shown in FIG. 26A), but the second address address information is returned to the predetermined storage area ( For example, the normal stack area 600cc of the main control RAM 600c shown in FIG. 9A is returned to the second address address information storage means (for example, see the TP register 600a4 shown in FIGS. The second address address information return process (see, for example, "POP TP" shown in FIG. 23(b)) is not executed,
The predetermined game program includes a plurality of call instructions capable of calling predetermined modules,
the plurality of call instructions include a first call instruction (e.g., CALL instruction), a second call instruction (e.g., CALL_M instruction), and a third call instruction (e.g., CALL_S instruction);
the first call instruction (for example, CALL instruction) has no restriction on the address address of the module to be called among the plurality of call instructions (see, for example, paragraph [0143] of the specification);
The second call instruction (for example, CALL_M instruction) has a program code data amount smaller than that of the first call instruction (for example, CALL instruction), and among the plurality of call instructions, the module to be called the address is within a predetermined range (see, for example, paragraphs [0141] and [0143] of the specification);
the third call instruction (for example, CALL_S instruction) has the smallest amount of program code data among the plurality of call instructions (see, for example, paragraph [0121] of the specification);
The predetermined game program includes a normal program used during game processing (for example, a program stored in the normal program area 600ba shown in FIG. 9B) and a measurement program used for the measurement processing. (For example, a program stored in the measurement program area 600be shown in FIG. 9B),
The command transmission process is a normal program called by the third call instruction (for example, CALL_S instruction) from the normal program (for example, the program stored in the normal program area 600ba shown in FIG. 9B). As a module in the program,
The third call instruction (for example, CALL_S instruction) that calls the command transmission process is executed in the normal program (for example, the program stored in the normal program area 600ba shown in FIG. 9B) for a predetermined time. The frequency of use in the game program in the interrupt process executed based on the timer interrupt signal generated every time is higher than the frequency used in the game program from the initial process to the main loop process where the interrupt process is called. (See, for example, paragraph [0140] of the specification).

According to the present invention , it is possible to reduce the processing load of the program and reduce the program capacity .

1 is a perspective view showing the appearance of a gaming machine according to one embodiment of the present invention; FIG. 2 is a front side perspective view showing a state in which the door of the game machine is opened before the game board according to the same embodiment is installed; FIG. It is a front view showing a state in which the door of the game machine is opened before the game board according to the same embodiment is installed. It is a perspective view of the back side showing the appearance of the gaming machine according to the same embodiment. It is a front view of the game board according to the same embodiment. It is the front perspective view which expanded and displayed the X section shown in FIG. It is a block diagram showing a control device of the game machine according to the same embodiment. (a) is a detailed view of the measurement display device according to the same embodiment, and (b) is a detailed view of the setting display device according to the same embodiment. (a) shows the memory area of the main control RAM which concerns on the same embodiment, (b) is explanatory drawing explaining the memory map which shows the memory area of the main control ROM which concerns on the same embodiment. (a) shows the conventional data arrangement of main control ROM, (b) is explanatory drawing which shows the data arrangement of main control ROM which concerns on the same embodiment. 10(a) shows a program example for arranging the data shown in FIG. 10(b), and FIG. 10(b) shows a program example for reading the data shown in FIG. 10(b). FIG. FIG. 12 is a diagram showing a program example showing another embodiment different from the program example shown in FIG. 11(a); (a) shows an example of a conventional counter program, (b) shows an example of a counter program according to the same embodiment, and (c) shows an example of a program when the counter program shown in (b) is made into a general-purpose module. and (d) is a diagram showing an example of a program when calling the general-purpose modularized program shown in (c). (a) shows a program example of the table address of a subroutine that can be called by the CALL_S instruction, (b) shows a program example showing part of the main control initialization processing, and (c) shows in (b) 4 shows a program example of a CTC setting table, (d) shows a program example of data set processing shown in (b), (e) shows a program example of command transmission processing shown in (b), and (f) shows a program example of It is a figure which shows the program example of the main loop process of main control. It is an explanatory diagram for explaining the internal register of the main control CPU. (a) is an explanatory diagram explaining how the value stored in the HL register is processed by the LDB instruction; Explanatory drawing explaining acquisition of data for a predetermined number of bits from the th bit, (b) is following (a), again, the value stored in the HL register is processed by the LDB instruction. (b-1) is an explanatory diagram explaining acquisition of a predetermined number of bits of data from a predetermined bit of the address address calculated in (b). (a) shows a program example for selecting a big winning hole pattern according to the number of rounds of big wins, and (b) shows a program example of a big winning hole pattern selection table 1. FIG. (a) is an explanatory diagram for explaining how the value stored in the HL register is processed by the LDB instruction using the program shown in FIG. 17(a); 17(a) is an explanatory diagram for explaining acquisition of a predetermined number of bits of data from a predetermined bit of the address address calculated in (a), and (b) is an HL An explanatory diagram explaining how the value stored in the register is processed by the LDB instruction. FIG. 10 is an explanatory diagram illustrating acquisition of data for the number of bits; FIG. 10 is an explanatory diagram for explaining how an address is stored in an HL register by an LDT instruction; (a) shows a program example of special symbol variation pattern processing, (b) shows a program example of a special symbol variation pattern group address table, and (c) shows a program example of data search processing. It is a figure which shows the example of a program of the special figure fluctuation pattern group table 1. FIG. (a) shows a program example of the fluctuation distribution table H1, and (b) shows a program example of the fluctuation distribution table B1. (a) is an explanatory diagram explaining the registers that are saved when the internal registers of the main control CPU are saved with PUSH ALL, (b) is saved when the internal registers of the main control CPU are saved with PUSH TP FIG. 4 is an explanatory diagram for explaining a register; FIG. 10 is a diagram showing a program example of timer interrupt processing; FIG. 10 is a diagram showing a program example of main loop processing; (a) shows a program example of special symbol variation pattern data processing, (b) is a diagram showing a program example of a special symbol variation parameter specification table. (a) shows a program example of the special figure fluctuation time table 1, (b) is a diagram showing a program example of the special figure fluctuation time table 2. It is a flowchart figure explaining the main process of the main control which concerns on the same embodiment. FIG. 29 is a flowchart for explaining input management processing during main processing shown in FIG. 28; It is a flowchart figure explaining the timer interrupt processing of the main control which concerns on the same embodiment. It is a flowchart figure explaining the design process normally shown in FIG. It is a flowchart figure explaining the special design process shown in FIG. FIG. 33 is a flowchart for explaining a starting port check process 1 (2) shown in FIG. 32; FIG. 33 is a flowchart for explaining special symbol variation start processing shown in FIG. 32; 33. It is a flowchart figure explaining the process during special design fluctuation|variation shown in FIG. FIG. 33 is a flowchart for explaining processing during a special symbol confirmation time shown in FIG. 32; (a) shows a normal symbol winning determination table used when executing a winning lottery of normal symbols, (b) shows a special symbol jackpot determining table used when executing a winning lottery of special symbols, (c) is a diagram showing a special symbol small hit determination table used when executing a special symbol lottery.

Hereinafter, one embodiment of the gaming machine according to the present invention will be specifically described with reference to the drawings, taking a pachinko gaming machine as an example. In the following description, when the directions of up, down, left, and right are indicated, they refer to up, down, left, and right when viewed from the front of the drawing.

<Description of pachinko machine exterior configuration>
First, referring to FIGS. 1 to 6, the external configuration of the pachinko gaming machine according to the present embodiment will be described.

<Description of the exterior configuration of the front of the pachinko machine>
As shown in FIG. 1, the pachinko game machine 1 includes a wooden outer frame 2 and a hinge 4a (see FIG. 2) provided on the front surface of the outer frame 2 and on the left side thereof. It is provided with a rectangular front frame 3 which is pivotally mounted so as to be openable and detachable.

The front frame 3 includes an upper mounting portion 5 and a lower mounting portion 6 provided below the upper mounting portion 5, as shown in FIGS. On the front side of the upper mounting portion 5, an upper opening/closing door 7 supporting a transparent glass is pivoted about the vertical axis via the hinge 4a so as to be openable and detachable. A lower opening/closing door 8 is pivotally attached to the hinge 4b provided on the same side as the hinge 4a so as to be openable and detachable.

As shown in FIG. 1, the lower opening/closing door 8 has an upper tray 9 for storing discharged game balls, and a lower tray for receiving and storing surplus balls when the upper tray 9 is full. A receiving plate 10 is integrally formed. In addition, a ball lending button 11 and a prepaid card ejection button 12 (card return button 12) are provided on the lower opening/closing door 8, and a built-in lamp (not shown) is lit on the surface of the upper tray 9. A push button type performance button device 13 is provided which can change the performance effect by pressing it. Further, the upper receiving tray 9 is provided with a ball extracting button 14 for drawing down the game balls stored in the upper receiving tray 9, and further provided with a setting button 15 consisting of a substantially cross key. The setting button 15 can be operated by the player, and includes a circular determination key 15a provided in the center, a triangular up key 15b provided above the determination key 15a in the drawing, and a determination key 15b provided above the determination key 15a. A triangular left key 15c provided on the left side of the key 15a in the figure, a triangular right key 15d provided on the right side of the enter key 15a in the figure, and a triangular right key 15d provided on the lower side of the enter key 15a in the figure. and a lower key 15e.

On the other hand, on the right end side of the lower opening/closing door 8, as shown in FIG. 1, a firing handle 16 for operating the firing unit is provided, and as shown in FIGS. A speaker 17 that emits BGM (background music) or sound effects is provided on the face side and in the vicinity of the firing handle 16 . Decorative lamps, such as LED lamps, are arranged at various locations on the upper opening/closing door 7 and the lower opening/closing door 8 to produce a dramatic effect by light decoration.

On the other hand, as shown in FIGS. 2 and 3, the upper mounting portion 5 is provided with a game board mounting frame 18, and the game board YB (see FIG. 1) is attached to the game board mounting frame 18 as shown in FIG. It is installed with the game area 40 shown facing the front, and is fixed within the game board installation frame 18 . That is, as shown in FIG. 3, the upper mounting portion 5 is provided with a plurality of connectors 19 (four in the figure) for connection on the right side lower portion, so that these connectors 19 are connected to the game board YB. The game board YB is mounted in the game board mounting frame 18 by connecting a connector for connection (not shown) provided on the rear surface of the game board YB. Then, the game board YB is fixed within the game board mounting frame 18 by the fixtures 20a and 20b provided in the vertical direction on the right side. As a result, the game board YB is mounted in the game board mounting frame 18, and the upper opening/closing door 7 supporting the transparent glass is provided in front of the game area 40 of the game board YB (see FIG. 1). ). The game area 40 is an area surrounded by ball guide rails UR (see FIG. 5) arranged on the surface of the game board YB.

On the other hand, as shown in FIGS. 2 and 3 , the lower mounting portion 6 has a firing mechanism 21 arranged substantially in the center in the left-right direction, and a speaker 17 is placed on the right side of the firing mechanism 21 . As shown in FIG. 3, the shooting mechanism 21 includes a support plate 22 made of sheet metal, a shooting rail 23 attached to the front surface of the support plate 22, and a game ball attached to the front surface of the support plate 22 for shooting. a ball holding portion 25 that holds the ball at a firing standby position 24 on the firing rail 23; and a firing control board 71 having a firing motor for driving the hitting mallet 27 in the hitting direction via the drive shaft 26 .

<Description of the appearance configuration of the game board>
On the other hand, in the game area 40 of the game board YB, as shown in FIG. 5, a liquid crystal display device 41 comprising an LCD (Liquid Crystal Display) or the like is arranged substantially in the center. The liquid crystal display device 41 divides the display area into three areas, left, middle and right, and is capable of independently displaying numbers, characters, characters (character conversations, lyric telops, etc.) or special patterns. is. A top decoration 42a, a left decoration 42b, and a right decoration 42c are provided around the liquid crystal display device 41, and the back side of the top decoration 42a, the left decoration 42b, and the right decoration 42c are provided. A movable accessory device 43 is arranged.

As shown in FIG. 5, the movable accessory device 43 includes an upper movable accessory 43a, a left movable accessory 43b, a right movable accessory 43c, an upper left movable accessory, and a left movable accessory 43c, which performs a predetermined effect operation as the game progresses. It is composed of an object 43d and a motor (not shown) such as a two-phase stepping motor for driving the upper, left, right, and upper left movable accessories 43a to 43d, respectively. Decorative lamps, such as LED lamps, are arranged on these upper/left/right/upper left movable accessories 43a to 43d to produce a dramatic effect by light decoration.

On the other hand, right below the liquid crystal display device 41, a special symbol 1 starting port 44 is arranged, and a special symbol 1 starting port switch 44a (see FIG. 7) for detecting winning balls is provided inside. Then, the number of valid winning balls detected by the special symbol 1 starting port switch 44a (see FIG. 7), that is, the number of the first start holding balls is displayed on the liquid crystal display device 41 in a predetermined number (for example, 4). . It should be noted that the number of the first start and hold balls is added by 1 (+1) when a game ball enters the special symbol 1 start port 44 and is detected by the special symbol 1 start port switch 44a (see FIG. 7). When the variable display of special symbols such as numbers, characters or patterns (decoration patterns) is started, 1 is subtracted (-1).

On the other hand, a special symbol 2 starting port 45 is arranged on the lower right side of the liquid crystal display device 41, and a special symbol 2 starting port switch 45a (see FIG. 7) for detecting winning balls is provided therein. Then, the number of valid winning balls detected by the special pattern 2 starting port switch 45a (see FIG. 7), that is, the number of second start holding balls is displayed on the liquid crystal display device 41 in a predetermined number (for example, 4). . It should be noted that the number of the second starting and holding balls is added by 1 (+1) when a game ball enters the special symbol 2 starting port 45 and is detected by the special symbol 2 starting port switch 45a (see FIG. 7). When the variable display of special symbols such as numbers, characters or patterns (decoration patterns) is started, 1 is subtracted (-1).

On the other hand, as shown in FIG. 5, the special symbol 2 starting port 45 is provided with an opening/closing member 45b, and when the opening/closing member 45b is opened, a game ball is easily won. The opening/closing member 45b is opened for a predetermined number of times and for a predetermined period of time when a lottery for a normal symbol (to be described later) is won, and the opening/closing operation is controlled by a normal electric accessory solenoid 45c (see FIG. 7). In addition, hereinafter, a device including such an opening/closing member 45b and a normal electric accessory solenoid 45c may be referred to as a normal electric accessory.

On the other hand, a winning device 46 is arranged on the right side of the special symbol 1 starting port 44, as shown in FIG. The winning device 46 opens and closes a large winning opening (not shown) that is closed by the open/close door 46a when a special symbol lottery, which will be described later, is won, that is, in a special game state caused by a big win. The door 46a is driven and controlled by a special electric accessory solenoid 46b (see FIG. 7), and a game ball can enter a big winning hole (not shown). A game ball entering this big winning hole (not shown) is detected as a winning ball by a big winning hole switch 46c (see FIG. 7) provided inside the big winning hole (not shown).

On the other hand, when the special pattern lottery is not won, that is, when the special game state is not set, the opening/closing door 46a is driven and controlled by the special electric accessory solenoid 46b (see FIG. 7), and a large winning opening (not shown) is opened. is closed. As a result, the game ball cannot enter the big winning hole (not shown). Incidentally, hereinafter, a device combining such an opening/closing door 46a and a special electric accessory solenoid 46b may be referred to as a special electric accessory.

On the other hand, in the upper right part of the liquid crystal display device 41, as shown in FIG. 5, a normal symbol starting port 47 consisting of a gate is arranged. 7) are provided. In addition, on the right side of the winning device 46 and on the left side of the special symbol 1 start opening 44, general winning openings 48 are arranged, respectively. The general prize winning openings 48 are an upper right general winning opening 48a arranged on the right side of the winning device 46, an upper left general winning opening 48b arranged on the left side of the special symbol 1 starting opening 44, and a middle left general winning opening. It is composed of an opening 48c and a lower left general winning opening 48d. An upper right general prize winning port switch 48a1 (see FIG. 7) for detecting passage of game balls is provided inside the upper right general prize winning port 48a, and an upper left switch for detecting passage of game balls is provided inside the upper left general prize winning port 48b. A general winning opening switch 48b1 (see FIG. 7) is provided, and a middle left general winning opening switch 48c1 (see FIG. 7) for detecting passage of game balls is provided inside the middle left general winning opening 48c, and a lower left general winning opening is provided. Inside the opening 48d, a lower left general winning opening switch 48d1 (see FIG. 7) for detecting passage of game balls is provided.

On the other hand, directly below the special symbol 1 starting port 44, an out port 49 is arranged into which a game ball (out ball) that has flowed down to the most downstream part of the game area 40 without winning a prize is entered. A game ball entering the out port 49 is detected as a non-winning ball by an out port switch 49a (see FIG. 7) provided inside. Since it passes through and flows down to the most downstream part, it will be detected by the out port switch 49a (see FIG. 7). Therefore, the out port switch 49a (see FIG. 7) detects the total number of ejected outs, that is, the same number of game balls as the game balls shot into the game area 40 by the shooting handle 16. FIG.

On the other hand, in the lower right peripheral portion of the game area 40 of the game board 4, three 7-segments are arranged side by side, two of which are special symbol display devices 50, and the other 7-segments are special symbol display devices 50. It displays the number of start pending balls of symbol 1 and special symbol 2. As shown in FIG. 5, this special symbol display device 50 is composed of a special symbol 1 display device 50a and a special symbol 2 display device 50b. A normal symbol display device 51 composed of LEDs is provided. In the game area 40 of the game board 4, a plurality of game nails (not shown) are arranged, and a windmill 52 as a member for changing the falling direction of the game balls is arranged.

By the way, in the above description, in detecting the same number of game balls as the game balls shot into the game area 40 by the shooting handle 16, the total number of ejected outs is counted by the outlet switch 49a (see FIG. 7). Although an example of detection is shown, it is not limited to this, and as shown in FIG. 6, a game ball detection device UR1 having a game ball detection switch UR1a may be provided on the ball guide rail UR. That is, as shown in FIG. 6, the game ball YK shot toward the game area 40 by the shooting handle 16 moves in the arrow Y1 direction along the ball guide rail UR. Then, when the game ball YK that has moved in the direction of the arrow Y1 contacts the game ball detection switch UR1a, the game ball detection device UR1 detects the game ball shot by the shooting handle 16. FIG. Thus, even in this way, the same number of game balls as the game balls shot into the game area 40 by the shooting handle 16 can be detected.

By the way, in providing the game ball detection device UR1 equipped with such a game ball detection switch UR1a, the game ball YK shot toward the game area 40 by the shooting handle 16 moves to the tip portion URa of the ball guide rail UR. If the game ball YK reaches the game area 40, there is no problem. When it falls and enters the ball guide rail UR, the game ball YK reaches the game area 40 while moving in the directions of arrows Y3 and Y4 shown in FIG. At this time, when the game ball YK that has entered the ball guide rail UR contacts (collides) with the game ball detection device UR1, the game ball detection device UR1 mistakenly believes that the game ball YK has contacted the game ball detection switch UR1a, resulting in an error. may detect.

Therefore, in this embodiment, in order to prevent the game ball YK from contacting (colliding) with the game ball detection device UR1, the upper side (the right side in the drawing) of the game ball detection device UR1, that is, the portion located inside the ball guide rail UR is A protective wall UR2 is provided to cover it. As a result, the game ball YK that has entered the ball guide rail UR does not contact (collide) with the game ball detection device UR1, but contacts (collides) with the protective wall UR2, thereby preventing erroneous detection. .

On the other hand, as a method of preventing erroneous detection, it is also possible to deal with it by program processing without providing the protection wall UR2. That is, after the game ball detection device UR1 detects that the game ball YK has touched the game ball detection switch UR1a, a certain period (for example, 400 ms) of a detection invalid period may be provided. Even with this arrangement, when the game ball YK that has entered the ball guide rail UR contacts (collides) with the game ball detection device UR1, there is a high possibility of contact (collision) within the detection invalid period. , erroneous detection can be prevented. It should be noted that this certain period of time (for example, 400 ms) is preferably shorter than the interval (for example, 600 ms) at which shots are fired into the game area 40 by the shooting handle 16 . In addition, if some kind of trouble occurs in the game ball detection device UR1, for example, if the game ball detection device UR1 continues to detect that the game ball YK has touched the game ball detection switch UR1a for a period of 1000 ms, the game ball detection device An error may be notified assuming that some trouble has occurred in UR1.

<Description of the exterior configuration of the back of the pachinko machine>
As shown in FIG. 4, the rear surface of the pachinko game machine 1 constructed as described above is provided with a frame-shaped back mechanism plate 53 that covers the game board mounting frame 18 and holds down the game board YB from the back side. there is A game ball storage tank 54 for storing game balls supplied from a game ball replenishing device (not shown) of the pachinko hall side island facility is provided on the upper right side of the back mechanism plate 53. A tank rail 55 is provided for leading out balls from the game ball storage tank 54 .

A payout device 56 and a payout passage 57 are attached to the inclined lower end of the tank rail 55, and when a game ball enters a winning opening such as a big winning opening (not shown), or a game ball lending device When there is a ball lending command from (not shown), the game balls in the game ball storage tank 54 are paid out by the payout device 56 through the tank rail 55, and the game balls are sent through the payout passage 57 to the upper tray 9 ( (See Fig. 1).

In addition, a transparent back cover 58 (see also FIG. 3) detachably attached to the back side of the game board YB is attached to substantially the center of the back mechanism plate 53. A transparent performance control board case 90a containing a control board 90 and a transparent liquid crystal board case 120a containing a liquid crystal control board 120 are detachably provided. Under the effect control board case 90a, a transparent main control board case 60a containing a main control board 60 is detachably provided. A transparent payout control board case 70a containing the is detachably provided. Further, below the main control board case 60a, a power board case 130a containing a power board 130 is detachably provided.

<Description of the control device>
Next, a control device that performs electronic control according to the progress of a game provided in the pachinko game machine 1 having the above-described external configuration will be described with reference to FIG. As shown in FIG. 7, this control device includes a main control board 60 that controls the overall game operation, a payout control board 70 that pays out game balls based on control commands from the main control board 60, an image and a control board. It is mainly composed of a sub-control board 80 that controls light and sound. 7, the sub-control board 80 is composed of a performance control board 90, a decorative lamp board 100, and a liquid crystal control board 120. As shown in FIG.

<Description on the main control board>
The main control board 60 is composed of a main control CPU 600a, a main control ROM 600b that stores a game program describing a series of game control procedures, and a main control RAM 600c that functions as a work area and a buffer memory. A computer 600, a measurement display device 610 consisting of 7 segments for displaying contents regarding the ratio of how many prize balls are won in a low probability time (when the winning lottery probability is normal low probability), and a special game advantageous to the player. A setting display device 620 consisting of 7 segments for displaying the setting contents of the probability of generating a state, a RAM clear switch 630, a setting key switch 640, and a setting change switch 650 are mainly mounted.

A payout control board 70 for controlling the payout motor M to pay out game balls is connected to the main control board 60 configured as described above. And further, a special symbol 1 start port switch 44a for detecting winning to the special symbol 1 start port 44, a special symbol 2 start port switch 45a for detecting winning to the special symbol 2 start port 45, and a normal symbol start port A normal symbol start opening switch 47a for detecting the passage of 47 and a winning to the general winning opening 48 (upper right general winning opening 48a, upper left general winning opening 48b, middle left general winning opening 48c, lower left general winning opening 48d) are detected. An upper right general winning opening switch 48a1, an upper left general winning opening switch 48b1, a middle left general winning opening switch 48c1, a lower left general winning opening switch 48d1, and a large winning opening (not shown) opened or closed by the open/close door 46a. A large winning opening switch 46c for detection and an out opening switch 49a capable of detecting the same number of game balls as the game balls shot into the game area 40 by the shooting handle 16 are connected. Furthermore, a normal electric accessory solenoid 45c that controls the operation of the opening/closing member 45b, a special electric accessory solenoid 46b that controls the operation of the opening/closing door 46a, a special symbol 1 display device 50a, and a special symbol 2 display device 50b , and the normal symbol display device 51 are connected.

The main control board 60 configured in this way is advantageous to the player when the main control CPU 600a receives a signal from the special symbol 1 starting port switch 44a, the special symbol 2 starting port switch 45a, or the normal symbol starting port switch 47a. A lottery is conducted to determine whether to generate a special game state (so-called "win") or not to generate a special game state that is advantageous to the player (so-called "losing"), and the lottery result is the success or failure information. The variation pattern of the special design, the display contents of the stop design or the normal design are determined, and the determined information is transmitted to the special design 1 display device 50a, the special design 2 display device 50b or the normal design display device 51. As a result, the lottery result is displayed on the special symbol 1 display device 50a, the special symbol 2 display device 50b, or the normal symbol display device 51. Further, the main control board 60 , that is, the main control CPU 600 a generates an effect control command DI_CMD including the determined information and transmits it to the effect control board 90 . In addition, the main control board 60, that is, the main control CPU 600a, the special symbol 1 starting opening switch 44a, the special symbol 2 starting opening switch 45a, the upper right general winning opening switch 48a1, the upper left general winning opening switch 48b1, the middle left general winning opening switch When receiving signals from 48c1, lower left general winning opening switch 48d1, and large winning opening switch 46c, it decides how many game balls to pay out to the player, and pays out a payout control command PAY_CMD including the determined information. By transmitting to the control board 70, the payout control board 70 pays out game balls to the player.

As a result of the lottery, when the lottery for the normal pattern is won, the normal electric accessory solenoid 45c is driven and controlled so that the opening/closing member 45b is opened for a predetermined number of times for a predetermined period of time, and when the lottery for the special pattern is won, A special electric accessary item solenoid 46b is controlled to open a large winning opening (not shown).

On the other hand, the main control board 60, that is, the main control CPU 600a, includes the special symbol 1 starting opening switch 44a, the special symbol 2 starting opening switch 45a, the upper right general winning opening switch 48a1, the upper left general winning opening switch 48b1, and the middle left general winning opening switch. Each time a signal is received from 48c1, a lower left general prize winning port switch 48d1, and a large winning prize port switch 46c, the number of prize balls is counted, and each time a signal is received from the out port switch 49a, the total number of discharged game balls is counted. to measure Then, the main control board 60, that is, the main control CPU 600a, based on the measured number of prize balls and the total number of discharged game balls, the content (performance display) regarding the ratio of how many prize balls were played at the time of low probability Output to the measurement display device 610 . As a result, the measurement display device 610 displays the content (performance display) related to the ratio of how many prize balls were won at the time of low probability.

To explain this measurement display device 610 in more detail, the measurement display device 610 includes, as shown in FIG. 610B, a third measurement display device 610C consisting of 7 segments, and a fourth measurement display device 610D consisting of 7 segments. 610B, the third measurement display device 610C, and the fourth measurement display device 610D display the contents (performance display) related to the ratio of how many prize balls were won at the time of low probability.

On the other hand, the setting display device 620, as shown in FIG. 6” can be displayed in six steps. In order to change such setting contents, a special key is inserted into the setting key switch 640, and when it is turned on, the setting change switch 650 is operated to generate a special game state advantageous to the player. For example, the setting contents can be changed in six stages from "1" to "6" (for example, the setting "6" has the highest probability of generating a special game state advantageous to the player). , setting "1" has the lowest probability of generating a special game state advantageous to the player). The content of the setting change is displayed on the setting display device 620, and when the content of the setting change is confirmed, the dot on the lower right side of the 7-segment lights up to indicate that the content of the setting has been confirmed. there is In the following description, the setting change switch 650 has a function of changing the set content of the probability of generating a special game state advantageous to the player (setting change function) and a function of confirming the set change content (setting change function). However, of course, the setting change switch 650 has only the function of changing the setting contents of the probability of generating a special game state advantageous to the player, and the setting change contents are changed. may be determined by providing another switch.

On the other hand, when the RAM clear switch 630 is pressed, the memory area of the main control RAM 600c (see FIG. 7) is not cleared entirely, but only a part of the memory area is cleared. That is, as shown in FIG. 9(a), the main control RAM 600c has memory space addresses 0000H to 0100H out of memory space addresses 0000H to 0200H. In the normal RAM area 600ca used as a memory space address 0100H to 0110H is an unused area 600cb, and memory space address 0110H to 0130H is a normal used during game processing such as lottery processing In the stack area 600cc, the memory space addresses 0130H to 0150H are the unused area 600cd, and the memory space addresses 0150H to 0190H are the prize balls measured by the main control board 60, that is, the main control CPU 600. In the measurement RAM area 600ce that stores the total number of game balls shot into the game area 40, including the number and non-winning number, the memory space address 0190H to 01E0H is an unused area 600cf, and the memory space address 01E0H. Addresses to 0200H constitute a measurement stack area 600cg used for measuring the total number of game balls shot to the game area 40 including the number of winning balls and the number of non-winning balls.

Thus, in the main control RAM 600c configured in this way, when the RAM clear switch 630 is pressed, the measurement RAM area 600ce and the measurement stack area 600cg of the main control RAM 600c are not cleared, and the normal RAM area 600ca and the normal RAM area 600ca are cleared. 600cc of the stack area for use is cleared. By doing so, it is possible to prevent the total number of game balls shot into the game area 40 including the measured number of prize balls and the number of non-win prizes from being erroneously cleared. In this embodiment, when the RAM clear switch 630 is pressed, the normal RAM area 600ca and the normal stack area 600cc are cleared. Including, memory space addresses 0000H to 0150H may be cleared.

The normal RAM area 600ca, the normal stack area 600cc, the measurement RAM area 600ce, and the measurement stack area 600cg are each started from an address whose last digit is 0, and the normal RAM area 600ca and the normal stack are An unused area 600cb is provided between the area 600cc, an unused area 600cd is provided between the normal stack area 600cc and the measurement RAM area 600ce, and a measurement RAM area 600ce and measurement stack area 600cg are provided. By providing an unused area 600cf between . This prevents other areas from being affected when the program runs out of control.

On the other hand, as shown in FIG. 9B, the main control ROM 600b has memory space addresses 8000H to 8B90H out of memory space addresses 8000H to A800H. is stored in the normal program area 600ba, memory space addresses 8B90H to 9000H are unused areas 600bb, and memory space addresses 9000H to 9A00H are used for game processing such as lottery processing. In the normal data area 600bc where data is stored, memory space addresses 9A00H to 9C00H are unused areas 600bd, and memory space addresses 9C00H to A010H contain the number of prize balls and the number of non-win prizes. In the measurement program area 600be, which stores a program used for measuring the total number of game balls shot into the game area 40, memory space addresses A010H to A200H are unused areas 600bf, Memory space addresses A200H to A320H are a measurement data area in which data used when measuring the total number of game balls shot into the game area 40, including the number of winning balls and the number of non-winning balls, is stored. 600bg, memory space addresses A320H to A780H are an unused area 600bh, and memory space addresses A780H to A800H are a vector table area 600bi. The vector table area 600bi stores table addresses of subroutines that can be called by the CALL_S instruction among a plurality of call instructions described later.

The main control RAM 600c configured in this manner has a normal program area 600ba, a normal data area 600bc, a measurement program area 600be, a measurement data area 600bg, and a vector table area 600bi. Starting from an address starting from 0, an unused area 600bb is provided between the normal program area 600ba and the normal data area 600bc, and an unused area is provided between the normal data area 600bc and the measurement program area 600be. An unused area 600bf is provided between the measurement program area 600be and the measurement data area 600bg, and an unused area 600bh is provided between the measurement data area 600bg and the vector table area 600bi. By providing the area, each area can be distinguished. This prevents other areas from being affected when the program runs out of control.

<Description on payout control board>
The payout control board 70 receives a payout control command PAY_CMD from the main control board 60 (main control CPU 600a) and generates a payout motor signal based on the received payout control command PAY_CMD. Then, the generated payout motor signal is used to control the payout motor M to pay out game balls to the player. Furthermore, the payout control board 70 transmits a prize ball counting signal indicating the payout operation of the game balls and a status signal related to an abnormality in the payout operation, and a launch control board 71 that shoots the game balls in response to the player's operation. process to transmit a launch control signal to start or stop the operation of

<Description on production control board>
The production control board 90 stores a production control CPU 900 that receives the production control command DI_CMD from the main control board 60 (main control CPU 600a) and executes and controls various productions, and a control program that describes the production control procedure. It is composed of an effect control ROM 910 consisting of a flash memory and an effect control RAM 920 functioning as a work area, a buffer memory and the like. Furthermore, the production control board 90 is equipped with a sound LSI 930 for generating desired BGM and sound effects, and a sound ROM 940 in which sound data such as BGM and sound effects are stored in advance.

The effect control board 90 configured in this way is connected to a decorative lamp board 100 on which a decorative lamp such as an LED lamp that produces a lamp effect is mounted. ) A push-button type performance button device 13 is connected which can change the performance effect by being pressed by the player when lit, and a speaker 17 is connected to emit BGM, effect sound, and the like. Further, the effect control board 90 is connected with a movable accessory device 43 that performs a predetermined effect operation as the game progresses, and is connected with a setting button 15 that enables various settings, and controls the liquid crystal display device 41. A control board 120 is connected. Needless to say, this decorative lamp board 100 is also equipped with decorative lamps arranged on the upper, left, right, and upper left movable accessories 43a to 43d.

Thus, the effect control board 90 configured in this way can control the special symbol variation pattern based on the jackpot lottery result (whether it is a jackpot or a loss) transmitted from the main control board 60 (main control CPU 600a), the current game state, the The production control CPU 900 receives the production control command DI_CMD including the basic information required for the number of balls to be started and held, the number of balls to be started and the number of balls to be started and the decorative pattern to be stopped based on the lottery result. Then, the performance control CPU 900 determines a performance pattern corresponding to the received performance control command DI_CMD by lottery from many performance patterns stored in advance in the performance control ROM 910, and executes the determined performance pattern. The instructing control signal is temporarily stored in the effect control RAM 920 .

Then, the effect control CPU 900 transmits to the sound LSI 930 a control signal relating to sound among the control signals instructing execution of the effect patterns stored in the effect control RAM 920 . In response to this, the sound LSI 930 reads sound data corresponding to the control signal from the sound ROM 940 and outputs it to the speaker 17 . As a result, the speaker 17 emits BGM and sound effects corresponding to the determined production pattern.

Also, the effect control CPU 900 transmits to the decoration lamp board 100 a control signal related to light among the control signals for instructing the execution of the effect pattern stored in the effect control RAM 920 . As a result, the decorative lamp substrate 100 controls lighting or extinguishing of the decorative lamp such as the LED lamp that produces the lamp effect, so that the lamp effect corresponding to the determined effect pattern is executed. .

Furthermore, the effect control CPU 900 transmits to the liquid crystal control board 120 the liquid crystal control command LCD_CMD regarding the image among the control signals instructing the execution of the effect patterns stored in the effect control RAM 920 . As a result, the liquid crystal control board 120 controls the liquid crystal display device 41 so as to display an image based on the liquid crystal control command LCD_CMD, thereby displaying an image corresponding to the determined effect pattern on the liquid crystal display device 41. The Rukoto. The liquid crystal control board 120 stores various image data for displaying an image according to the content of the effect, and is also equipped with a VDP (Video Display Processor) that controls the output of the effect in general.

Furthermore, the effect control CPU 900 transmits to the movable accessory device 43 a control signal relating to the movable accessory among the control signals for instructing the execution of the effect patterns stored in the effect control RAM 920 . As a result, the movable accessory device 43 moves according to the determined effect pattern.

By the way, the power supply to each board described above is supplied from the power supply board 130 shown in FIG. The power supply board 130 includes a voltage generating section 1300 , a voltage monitoring section 1310 and a system reset generating section 1320 . The voltage generation unit 1300 receives an AC voltage of 24 V, which is an external power source supplied from a transformation transformer (not shown) installed in an amusement arcade, and generates a plurality of types of DC voltages. Although not shown, it is supplied to each substrate.

In addition, the voltage monitoring unit 1310 monitors the voltage of the AC 24V AC voltage, and when this voltage is interrupted or a power failure occurs and a voltage abnormality is detected, the voltage abnormality signal ALARM is sent to the main control board 60. is output to The voltage abnormality signal ALARM outputs a signal of "L" level when the voltage is abnormal, and outputs a signal of "H" level when it is normal.

On the other hand, the system reset generation unit 1320 generates a system reset signal when the power is turned on, and the generated system reset signal is output to each substrate, although not shown.

<Description of data arrangement in main control ROM>
Here, the arrangement of data stored in the normal data area 600bc and the measurement data area 600bg of the main control ROM 600b described above will be described with reference to FIG.

Conventionally, the data arrangement of the main control ROM 600b is configured in units of 1 byte, so depending on the type of data, the data arrangement includes unused bits among the 8 bits that make up 1 byte. . This point will be described in detail, taking as an example the data arrangement of the variable time data of the special symbol shown in FIG. 10(a).

It is assumed that there are a first variation time of 10 seconds, a second variation time of 30 seconds, a third variation time of 50 seconds, and a fourth variation time of 120 seconds as the data of the variation time of the special symbols. At this time, 10 seconds is 10,000 milliseconds, and as will be described later, when a timer interrupt occurs periodically every 4 ms, it counts by 1. Therefore, 10,000/4=2500, which is hexadecimal, is 09C4H. becomes. Therefore, when calculated in this way, 30 seconds is 1D4CH, 50 seconds is 30D4H, and 120 seconds is 7530H.

Thus, the first variable time data corresponding to 10 seconds is 09C4H, which when converted to binary numbers is "0000 1001 1100 0100", and as shown in FIG. In the conventional data arrangement of variable time data in 600bc, the lower 8 bits "1100 0100" are arranged at memory space address 9000H, and the upper 8 bits "0000 1001" are arranged at the next memory space address 9001H. will be placed.

Next, the second variable time data corresponding to 30 seconds is 1D4CH, which when converted to a binary number is "0001 1101 0100 1100", and as shown in FIG. In the conventional data arrangement of variable time data in 600bc, the lower 8 bits "0100 1100" are arranged at memory space address 9002H, and the upper 8 bits "0001 1101" are arranged at the next memory space address 9003H. will be placed.

Next, the third variable time data corresponding to 50 seconds is 30D4H, which when converted to a binary number is "0011 0000 1101 0100", and as shown in FIG. In the conventional data arrangement of variable time data in 600bc, the lower 8 bits "1101 0100" are arranged at memory space address 9004H, and the upper 8 bits "0011 0000" are arranged at the next memory space address 9005H. will be placed.

Next, the fourth variable time data corresponding to 120 seconds is 7530H, which when converted to binary number is "0111 0101 0011 0000", and as shown in FIG. In the conventional data arrangement of variable time data in 600bc, the lower 8 bits "0011 0000" are arranged at the memory space address 9006H, and the upper 8 bits "0111 0101" are arranged at the next memory space address 9007H. will be placed.

Thus, in the conventional data arrangement of variable time data, data is arranged for each memory space address.

However, with such data arrangement, the first variation time of 10 seconds, the second variation time of 30 seconds, the third variation time of 50 seconds, and the fourth variation time of 120 seconds are all Since all the 16th bits are "0", even though only 15 bits are required as the variable time data, the useless 1 bit is stored in the memory as shown in FIG. 10(a). They are arranged at the 8th bit of space address 9001H, the 8th bit of memory space address 9003H, the 8th bit of memory space address 9005H, and the 8th bit of memory space address 9007H. Therefore, in the conventional data arrangement, the data arrangement of the main control ROM 600b cannot be efficiently performed, and thus the data capacity of the main control ROM 600b cannot be reduced.

Therefore, in this embodiment, the data stored in the normal data area 600bc is arranged as shown in FIG. 10(b) in order to efficiently arrange the data in the main control ROM 600b.

That is, the first variable time data corresponding to 10 seconds is 09C4H, and the 15-bit data to be used is expressed in binary notation as "000 1001 1100 0100", as shown in FIG. 10(b). , the lower 8 bits "1100 0100" are arranged at the memory space address 9000H, and the upper 7 bits "000 1001" are arranged at the next memory space address 9001H.

Next, the second variable time data corresponding to 30 seconds is 1D4CH, and when the 15-bit data to be used is expressed in binary, it becomes "001 1101 0100 1100", as shown in FIG. 10(b). , the least significant bit "0" of the lower 8 bits is arranged at the 8th bit of the memory space address 9001H, and the remaining 7 bits of the lower 8 bits "0100" are arranged at the next memory space address 9002H. 110" is arranged, the least significant bit "1" of the upper 7 bits is arranged at the 8th bit of the memory space address 9002H, and the remaining upper 7 bits are arranged at the next memory space address 9003H. 6 bits "001 110" are allocated.

Next, the third variable time data corresponding to 50 seconds is 30D4H, and the 15-bit data to be used is expressed in binary notation as "011 0000 1101 0100", as shown in FIG. 10(b). , the 8th and 7th bits of the memory space address 9003H are the lower 2 bits "00" of the lower 8 bits, and the remaining 6 bits of the lower 8 bits are arranged at the next memory space address 9004H "1101 01" is allocated to the memory space address 9004H, the lower 2 bits of the upper 7 bits are allocated to the 8th and 7th bits of the memory space address 9004H, and "00" is allocated to the next memory space address 9005H. "011 00", which is the remaining 5 bits of the high-order 7 bits, is arranged in the .

Next, the fourth fluctuation time data corresponding to 120 seconds is 7530H, and the 15-bit data to be used is expressed in binary notation as "111 0101 0011 0000", as shown in FIG. 10(b). , the lower 3 bits "000" of the lower 8 bits are arranged at the 8th to 6th bits of the memory space address 9005H, and the remaining 5 bits of the lower 8 bits are arranged at the next memory space address 9006H. "0011 0" is arranged, and "101", which is the lower 3 bits of the upper 7 bits, is arranged in the 8th to 6th bits of the memory space address 9006H, and the next memory space address 9007H is arranged. "111 0", which is the remaining 4 bits of the high-order 7 bits, is arranged in .

Thus, by arranging the data across consecutive address addresses and arranging the data closely, the 8th to 5th bits of the memory space address 9007H become a free area. As a result, the data capacity can be reduced.

By the way, in arranging the data as shown in FIG. 10(b), for example, a program as shown in FIG. 11(a) is used. This program will be described below. This program is stored in the normal program area 600ba of the main control ROM 600b shown in FIG. 9(b).

As shown in FIG. 11(a), first, the top memory space address 9000H of the normal data area 600bc (see FIG. 9(b)) for data allocation is defined (ORG 9000H), and the defined label is D_HEDOUTTIME.

Next, the storage size is declared to be 15 bits (START EQU SIZE {15}), data 09C4H corresponding to the first variation time of 10 seconds, data 1D4CH corresponding to the second variation time of 30 seconds, and 50 seconds Write data 30D4H corresponding to the third variation time of , and data 7530H corresponding to the fourth variation time of 120 seconds, and declare that the data to be stored is 15 bits (END EQU SIZE) . As a result, when the program is assembled to create ROM data, the data described in the program is stored in the normal data area 600bc (see FIG. 9(b)) as shown in FIG. 10(b). It will continue.

Thus, the data arrangement as shown in FIG. 10(b) is achieved by setting the data arrangement in such a manner that the size to be stored is specified by the program. Although the data of 09C4H, 1D4CH, 30D4H, and 7530H are described in 16-bit format, since the storage size is declared to be 15 bits, when the program is assembled and ROM data is created, , as shown in FIG. 10(b), 15-bit data is stored starting from address 9000H.

On the other hand, to obtain the data stored in the normal data area 600bc (see FIG. 9(b)) of the main control ROM 600b, for example, a program as shown in FIG. 11(b) is used. This program will be described below. This program is stored in the normal program area 600ba of the main control ROM 600b shown in FIG. 9(b).

First, as a process before the processing of this program is started, a special symbol variation pattern (special symbol variation time) lottery is performed by the main control CPU 600a, and as a result of this lottery, the fourth variation time of 120 seconds. It is assumed that a variation pattern is selected and "04H" indicating the number of the selected variation pattern is stored in W_HENDOUNo shown in FIG. 11(b).

As shown in FIG. 11(b), first, the selected variation pattern number (“04H”) is acquired from W_HENDOUNo in which the selected variation pattern number (“04H”) is stored (LD A, (W_HENDOUNo)-1).

Next, the number (“03H”) decremented (-1) from the obtained variation pattern number is multiplied by 15 to calculate the offset value (MUL A, 15).

The offset value calculated above is then incremented (+1) (INC A) to match the bit position to be called.

Next, set the 15-bit data from the address obtained by adding the offset value calculated above to the first address (D_HENDOUTTIME (9000H) shown in FIG. 11(a)) where the fluctuation time is stored in the HL register. (LD(15) HL, D_HENDOUTTIME, A). As a result, the main control CPU 600a, shown in FIG. The data (111 0101 0011 0000) stored up to the 4th bit of address 9007H is set in the HL register. Thus, the fourth variable time data corresponding to 120 seconds is obtained from the normal data area 600bc (see FIG. 9B) of the main control ROM 600b. The internal registers (A register, HL register, etc.) of the main control CPU 600a are configured in 1-byte units. Therefore, the main control CPU 600a performs processing in 1-byte units according to the internal registers (A register, HL register, etc.) of the main control CPU 600a on the program, so 15-bit data (111 0101 0011 0000), 0 is added to the most significant bit, and 16-bit data (0111 0101 0011 0000) is set in the 2-byte HL register. Therefore, the program can perform processing without worrying that the read data size is 15 bits.

By the way, in the present embodiment, only the normal data area 600bc has been described as an example, but of course, the same data arrangement is possible even in the measurement data area 600bg. The normal data area 600bc and the measurement data area 600bg may be composed only of the above-described data arrangement area, or may be divided into the above-described data arrangement area and the conventional data arrangement area. You may configure it. In this way, a program can be created in accordance with the situation, thereby enabling optimal program processing.

In addition, in this embodiment, the data arrangement of the variation time data of the special symbol has been described as an example, but it is not limited to this, the distribution value of the variation pattern, the distribution table data of the selected variation pattern number, the jackpot It can be applied to any data such as the sorting value of the type lottery, sorting table data, and other set value data related to big hit control.

On the other hand, in the present embodiment, a data size of 15 bits is defined, that is, an example of defining one data size is shown, but it is also possible to define different bit sizes for a plurality of data. . This point will be described in detail with reference to FIG. 12, taking as an example a program for defining the judgment value of the variation pattern random number and the number data of the variation pattern selected at that time.

As shown in FIG. 12, the top memory space address 9100H of the normal data area 600bc (see FIG. 9B) for the data arrangement is defined (ORG 9100H), and the defined label is D_HEDOUHANTEI.

Next, a declaration (START EQU SIZE {14, 4}) to set the storage size to 14 bits and 4 bits is made. Then, when the variation pattern random number is 0 to 255 (= 0100H-1), "0100H, 01H" indicating that the variation pattern number 01H is selected is described, and the variation pattern random number is 256 to 511 (= 0200H-1 ), "0200H, 02H" indicating that the variation pattern number 02H is selected, and when the variation pattern random number is 512 to 4999 (= 1388H-1), select the variation pattern number 04H If the variation pattern random number is 5000 to 10000 (= 2710H-1), describe "2710H, 08H" indicating that the variation pattern number 08H is selected, and store the size Declare that the data for 14 bits and 4 bits is up to here (END EQU SIZE). As a result, the main control CPU 600a stores 14-bit and 4-bit data in order from memory space address 9100H in the normal data area 600bc (see FIG. 9B). Although the data of 0100H, 0200H, 1388H, and 2710H are described in 16-bit format, and the data of 01H, 02H, 04H, and 08H are described in 8-bit format, the storage size is set to 14 bits and 4 bits. Since the declaration is made, the main control CPU 600a will store 14-bit data and 4-bit data starting from address 9100H.

Thus, in this way, different bit sizes can be defined for a plurality of data.

<Description of Counter Update Processing>
Next, referring to FIG. 13, the process of updating random numbers such as normal symbols and special symbols used in the lottery, which will be described later, and of counters such as a common counter will be described.

Conventionally, when a program updates a counter that circulates within a predetermined range, it has been necessary to create a program for resetting the counter to 0 when the predetermined range is exceeded. This point will be described in detail, taking as an example the counter program that updates in the range of 0 to 99 shown in FIG. 13(a).

As shown in FIG. 13(a), in the counter program labeled M_INCEX, first, the counter is updated based on the specified upper limit value, that is, the work value of W_COUNTER is set in the A register (LD A, ( W_COUNTER)).

Then, the value of the A register is incremented (+1) (INC A).

It is then compared to 100 (CP 100) and if greater than 100, the A register is set to 0 (XOR A).

On the other hand, it compares with 100 (CP 100) and if it does not exceed 100, it jumps to label XXX (JR C, XXX). Then, at this label XXX, the updated count value is stored in the W_COUNTER work (LD (W_COUNTER), A).

Thus, by repeating the above program, the count value is updated within the range of 0-99.

Thus, conventionally, when updating a counter that circulates from 0 to 99 in a program, it was necessary to create a program for processing to reset the counter to 0 when it exceeds 99 as described above.

However, in the above-described program, the comparison instruction must always be used for branch processing, and there is a problem that the processing load of the program and the reduction of the program capacity cannot be achieved.

Therefore, in the present embodiment, a counter program that can update a counter that circulates within a predetermined range without branching using a comparison instruction is constructed. This point will be described in detail, taking as an example the counter program that updates in the range of 0 to 63 shown in FIG. 13(b). This counter program is stored in the normal program area 600ba and the measurement program area 600be of the main control ROM 600b shown in FIG. 9(b).

As shown in FIG. 13(b), in the counter program labeled M_INCEX, first, the counter is updated based on the specified upper limit value, that is, the work value of W_COUNTER is set in the A register (LD A, ( W_COUNTER)).

Next, the value of the A register is incremented (+1) and the lower 6 bits are masked with "0011 1111" (AND A+, 0011 1111B).

Then, the updated count value is stored in the W_COUNTER work (LD (W_COUNTER), A).

Thus, by repeating the above program, the count value is updated within the range of 0-63.

Therefore, if the above program is used, even if the count value is incremented (+1) from 63 (=0011 1111) and becomes 64 (=0100 0000), the value after the addition is "0011 1111 (AND A+, 0011 1111B), the count value becomes 0 (=0000 0000). Therefore, by masking with "0011 1111" all the time, not only when the value changes from 63 to 64 as in the program described above, branch processing using a comparison instruction can be performed in the program as in the past. A counter that circulates within a predetermined range can be updated without provision. As a result, the processing load of the program can be reduced and the program capacity can be reduced.

In this embodiment, the total number is 64, that is, the total number is a power of 2. However, the program is not limited to this and can be applied to any count value. be. However, it is preferably used in a counter program that updates a count value whose total is a power of two. This is because mask processing is easy.

By the way, the counter program described above can also be used as a general-purpose module. This point will be specifically described with reference to FIGS.

As shown in FIG. 13(c), in the counter program labeled M_INCEX, first, the counter is updated based on the specified upper limit value, that is, the value of the HL register is set in the A register (LD A, (HL )).

Next, the value of the A register is incremented (+1) and masked with the value of the B register (AND A+, B).

Then, the updated count value is stored in the HL register (LD (HL), A).

Thus, the counter program labeled M_INCEX, which has been made into a general module as described above, sets the work value of W_COUNTER in the HL register (LD HL, W_COUNTER) as shown in FIG. is set in the B register and the counter program labeled M_INCEX is read out (CALL M_INCEX).

Thus, by using the above-described counter program as a general-purpose module, it becomes possible to use it when updating a plurality of count values.

<Description of call instruction>
Next, referring to FIG. 14, a call instruction relating to the subroutine table address that can be called by the CALL_S instruction stored in the vector table area 600bi of the main control ROM 600b shown in FIG. 9B will be described. do.

In this embodiment, as call instructions executable by the main control CPU 600a, a plurality of call instructions including CALL_S instruction, CALL_M instruction, CALL_L instruction, and CALL instruction are provided. This CALL_S instruction has the smallest program code data amount (for example, 1 byte) among the plurality of call instructions. The subroutine called by this CALL_S instruction is called using the storage number of the address data table stored in the vector table area 600bi of the main control ROM 600b shown in FIG. 9(b). As shown in FIG. 14(a), this address data table stores the start address data of subroutines called by the CALL_S instruction such as data set processing (DW M_DTSET) and command transmission processing (DW M_CMDOUT) in 2 bytes. ing. Note that this stored order is used as the storage number when called by the CALL_S instruction. As a result, the program can use the name of the subroutine declared in this address data table without being aware of the storage number.

Therefore, in order to call the processing stored in such address data table, the CALL_S instruction is used as shown in FIG. 14(b). More specifically, the program shown in FIG. 14(b) shows a part of the initialization process described later, and the function of creating a constant cycle pulse output provided inside the main control CPU 600a and A CTC (Counter Timer Circuit) setting table (D_CTCSET), which has a time measurement function, etc., is set in the HL register (LD HL, D_CTCSET), and data set processing (M_DTSET) is called with the CALL_S instruction. There is (CALL_SM_DTSET).

By the way, this CTC setting table stores the contents as shown in FIG. 14(c). That is, the normal RAM area 600ca of the main control RAM 600c shown in FIG. 9A is set in the first half (LOW W_CTC1 to 3), and the second half (001H, 010H, 080H) is set in the normal RAM area 600ca. An end code is stored (DB 0FFH) indicating the data to be read and finally indicating the end of the data set.

On the other hand, the data set processing is performed as shown in FIG. 14(d). Specifically, first, the HL register is shifted to the A register, and then the HL register is incremented (+1) (LD A, (HL+)).

The A register is then compared with 0FFH (CP 0FFH) to check for the end of the data set.

Next, the upper address of the normal RAM area 600ca is set in the D register (LD D, 00H).

Next, the lower address of the normal RAM area 600ca read from the CTC setting table (D_CTCSET shown in FIG. 14(c)) is set in the E register (LD E, A).

Next, the data value to be set from the CTC setting table (D_CTCSET shown in FIG. 14(c)) is read into the A register (LD A, (HL+)).

Next, data is set in the work address set in the DE register (LD (DE), A), and the process returns to the beginning of the data setting process (JRM_DTSET).

Thus, in this way, the data set processing called by the CALL_S instruction will be executed.

On the other hand, the program shown in FIG. 14(b), which shows a part of the initialization process to be described later, calls the data set process (M_DTSET) with the CALL_S instruction, and then displays the standby screen on the liquid crystal display device 41 (see FIG. 5). Set the standby screen display command (0BA01H) to the DE register (LD DE, 0BA01H).

Next, the command transmission processing (M_CMDOUT) is called with the CALL_S instruction (CALL_SM_CMDOUT). This command transmission process is performed as shown in FIG. 14(e).

in particular,
LD A, D
OUT (CMDPORT), A
and output the upper byte data of the command from the command port.

then
LD B, 1000
WAIT:
DJNZ WAIT
and waits for a while until the effect control CPU 900 receives the command data.

then
LD A,E
OUT (CMDPORT), A
and output the lower byte data of the command from the command port.

Thus, the command transmission process called by the CALL_S instruction is executed in this manner.

Thus, in this way, the CALL_S instruction will be used in the initialization process.

However, since the above program is only an example, the CALL_S instruction is used not only for initialization processing but also for timer interrupts, which will be described later. That is, the command transmission process is not limited to the initialization process, but command transmission can be performed in various situations such as when the number of start holding balls increases, when the special symbol starts to change, when the jackpot starts, when an error occurs, etc. executed. Therefore, the CALL_S instruction is also used for timer interrupts.

Therefore, as described in the above program, by making the highly versatile process a subroutine corresponding to the CALL_S instruction, an increase in the data amount of the program can be suppressed. Therefore, it is possible to reduce the processing load of the program and reduce the program capacity.

In addition, command transmission processing is executed in various situations such as when the number of start pending balls increases, when special symbols start to fluctuate, when a big hit starts, and when an error occurs. , CALL_S instructions are used in timer interrupt processing at a higher rate than in initialization processing to main loop processing that calls timer interrupt processing. Therefore, it is possible to further reduce the processing load of the program and reduce the program capacity.

By the way, among the plurality of call instructions, the CALL_M instruction is used when calling a subroutine within a predetermined address range. Specifically, it is used when calling each subroutine such as special design processing, normal design processing, timer management processing, etc., which are executed in the timer interrupt processing described later. Since the CALL_S instruction is used when calling a subroutine with high versatility, the CALL_M instruction is used for each subroutine executed in the timer interrupt process that is called only once. Note that the CALL_M instruction differs in the data amount of the program code depending on the address of the subroutine to be called (for example, 2 bytes to 3 bytes).

On the other hand, among the plurality of call instructions, the CALL_L instruction, when calling a subroutine, sets the program counter (the address of the program being executed) to the normal stack area 600cc of the main control RAM 600c shown in FIG. In addition to saving to the stack area 600cg, the value of the flag register is also saved to the normal stack area 600cc and the measurement stack area 600cg of the main control RAM 600c shown in FIG. 9(a). Therefore, the CALL_L instruction is used when a flag is held before calling a subroutine and the value of the flag changes within the subroutine. Note that this CALL_L instruction consists of, for example, 2 bytes.

On the other hand, among the plurality of call instructions, the CALL instruction is mainly stored in the measurement program area 600be of the main control ROM 600b shown in FIG. It is used when calling a program used for measuring the total number of game balls shot into the game area 40 including the number of winning balls and the number of non-winning balls. That is, when calling the address address of the program used for measuring the total number of game balls shot into the game area 40, including the number of winning balls and the number of non-winning balls, it cannot be read by other call instructions. Since there is a possibility that a subroutine is arranged at an address address, CALL instruction is used. It should be noted that the CALL_M command described above cannot call the program used when measuring the total number of game balls shot into the game area 40, including the number of winning balls and the number of non-winning balls. Since the CALL_M instruction described above cannot be called by setting the address of the subroutine in a 2-byte register such as the HL register, it is called by specifying the address directly. be. Therefore, the CALL instruction calls a program used to measure the total number of game balls shot into the game area 40, including the number of winning balls and the number of non-winning balls, because there is no limit to the address address of the subroutine to be called. be able to. Note that this CALL instruction consists of, for example, 4 bytes.

Here, an example of using the CALL_M instruction and the CALL instruction described above will be described using the program shown in FIG. 14(f) as an example. The program shown in FIG. 14(f) shows main loop processing which will be described later. A CALL command is used to call a winning ball winning number management process 1 (M_SHOUKYU1), which is a program used when measuring the total number of game balls shot into the game area 40, including the number of winning balls and the number of non-winning balls. Then (CALL M_SHOUKYU1), various random number update processing (M_RANSU), which is a program used during game processing such as lottery processing stored in the normal program area 600ba of the main control ROM 600b shown in FIG. 9B, is executed. The process of calling with the CALL_M instruction (CALL M_SHOUKYU1) and enabling interrupts (EI) is repeated.

Thus, in this way the CALL_M and CALL instructions are used.

As described above, among the plurality of call instructions, the subroutine called by the CALL_M instruction and the subroutine called by the CALL_S instruction are stored in the normal program area 600ba of the main control ROM 600b shown in FIG. 9(b). A subroutine called by the CALL instruction is stored in the measurement program area 600be of the main control ROM 600b shown in FIG. 9(b). However, by selectively using a plurality of call instructions according to the situation, it is possible to reduce the processing load of the program and reduce the program capacity.

<Description of LDB instruction>
15 to 18 and 20 to 22 for the LDB instruction used to acquire the data stored in the normal data area 600bc (see FIG. 9B) of the main control ROM 600b. will be explained.

First, the internal registers within the main control CPU 600a will be described with reference to FIG. As shown in FIG. 15, the internal registers in the main control CPU 600a include a general-purpose register 600a1 having register bank 0 and register bank 1, a PC register 600a2 functioning as a program counter, an SP register 600a3 functioning as a stack pointer, It consists of a TP register 600a4 functioning as a table pointer and a PSW register 600a5 functioning as a program status word. As shown in FIG. 15, the general-purpose registers 600a1 are composed of W register, A register, B register, C register, D register, E register, H register, and L register each composed of 8 bits in both register bank 0 and register bank 1. , and 16-bit IX and IY registers. The TP register 600a4 stores an address address (for example, address 9000) that serves as a reference for designating the data area. , 9000H.

Therefore, the LDB instruction will be executed using such an internal register. More specifically, when executing the LDB command, as shown in the program example of the special symbol variation pattern processing shown in FIG. ).4”. This program "LDB BC, (HL+).9" reads 10-bit data from the address address "95A4H" in the normal data area 600bc of the main control ROM 600b (see FIG. 9(b)). This program stores 10-bit data in the BC register. Then, the program "LDB E, (HL+).4" reads 5-bit data from the address address "95A5H" in the normal data area 600bc of the main control ROM 600b (see FIG. 9(b)). This program stores the 5-bit data in the E register.

The contents of this program will be described in more detail with reference to FIGS. 16 and 20 to 22. FIG. First, as shown in FIG. 20(a), the HL register is programmed with "LDT HL,_TPTADR" to store the address of the special symbol pattern group address table shown in FIG. 20(b). . Then, either the normal game state table or the probability variation state table is selected by the following program shown in FIG. 20(a).

That is, as shown in FIG. 20(a),
LD A, (IY+W_TCODE1)
CALL_S_DTSRCH
, and the CALL_S instruction calls the data search process shown in FIG. In the present embodiment, the table of "DWD_TPATBL_1" programmed with "DW D_TPATBL_1" indicating the normal gaming state is selected, and the address address of the special figure variation pattern group table 1 shown in FIG. 21 is stored in the HL register. is stored. Then, one of the tables shown in FIG. 21 is selected by the following program shown in FIG. 20(a).

That is, as shown in FIG. 20(a),
LD A, (IY+W_TPTOFF)
JR NZ,TPTMK_10
;
LD A, (IY+W_T1GONUM)
TPTMK_10:
CALL_S_DTSRCH
21 is selected by calling the data search process shown in FIG. 20(c) with the CALL_S instruction. In the present embodiment, a table of "D_PT_FH1" programmed with "DW (D_PT_FH1-09000H)*8+0" indicating that the number of pending balls to start is 0 is selected, and the HL register is stored in FIG. ) is stored in the variable allocation table H1. That is, in the HL register, as shown in FIG. 16A, 9000H is subtracted from the address of D_PT_FH1 and multiplied by 8 to store "05A4" in the upper 13 bits. Of the "DW (D_PT_FH1-09000H) * 8 + 0" indicating that the number of start pending balls is 0, "(D_PT_FH1-09000H) * 8" is stored in the upper 13 bits, and "05A4" is stored in the program. be.

On the other hand, the HL register stores 9+1 (= 10) Bit designation information indicating whether to acquire bit data is stored in the lower 3 bits. This bit designation information corresponds to "+0" in the program "DW (D_PT_FH1-09000H)*8+0". That is, in the case of "+0", data is obtained from the 0th bit, in the case of "+1", data is obtained from the 1st bit, and in the case of "+2", data is obtained from the 2nd bit. will be done. Thus, the HL register stores the value "2D20" as shown in FIG. 16(a).

Thus, when the LDB instruction is executed for the HL register storing such data, the main control CPU 600a divides the value of the HL register by 8, as shown in FIG. 16(a). As a result, the value of "2D20" becomes "05A4". Then, the main control CPU 600a adds the reference address address 9000H for designating the data area stored in the TP register 600a4 (see FIG. 15) and the value "05A4" obtained by dividing by 8, and the main control CPU 600a The address of "95A4H" in the normal data area 600bc (see FIG. 9B) of the ROM 600b is calculated. Subsequently, since the bit designation information is "0", the main control CPU 600a, as shown in FIG. "0001010001" (data to be read is surrounded by a square in the drawing) is obtained (read).

Next, as shown in FIG. 20(a), following the program of "LDB BC, (HL+).9", when "LDB E, (HL+).4" is programmed, the main control CPU 600a As shown in FIG. 16(b), the value of "2D20" stored in the HL register is added to the value of 9+1 (=10) specified by the program "LDB BC, (HL+).9". , “2D2A”. As a result, the HL register stores "05A5" in the upper 13 bits and bit designation information for acquiring data from the second bit in the lower 3 bits.

Next, the main control CPU 600a divides the value of the HL register by 8, as shown in FIG. 16(b). As a result, the value of "2D2A" becomes "05A5". Subsequently, the main control CPU 600a adds the reference address address 9000H for designating the data area stored in the TP register 600a4 (see FIG. 15) and the value "05A5" obtained by dividing by 8. The address address of "95A5H" in the normal data area 600bc (see FIG. 9B) of the control ROM 600b is calculated. Therefore, since the bit designation information is "2", the main control CPU 600a, as shown in FIG. LDB E, (HL+).4" is programmed, so 4+1 (=5) bits of data "10000" (in the figure, the data to be read is enclosed in ).

Thus, as shown in FIG. 22(a), if the acquired value is 0 to 552, "001" is selected as the variation pattern command, If "002" is selected as the command, and if 783-997 (552+230+215), "004" is selected as the variation pattern command, and if 997-1000 (552+230+215+3), "005" is selected as the variation pattern command. will be selected. In this embodiment, since the number is 0 to 552, "001" is selected as the variation pattern command.

In addition, the process of acquiring the variation pattern command described above is shown in FIG.
LD WA, (IY+W_TPRBF0)
TPTMK_20:
LDB BC, (HL+).9
LDB E, (HL+).4
SUB WA, BC
JR NC, TPTMK_20
It will be executed by a program called

Thus, as shown in FIG. 16, the data obtained by subtracting the reference address address for designating the data area stored in the TP register 600a4 (see FIG. 15) in the HL register, and the bit designation information. , can be stored in the HL register, so that the program capacity can be reduced and the data capacity of the ROM can be reduced.

In addition, by programming "DW (D_PT_FH1-09000H)*8+0" and "0" as bit designation information, the possibility of designating the wrong bit can be reduced, thereby improving debugging accuracy. can be improved.

On the other hand, like the program "DW (D_PT_FH1-09000H)*8+0" shown in FIG. 21, to specify the data area stored in the TP register 600a4 (see FIG. 15) from the address address of D_PT_FH1 to the HL register. By storing the address address obtained by subtracting the reference address address 9000H, it is possible to reduce the capacity of the HL register. As a result, as shown in FIG. 16, two pieces of data can be stored in the HL register, thereby reducing the program capacity and reducing the data capacity of the ROM.

In the present embodiment, an example in which the variable distribution table H1 is selected is shown, but the table of "D_PT_FB1" programmed with "DW (D_PT_FB1-09000H)*8+0" indicating 5 rounds of the normal game is selected. If so, the fluctuation distribution table B1 shown in FIG. 22(b) will be selected. Further, since the process of acquiring the variation pattern command at this time is also the same as the process described above, the description thereof will be omitted.

<Explanation of modification of LDB instruction>
By the way, in the present embodiment, an example in which the LDB instructions are executed continuously has been shown, but the LDB instructions can be executed like the program shown in FIG. 17 without being limited to this.

That is, the program shown in FIG. 17(a) is a program for selecting a big winning opening pattern according to the number of rounds of the jackpot. ) is stored in the HL register. Specifically, as shown in FIG. 18(a), by multiplying the value of the address address "0352H" (see FIG. 17(b)) of _TDPTSEL1 by 8, "0352H" is added to the upper 13 bits of the HL register. Stored.

Then, in storing the bit designation information in the lower 3 bits of the HL register, the following processing is performed. That is, as shown in FIG. 17(a), by programming "LD A, (W_VCNT)", the value of W_VCNT indicating the number of rounds of the jackpot is stored in the A register. Next, by programming "MUL A.2", bit designation information is generated, and by programming "LD HL, (HL+A)", the generated bit designation information is stored in the lower 3 bits of the HL register. It will be done. In addition, in FIG. 18A, since the value of W_VCNT is "0", "0" is stored as the bit designation information.

Thus, when the LDB instruction "LDB A, (HL).1" is executed for the HL register storing such data, the main control CPU 600a changes the HL Divide the value in the register by 8. As a result, the value of "1A90" becomes "0352". Then, the main control CPU 600a adds the reference address address 9000H for specifying the data area stored in the TP register 600a4 (see FIG. 15) and the value "0352" obtained by dividing by 8, The address address of "9352H" in the normal data area 600bc (see FIG. 9B) of the ROM 600b is calculated. Subsequently, since the bit designation information is "0", the main control CPU 600a, as shown in FIG. "10" (data to be read is enclosed in a square in the drawing) is obtained (read).

Next, when the value of W_VCNT becomes "1" and "2" is stored as bit designation information, the HL register stores "010" in the lower 3 bits of the HL register as shown in FIG. 18(b). Value is stored. As a result, the value "1A90" is stored in the HL register.

Thus, when the LDB instruction "LDB A, (HL).1" is executed for the HL register storing such data, the main control CPU 600a changes the HL Divide the value in the register by 8. As a result, the value of "1A92" becomes "0352". Then, the main control CPU 600a adds the reference address address 9000H for specifying the data area stored in the TP register 600a4 (see FIG. 15) and the value "0352" obtained by dividing by 8, The address address of "9352H" in the normal data area 600bc (see FIG. 9B) of the ROM 600b is calculated. Subsequently, since the bit designation information is "2", the main control CPU 600a, as shown in FIG. "00" (data to be read is enclosed in a square in the drawing) is obtained (read).

Thus, if the bit designation information is generated by the program, the LDB instruction can be executed without executing the LDB instruction continuously. However, by doing so, it becomes possible to use it for various programs, thereby further reducing the program capacity and further reducing the data capacity of the ROM.

<Explanation of LDT instruction>
Next, the LDT instruction used to acquire the data stored in the normal data area 600bc (see FIG. 9B) of the main control ROM 600b will be described with reference to FIGS. 19 to 20. .

When executing the LDT command, as shown in the program example of the special symbol variation pattern process shown in FIG. 20(a), "LDT HL, _TPTADR" is programmed. This "LDT HL, _TPTADR" program is a program for storing the address address "954E" of the special figure variation pattern group address table shown in FIG. 20(b) in the HL register.

The contents of this program will be described in more detail with reference to FIG. When the LDT instruction is executed to store the address of "954E" in the HL register, the main control CPU 600a stores "054E" in the m register. Then, the main control CPU 600a adds the stored value "054E" and the reference address address 9000H for designating the data area stored in the TP register 600a4 (see FIG. 15), thereby obtaining HL "954E" is stored in the register.

Thus, by doing so, the program capacity can be reduced, and the data capacity of the ROM can be reduced.

Conventionally, an LD instruction was used to obtain such an address. This LD instruction has an instruction length of 4 bits and an address address to be obtained is at least 2 bytes. Therefore, when the LD instruction is used, 3 bytes are used as the program capacity.

However, when the LDT instruction is used, address address 9000H is used as a reference for specifying the data area stored in TP register 600a4 (see FIG. 15), so address specification is limited to 12 bits (in m register). (See stored "54E"). Therefore, since the instruction length of the LDT instruction is 4 bits, the program capacity can be reduced to 2 bytes, which is 16 bits in total.

Therefore, by using the LDT instruction, it is possible to reduce the program capacity by 1 byte compared to the conventional one. Therefore, it is possible to reduce the data capacity of the ROM.

By the way, in this embodiment, an example of executing the LDT instruction in storing the address in the HL register has been shown, but the LD instruction may be executed in some cases. That is, as shown in FIG. 20(c), "LD HL, (HL)" is programmed in the data search process, which is a subroutine. This is a program that stores the value stored in the HL register in the HL register. In this case, since the instruction stores a value from register to register, the program capacity, including the instruction length, is 2 bytes. will be enough. Therefore, in such a case, the LD instruction can be used without using the LDT instruction. Thus, by selectively using instructions according to the content of processing, it is possible to prevent unnecessary processing from being executed, thereby improving the processing speed.

<Explanation about TP register>
Next, the TP register 600a4 (see FIG. 15) used in the LDB and LDT instructions will be described with reference to FIGS. 23-25. This TP register 600a4 stores an address address 9000H as a reference for designating the data area. Therefore, as shown in FIG. 9(b), the address address of the measurement data area 600bg (see FIG. 9(b)) of the main control ROM 600b straddles the address 9000H and starts from "A200H". When acquiring data stored in the measurement data area 600bg (see FIG. 9B), the TP register 600a4 cannot be used. Therefore, the LDB and LDT instructions described above cannot be used.

Thus, when measuring the total number of game balls shot into the game area 40 including the number of winning balls and the number of non-winning balls stored in the measurement program area 600be of the main control ROM 600b shown in FIG. When using the program to be used, it is necessary to temporarily save the unused TP register 600a4.

For this saving, as shown in FIG. 23(a), the general-purpose register 600a1, the SP register 600a3, and the PSW register 600a5 are saved by using the instruction "PUSH ALL". At this time, since the TP register 600a4 cannot be saved by the instruction "PUSH ALL", only the TP register 600a4 is saved by using the instruction "PUSH TP" as shown in FIG. 23(b). make it When restoring the saved registers, the general-purpose register 600a1, the SP register 600a3, and the PSW register 600a5 can be restored by using the instruction "POP ALL". POP TP" can be used to restore only the saved TP register 600a4.

Thus, such a program can be used as follows. FIG. 24 is a program showing an example of timer interrupt processing, and FIG. 25 is a program showing an example of a main loop.

As shown in FIG. 24, the total number of game balls shot into the game area 40 including the number of winning balls and the number of non-winning balls stored in the measurement program area 600be of the main control ROM 600b shown in FIG. In FIG. 24, the processing by the program used for measurement is programmed as "CALL O_EXAREA2", and the processing for saving the register is programmed as follows.

PUSH ALL
PUSH TP
CALL O_EXAREA2

Thus, by "PUSH ALL", as shown in FIG. 23(a), the general-purpose register 600a1, SP register 600a3, and PSW register 600a5 are moved to the measurement stack area 600cg (see FIG. 9(a)) of the main control RAM 600c. ), and by "PUSH TP", the TP register 600a4 is saved in the measurement stack area 600cg (see FIG. 9A) of the main control RAM 600c as shown in FIG. 23B.

On the other hand, in FIG. 24, the processing for restoring the saved registers is programmed as follows.

CALL O_EXAREA2
POP TP
POP ALL

Thus, ``POP TP'' restores the saved TP register 600a4 as shown in FIG. 600a1, SP register 600a3, and PSW register 600a5 are restored.

Also, as shown in FIG. 25, the total number of game balls shot into the game area 40 including the number of winning balls and the number of non-winning balls stored in the measurement program area 600be of the main control ROM 600b shown in FIG. In FIG. 25, the following programming is performed as the processing for saving the register when calling the program "CALL O_EXAREA1" for the processing by the program used when measuring .

PUSH ALL
PUSH TP
CALL O_EXAREA1

Thus, by "PUSH ALL", as shown in FIG. 23(a), the general-purpose register 600a1, SP register 600a3, and PSW register 600a5 are moved to the measurement stack area 600cg (see FIG. 9(a)) of the main control RAM 600c. ), and by "PUSH TP", the TP register 600a4 is saved in the measurement stack area 600cg (see FIG. 9A) of the main control RAM 600c as shown in FIG. 23B.

On the other hand, in FIG. 25, the processing for restoring the saved registers is programmed as follows.

CALL O_EXAREA1
POP TP
POP ALL

Thus, ``POP TP'' restores the saved TP register 600a4 as shown in FIG. 600a1, SP register 600a3, and PSW register 600a5 are restored.

Thus, by performing such processing, the number of winning balls and the number of non-winning balls stored in the measurement program area 600be of the main control ROM 600b shown in FIG. When using a program that is used to measure the total number of spheres, it is possible to temporarily save the unused TP register 600a4.

In the timer interrupt processing shown in FIG. 24, "LD TP, 09000H" is first programmed to store 9000H in the TP register 600a4, but this program need not be written. This is because the TP register 600a4 is initialized to 9000H, which is the reference address for designating the data area, at reset. However, if described, even if some kind of bug occurs, 9000H will be stored in the TP register 600a4 each time a timer interrupt occurs, which is preferable. If it is not necessary to store frequently, 9000H may be stored in the TP register 600a4 in the initial processing when the power is turned on.

<Explanation of other programs>
By the way, in the special symbol variation pattern processing program shown in FIG. 20(a), the special symbol variation pattern data processing is called by programming "CALL_MM_TPTDTMK". It is programmed as shown in FIG. 26(a).

This program first
LD C, 000H
;
CP (IY+W_TPTOFF), 005H
JRS T,TPTDTMK_10
INC C
By programming , the value of win or lose is stored in the C register.

then
TPTDTMK_10:
LDT HL,_TMVTBL;
LD B, 003H
MUL B,C
ADDHL,BC
LD D, (HL+)
By programming , the value of the C register is confirmed, and a variation pattern command for winning or losing is generated.

More specifically, by programming "LDT HL,_TMVTBL", the special figure variation parameter specification table shown in FIG. 26(b) is read. In the case of a loss, "A0H" out of "DB 0A0H" shown in FIG. "A1H" of "DB 0A1H" shown in b) is stored in the D register. The lower byte of the variation pattern command is the value selected as the variation pattern command stored in the E register in the variation pattern command acquisition process shown in FIG. ).

Then, when the value is stored in the DE register,
LD HL, (HL);
PUSH ALL;
CALL_S_CMDOUT;
POP ALL
By programming, the variation pattern command stored in the DE register is transmitted to the effect control CPU 900 (see FIG. 7).

If the lower byte of the variation pattern command is 00H, it is unknown whether or not a bug has occurred due to noise or the like. Therefore, as shown in FIG. I am trying to However, as the offset in the main control main process, 0 is used, so the variation pattern command stored in the DE register is sent to the effect control CPU 900 (see FIG. 7), and then shown in FIG. Thus, "DEC E" is programmed to decrement the E register.

Also, when transmitting the variation pattern command stored in the DE register to the effect control CPU 900 (see FIG. 7), by programming "CALL_S _CMDOUT", by calling the subroutine of "_CMDOUT", Stored in the DE register The variation pattern command is sent to the effect control CPU 900 (see FIG. 7), but at this time, there is a possibility that the value of the register will be rewritten in the process of the subroutine.

Therefore, in this embodiment, "PUSH ALL" is programmed before "CALL_S_CMDOUT" is programmed, and as shown in FIG. , is saved in the normal stack area 600cc (see FIG. 9(a)) of the main control RAM 600c, and after programming "CALL_S_CMDOUT", "POP ALL" is programmed as shown in FIG. 23(a). Then, the saved general-purpose register 600a1, SP register 600a3, and PSW register 600a5 are restored.

At this time, the reason why the TP register 600a4 is not saved is that the TP register 600a4 is used when acquiring the data stored in the normal data area 600bc (see FIG. 9B) of the main control ROM 600b. is. That is, it is used when measuring the total number of game balls shot into the game area 40 including the number of winning balls and the number of non-winning balls stored in the measurement program area 600be of the main control ROM 600b shown in FIG. 9(b). This is because it is not a process that uses a program to be processed.

However, if the process does not use the program used to measure the total number of game balls shot into the game area 40, including the number of winning balls and the number of non-winning balls, the process of saving the TP register 600a4 is not performed. By doing so, it is not necessary to execute useless processing, and the processing speed can be improved.

Then, after transmitting the variation pattern command stored in the DE register to the effect control CPU 900 (see FIG. 7),
DEC E
ADDHL,E
ADDHL,E
LD HL, (HL)
CALL_S_SVTMR
By programming, the variable time used in the main control is set. In addition, as shown in FIG. 26(b), in the case of losing, by programming "DW D_TMTMR1", the special figure fluctuation time table 1 shown in FIG. By programming "DWD_TMTMR2", the special figure fluctuation time table 2 shown in FIG. 27(b) will be selected.

Thus, after transmitting the variation pattern command stored in the DE register to the effect control CPU 900 (see FIG. 7), by setting the variation time used in the main control, the efficiency of the process is improved. Therefore, it is possible to improve the processing speed.

<Explanation of the program>
Here, the program used during game processing such as lottery processing stored in the normal program area 600ba of the main control ROM 600b shown in FIG. An outline of a program used for measuring the total number of game balls shot into the game area 40 including the number of winning balls and the number of non-winning balls will be described with reference to FIGS. 28 to 37. FIG.

<Description of main processing>
First, when the pachinko game machine 1 is powered on, a power-on signal is sent to the effect that the DC voltage generated by the voltage generator 1300 of the power supply board 130 (see FIG. 7) is supplied to each control board. , in response to the signal, the main control CPU 600a (see FIG. 7) reads the program stored in the normal program area 600ba of the main control ROM 600b shown in FIG. I do. At this time, the main control CPU 600a first sets itself to an interrupt disabled state (step S1).

Next, the main control CPU 600a performs initial settings such as register values in the main control CPU 600a (step S2).

Subsequently, the main control CPU 600a sets the activation waiting time of the sub-control board 80 (step S3), decrements (-1) the set waiting time (step S4), and clears the watchdog timer (WDT) not shown. (step S5).

Next, the main control CPU 600a confirms whether or not the set waiting time has become "0" (step S6), and if it has not become "0" (step S6: ≠ 0), returns to the process of step S4. , "0" (step S6:=0), the process proceeds to step S7.

Next, the main control CPU 600a acquires the voltage abnormality signal ALARM (see FIG. 7) output from the power supply board 130 (voltage monitoring unit 1310) (see FIG. 7) twice, and are stored in an internal register (not shown) of the main control CPU 600a, and the level of the voltage abnormality signal ALARM is confirmed (step S7). If the level of the voltage abnormality signal ALARM is "L" level (step S8: YES), the process returns to step S7. If the voltage abnormality signal ALARM is at "H" level (step S8: NO), The process proceeds to step S9. That is, the main control CPU 600a repeats the same processing until the abnormal voltage signal ALARM changes to the normal level (that is, "H" level) (steps S7-S8). By acquiring the abnormal voltage signal ALARM twice in this manner, an accurate signal can be read.

Next, the main control CPU 600a clears a watchdog timer (WDT) (not shown) (step S9), and confirms whether or not a signal (power-on signal) indicating that power has been turned on from the payout control board 70 ( step S10). If the power-on signal has not come (step S10: OFF), the process returns to step S9, and if the power-on signal has come (step S10: ON), a constant period A CTC (Counter Timer Circuit) having a function of generating a pulse output, a function of time measurement, etc. is set. That is, the main control CPU 600a sets the time constant register of the CTC so that a timer interrupt is periodically applied every 4 ms (step S11).

It should be noted that this CTC setting process sets the CTC setting table (D_CTCSET) in the HL register (LD HL, D_CTCSET) shown in FIG. It is processed by the program that is doing

<Main processing: Description of setting display device>
Next, the main control CPU 600a confirms whether or not a dedicated key is inserted into the setting key switch 640 shown in FIG. 7 and turned on (step S12). If the setting key switch 640 is turned on (step S12: YES), the main control CPU 600a checks whether the upper opening/closing door 7 and the lower opening door 8 are open (step S12: YES), as shown in FIG. S13). If the upper opening/closing door 7 and the lower opening door 8 are open (step S13: YES), the main control CPU 600a stores the normal RAM area 600ca and the normal stack area 600cc of the main control RAM 600c shown in FIG. All are cleared (step S14). However, it is desirable that the RAM area storing data relating to setting values, which will be described later, be held without being cleared, considering that the setting values may be changed based on the previous setting values.

Next, the main control CPU 600a sets the setting changing flag to ON (step S15), and permits data writing to the main control RAM 600c (see FIG. 7) (step S16).

Next, the main control CPU 600a transmits to the effect control board 90 a processing command (effect control command DI_CMD) that causes the liquid crystal display device 41 to display that the setting is being changed (step S17), and the main control RAM 600c (FIG. 7). (see step S18). The processing command (effect control command DI_CMD) transmission processing for displaying that the setting is being changed is called by the CALL_S instruction and processed.

Next, the main control CPU 600a confirms whether or not the obtained setting value indicates any value from "1" to "6" (step S19). If the acquired setting value does not indicate any value of "1" to "6" (step S19: NO), the acquired setting value is set to "1" (step S20). On the other hand, if the acquired setting value indicates any value from "1" to "6" (step S19: YES), the process proceeds to step S21.

Next, the main control CPU 600a performs processing for displaying the setting values on the setting display device 620 (see FIGS. 7 and 8B) (step S21). As a result, one of the values "1" to "6" is displayed on the setting display device 620. FIG.

Next, the main control CPU 600a executes input management processing during main processing (step S22).

<Description of input management processing during main processing>
This input management processing during main processing will be specifically described with reference to FIG. As shown in FIG. 29, the main control CPU 600a first clears a watchdog timer (WDT) (not shown) (step S50).

Next, the main control CPU 600a sets a predetermined value in a register in the main control CPU 600a so that a wait of 4 ms is applied, and counts down (step S51). In this process, when confirming a change in the level data of the setting change switch 650 (see FIG. 7), by waiting at least 4 ms after the previous acquisition of the switch level, it is possible to prevent the level data from being changed due to irregularities such as noise. This is processing for confirming that there is no change.

Next, the main control CPU 600a acquires the current switch level data from the input port (switch port) of the main control CPU 600a that can confirm the change in the switch level of the setting change switch 650 (see FIG. 7) (step S52). .

Next, the main control CPU 600a creates switch edge data from the previous and current switch level data (step 53). The main control CPU 600a stores the created edge data in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c.

Next, the main control CPU 600a executes the voltage monitoring process (step S54) and finishes the input management process during the main process. This voltage monitoring process determines the level of the abnormal voltage signal ALARM output from the power supply substrate 130 (see FIG. 7), and if the abnormal voltage signal ALARM is at the "L" level (abnormal level), The purpose is not backup processing, such as clearing the port and transmission of a power interruption command (effect control command DI_CMD) to the production control board 90, but the purpose is to execute power interruption processing during normal games. This power interruption command (effect control command DI_CMD) transmission process is called by a CALL_S command and processed.

Thus, by executing such an input management process during main processing, the main control CPU 600a may erroneously input data such as noise even though the setting has not been changed by the setting change switch 650 (see FIG. 7). is obtained and misidentified that the settings have been changed, preventing erroneous setting changes.

<Main processing: Description of setting display device>
Next, the main control CPU 600a confirms the created edge data stored in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c, and changes the setting with the setting change switch 650 (see FIG. 7). It is checked whether or not the completion function is ON (step S23). If the setting change completion function is not turned on by the setting change switch 650 (see FIG. 7) (step S23: NO), the main control CPU 600a turns on the setting change function by the setting change switch 650 (see FIG. 7). is confirmed (step S24). If the setting change function is not turned ON by the setting change switch 650 (see FIG. 7) (step S24: NO), the main control CPU 600a returns to the process of step S22, and turns on the setting change switch 650 (see FIG. 7). If the setting change function is ON (step S24: YES), the main control CPU 600a increments (+1) the current set value (step S25) and returns to the process of step S19.

On the other hand, if the setting change completion function is turned on by the setting change switch 650 (see FIG. 7) (step S23: YES), the main control CPU 600a stores the current set value in the main control RAM 600c (see FIG. 7) ( (step S26), and the setting display device 620 (see FIGS. 7 and 8B) indicates that the set values have been determined. (step S27). As a result, the dot on the lower right side of the seven segments forming the setting display device 620 (see FIG. 8(b)) lights up, indicating that the setting has been finalized.

Next, the main control CPU 600a clears a watchdog timer (WDT) (not shown) (step S28).

Next, the main control CPU 600a confirms whether or not the setting key switch 640 shown in FIG. 7 is turned off (step S29). If it is not turned off (step S29: NO), the processing of steps S28 to S29 is repeated until it is turned off, and if it is turned off (step S29: YES), the setting value set in the effect control board 90 is indicated. A setting value command (effect control command DI_CMD) is transmitted (step S30), a setting changing flag is set to OFF (step S31), and the process proceeds to step S40. This set value command (effect control command DI_CMD) transmission process is called by a CALL_S command and processed.

<Description of main processing>
On the other hand, if the setting key switch 640 (see FIG. 7) is OFF (step S12: NO) and the upper opening/closing door 7 and the lower opening door 8 are not opened as shown in FIG. : NO), the main control CPU 600a permits data writing to the main control RAM 600c (see FIG. 7) (step S32), and gives a processing command (effect A control command DI_CMD) is transmitted (step S33).

14(b), the standby screen display command (0BA01H) for displaying the standby screen on the liquid crystal display device 41 (see FIG. 5) is set in the DE register (see FIG. 5). LD DE, 0BA01H) and command transmission processing (M_CMDOUT) are processed by a program (CALL_SM_CMDOUT) that calls the command transmission processing (M_CMDOUT) with the CALL_S instruction.

Next, the main control CPU 600a confirms the contents of the backup flag BFL (step S34). The backup flag BFL is data indicating whether or not backup processing has been executed when a voltage drop due to a power failure or the like is detected in the voltage monitoring processing shown in FIG.

If the backup flag BFL is in the OFF state (step S34: OFF), it means that backup processing is not being executed when a voltage drop due to a power failure or the like is detected in the voltage monitoring processing shown in FIG. 30, which will be described later. The main control CPU 600a transmits a processing command (effect control command DI_CMD) indicating a RAM error to the effect control board 90 (step S35), and performs infinite loop processing. It should be noted that the processing command (effect control command DI_CMD) transmission processing indicating that there is a RAM error is called by the CALL_S instruction and processed.

On the other hand, if the backup flag BFL is ON (step S34: ON), it means that backup processing is being executed when a voltage drop due to a power failure or the like is detected in the voltage monitoring processing shown in FIG. 30, which will be described later. Therefore, the main control CPU 600a performs checksum calculation for calculating the checksum value. After the checksum value is calculated, the main control CPU 600a performs a process of comparing the calculation result with the stored value of the SUM address in the main control RAM 600c (step S36). Note that the checksum operation is an 8-bit addition operation for the main control RAM 600c, and the stored operation result is stored in the power supply board 130 shown in FIG. 7 together with other data stored in the main control RAM 600c. maintained by a backup power source generated by

If the stored value of the SUM address and the calculated checksum value do not match (step S36: NO), the main control CPU 600a gives the effect control board 90 a processing command (effect control command DI_CMD) indicating a RAM error. is transmitted (step S35), and infinite loop processing is performed. As described above, the processing command (effect control command DI_CMD) transmission processing indicating that there is a RAM error is called by the CALL_S instruction and processed.

On the other hand, if they match (step S36: YES), the main control CPU 600a confirms the contents of the RAM clear switch 630 (see FIG. 7) (step S37). If the edge data of the RAM clear switch 630 is ON (step S37: ON), the main control CPU 600a determines that the RAM clear switch 630 has been pressed, ), the measurement stack area 600cg (see FIG. 9A) is not cleared, the normal RAM area 600ca of the main control RAM 600c (see FIG. 9A), the normal stack area 600cc (see FIG. 9A) ) is cleared (step S39), and the process proceeds to step S40.

Thus, as described above, when the backup flag is OFF (step S34: OFF) or when the checksum values do not match (step S36: NO), the RAM clear switch 630 (see FIG. 7) is turned ON. However, the normal RAM area 600ca and the normal stack area 600cc (see FIG. 9A) of the main control RAM 600c are not cleared. This is because when there is an abnormality in the backup process or when the checksum value is abnormal, there is a possibility that the setting value displayed on the setting display device 620 (see FIGS. 7 and 8B) is abnormal. Because it is expensive. Therefore, as shown in the present embodiment, after the processing of step S35, infinite loop processing is executed, the power is turned on again, and the game cannot be restarted unless the set value is changed. By doing so, it is possible to prevent a situation in which the player and the game hall (hall) are disadvantaged.

On the other hand, if the edge data of the RAM clear switch 630 is OFF (step S37: OFF), the main control CPU 600a determines that the RAM clear switch 630 is not pressed, and the data stored in the main control RAM 600c Based on this, a process of returning to the game operation at the time of power shutdown is performed (step S38).

Thus, after completing the process of step S38 or step S39, the main control CPU 600a permits data writing to the main control RAM 600c (see FIG. 7) (step S40) and clears the watchdog timer (WDT) not shown. (step S41).

Next, the main control CPU 600a sets the firing control signal to ON and transmits it to the payout control board 70 (step S42). As a result, the payout control board 70 controls the launch control board 71 to start operating.

Next, the main control CPU 600a reads the program stored in the measurement program area 600be of the main control ROM 600b shown in FIG. A winning ball winning number management process 1 for calculating performance such as the total number of game balls shot into the game area 40 including the number of balls and the number of non-winning balls is performed (step S44). During this processing, as shown in FIG. 25, programs "PUSH ALL" and "PUSH TP" are executed, and as shown in FIG. is saved in the measurement stack area 600cg (see FIG. 9(a)) of the main control RAM 600c, and by "PUSH TP", the TP register 600a4 is stored in the main control RAM 600c for measurement as shown in FIG. It is saved in the stack area 600cg (see FIG. 9A). After the ball winning number management process 1 is performed, the programs "POP TP" and "POP ALL" are executed, and the saved TP register 600a4 is restored as shown in FIG. 23(a), the saved general-purpose register 600a1, SP register 600a3, and PSW register 600a5 are restored.

Next, the main control CPU 600a updates various random number counters based on the program stored in the normal program area 600ba of the main control ROM 600b shown in FIG. The permission state is restored (step S46), the process returns to step S43, and a loop process of repeating the processes of steps S43 to S46 is performed.

It should be noted that the process of step S43 to step S46, shown in FIG. 14 (f), after performing the interrupt prohibition process (DI), call the prize ball winning number management process 1 (M_SHOUKYU1) with a CALL instruction (CALL M_SHOUKYU1). , various random number updating processes (M_RANSU) are called with the CALL_M instruction (CALL M_SHOUKYU1), and interrupts are permitted (EI).

Thus, when the RAM clear switch 630 (see FIG. 7) is pressed, the measurement RAM area 600cb and the measurement stack area 600cg (see FIG. 9A) of the main control RAM 600c are not cleared. , the normal RAM area 600ca of the main control RAM 600c and the normal stack area 600cc (see FIG. 9(a)) are cleared so that the game area 40 including the measured number of prize balls and the number of non-winning balls is shot. It is possible to prevent a situation in which the total number of game balls or the like is erroneously cleared. In other words, even if the power supply is cut off due to the occurrence of some kind of abnormality, the total number of game balls shot into the game area 40 including the measured number of prize balls and the number of non-win prizes, etc., will be erroneously cleared even after the power is restored. Therefore, it is possible to generate accurate information displayed on the measurement display device 610 (see FIGS. 7 and 8(a)). can do.

<Description of timer interrupt processing>
Next, with reference to FIG. 30, a timer interrupt program that interrupts the above-described main processing and is started every 4 ms will be described. This program is to read and execute a program stored in the normal program area 600ba of the main control ROM 600b shown in FIG. 9(b).

When this timer interrupt occurs, save processing is executed to save the contents of the register group in the main control CPU 600a to the normal stack area 600cc (see FIG. 9A) of the main control RAM 600c (step S100), and then the voltage is monitored. Processing is executed (step S101). This voltage monitoring process determines the level of the abnormal voltage signal ALARM output from the power supply board 130 (see FIG. 7). Backup processing of stored data, that is, processing of calculating the checksum value of the data and storing the calculated checksum value as backup data in the main control RAM 600c is performed.

Next, when the voltage monitoring process (step S101) ends, the main control CPU 600a performs timer subtraction processing of various timers (normal symbol variation timer, normal symbol role timer, etc.) that manage the time of each game operation. (Step S102).

Next, the main control CPU 600a includes a special symbol 1 start switch 44a (see FIG. 7), a special symbol 2 start switch 45a (see FIG. 7), a normal symbol start switch 47a (see FIG. 7), Upper right general winning opening switch 48a1 (see FIG. 7), upper left general winning opening switch 48b1 (see FIG. 7), middle left general winning opening switch 48c1 (see FIG. 7), lower left general winning opening switch 48d1 (see FIG. 7), The ON/OFF signals of various switches including the outlet switch 49a (see FIG. 7) and the big winning switch 46c (see FIG. 7) are input, and the ON/OFF signal level, The rising state is stored (step S103).

Next, the main control CPU 600a performs random number management processing (step S104). Specifically, it carries out a process of updating random numbers such as normal symbols and special symbols used in the lottery. At this time, the counter programs shown in FIGS. 13(b) to 13(d) are executed.

Next, the main control CPU 600a performs error management processing (step S105). In the error management process, the supply of game balls is stopped, or the game balls are jammed, the special symbol 1 start switch 44a (see FIG. 7), the special symbol 2 start switch 45a (see FIG. 7), Normal pattern start opening switch 47a (see FIG. 7), upper right general winning opening switch 48a1 (see FIG. 7), upper left general winning opening switch 48b1 (see FIG. 7), middle left general winning opening switch 48c1 (see FIG. 7), lower left It is to determine whether there is an abnormality inside the device, such as disconnection of the general winning opening switch 48d1 (see FIG. 7), the out opening switch 49a (see FIG. 7), and the big winning opening switch 46c (see FIG. 7). be. In addition, when some error occurs, a command (effect control command DI_CMD) corresponding to the error is transmitted to the effect control board 90, and this command (effect control command DI_CMD) transmission process is called by CALL_S instruction. will be processed as

Next, the main control CPU 600a determines whether the set value of the probability of generating a special game state advantageous to the player stored in the main control RAM 600c (see FIG. 7) is within the range of "1" to "6". is confirmed (step S106). If the RAM error flag is set to ON (step S106: YES), the main control CPU 600a determines the probability of generating a special game state advantageous to the player stored in the main control RAM 600c (see FIG. 7). It determines that the set value is outside the range of "1" to "6", skips the process related to the design, and proceeds to the process of step S119. On the other hand, if the RAM error flag is set to OFF (step S106: NO), the main control CPU 600a generates a special game state advantageous to the player stored in the main control RAM 600c (see FIG. 7). It is determined that the set value of the probability is within the range of "1" to "6", and the process proceeds to step S107.

Next, the main control CPU 600a checks the setting changing flag (step S107). If the setting changing flag is set to ON (step S107: YES), the main control CPU 600a determines that it is an irregular state in which the setting value can only be changed when the power is turned on, and step S117. proceed to the processing of On the other hand, if the setting changing flag is set to OFF (step S107: NO), the main control CPU 600a determines that the set value of the probability of generating a special game state advantageous to the player is not being changed, and step The process proceeds to S108.

Next, the main control CPU 600a confirms the setting confirmation flag (step S108). If the setting confirmation flag is set to ON (step S108: YES), the main control CPU 600a determines that the set value of the probability of generating a special game state advantageous to the player is being confirmed, and in step S114 Proceed to processing. On the other hand, if the setting confirmation flag is set to OFF (step S108: NO), the main control CPU 600a determines that the set value of the probability of generating a special game state advantageous to the player is not being confirmed, and step S109. proceed to the processing of

Next, the main control CPU 600a executes prize ball management processing (step S109). This prize ball management process outputs a payout control command PAY_CMD for causing the payout control board 70 (see FIG. 7) to perform a payout operation.

Next, the main control CPU 600a executes normal symbol processing (step S110). In this normal design process, a winning lottery for normal symbols is executed, and based on the result of the lottery, the variation pattern of the normal symbols and the stop display state of the normal symbols are determined. The details of this processing will be described later.

Next, the main control CPU 600a executes normal electric accessory management processing (step S1111). In this normal electric auditors management process, a signal related to control of the normal electric auditors solenoid 45c (see FIG. 7) necessary for normal electric auditors open game generation is generated based on the lottery result of the normal symbol processing (step S110). It is a thing.

Next, the main control CPU 600a executes special symbol processing (step S112). In this special design process, a lottery for the special design is executed, and the variation pattern of the special design and the stop display mode of the special design are determined based on the result of the lottery. The details of this processing will be described later.

By the way, when executing the special symbol processing, the main control CPU 600a sets the probability of generating a special game state advantageous to the player, which is stored in the main control RAM 600c (see FIG. 7), regarding the lottery of special symbols. Based on the value, lottery of special symbols is performed. Therefore, the main control CPU 600a determines whether the set value of the probability of generating a special game state advantageous to the player stored in the main control RAM 600c (see FIG. 7) is within the range of "1" to "6". If it is out of range, the RAM error flag is set to ON.

Next, the main control CPU 600a executes a special electric accessary product management process (step S113). In this special electric accessary product management process, when the jackpot lottery result is "big hit" or "small hit", setting processing necessary for executing and controlling the winning game corresponding to the hit is mainly performed. be. At this time, a signal for controlling the special electric accessory solenoid 46b (see FIG. 7) is also generated. In addition, when the jackpot lottery result is "big hit" or "small hit", a command (effect control command DI_CMD) relating to it is transmitted to the effect control board 90 . This command (effect control command DI_CMD) transmission processing is called by a CALL_S instruction and processed.

Next, the main control CPU 600a performs a process of confirming the set value of the probability of generating a special game state advantageous to the player stored in the main control RAM 600c (see FIG. 7) (step S114).

Next, the main control CPU 600a reads the program stored in the measurement program area 600be of the main control ROM 600b shown in FIG. 9(b), and executes the winning ball winning number management process 2 (step S115). In this prize ball winning number management process 2, the process of displaying the value calculated in the prize ball winning number management process 1 of step S44 shown in FIG. It is something to do. During this processing, as shown in FIG. 24, programs "PUSH ALL" and "PUSH TP" are executed, and as shown in FIG. is saved in the measurement stack area 600cg (see FIG. 9(a)) of the main control RAM 600c, and by "PUSH TP", the TP register 600a4 is stored in the main control RAM 600c for measurement as shown in FIG. It is saved in the stack area 600cg (see FIG. 9A). After the ball winning number management process 2 is performed, the programs "POP TP" and "POP ALL" are executed, and the saved TP register 600a4 is restored as shown in FIG. 23(a), the saved general-purpose register 600a1, SP register 600a3, and PSW register 600a5 are restored.

By the way, as shown in FIG. 30, in the prize ball winning number management process 2, the RAM error (step S106 shown in FIG. 30) and the irregular state in which the set value is changed (step S107 shown in FIG. 30) It will not be processed. Incidentally, the winning ball winning number management process 2 is called by a CALL command and processed.

Next, the main control CPU 600a performs solenoid drive processing (step S116). At this time, the main control CPU 600a confirms the signal related to the control of the normal electric auditors product solenoid 45c (see FIG. 7) generated in the normal electric auditors product management process (step S111), and also confirms the special electric auditors product management process ( A signal relating to the control of the special electric accessory solenoid 46b (see FIG. 7) generated in step S113) is checked. Based on this signal, the operation/stop of the normal electric accessory solenoid 45c or the special electric accessory solenoid 46b is controlled to open or close the opening/closing member 45b (see FIG. 5), or open or close the big prize opening (not shown). The open/close door 46a (see FIG. 5) is operated so that the is opened or closed.

Next, the main control CPU 600a executes LED management processing (step S117). This LED management process generates output data to the special symbol display device 50 (see FIG. 5) or the normal symbol display device 51 (see FIG. 5) according to the progress of the process, or generates a control signal based on the data. Or, if the setting changing flag and setting confirmation flag are set to ON, output data to the setting display device 620 (see FIGS. 7 and 8B) is generated, or the relevant This is a process of outputting a control signal based on data. By this processing, the lottery results are displayed on the special symbol display device 50 and the normal symbol display device 51, and the set value of the probability of generating a special game state advantageous to the player is displayed on the setting display device 620.例文帳に追加

Next, the main control CPU 600a executes external terminal management processing (step S118). In this external terminal management process, a hall computer (not shown) used for management of game islands in a game arcade stores information such as the number of occurrences of winning, the number of times special symbols change, and the detection of winning balls to the winning opening during a winning game. , predetermined game information is output. Further, when the setting changing flag and the setting confirmation flag are set to ON, a security signal is output.

Next, the main control CPU 600a returns to the interrupt enabled state (step S119), restores the contents of the register saved in the normal stack area 600cc (see FIG. 9A) of the main control RAM 600c, and ends the timer interrupt. (Step S120). As a result, the interrupt processing routine returns to the main processing (see FIG. 28).

The voltage monitoring process (step S101) to error management process (step S105), the prize ball management process (step S109) to the external terminal management process (step S118) executed in the timer interrupt process are called by the CALL_M instruction. will be processed.

<Description of normal symbol processing>
Next, referring to FIG. 31, the normal symbol processing will be described in detail.

As shown in FIG. 31, in the normal symbol processing, first, in the normal symbol starting port 47 (see FIG. 5) consisting of a gate, it is confirmed whether or not the passage of the game ball is detected. The signal level of the normal symbol starting port switch 47a (see FIG. 7) is confirmed (step S150). Then, when the passage of the game ball is detected (step S150: YES), the main control CPU 600a determines whether the number of start suspension balls of the normal symbol is, for example, 4 or more, so that the number of start suspension balls of the normal symbol is stored. The normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c is confirmed (step S151). At that time, if the number of starting reservation balls in the normal design is less than 4 (step S151: ≠MAX), the number of starting reservation balls in the normal design is added by 1 (step S152). After that, the main control CPU 600a puts the normal symbol hit determination random number used in the normal symbol lottery into the normal RAM area 600ca (FIG. 9A) of the main control RAM 600c in which the number of start suspension balls of the normal symbol is stored. ) (step S153), and the process proceeds to step S154.

On the other hand, in step S150, when the passage of the game ball is not detected (step S150: NO), in step S151, when it is determined that the number of start suspension balls in the normal design is 4 or more (step S151: = MAX), the process of steps S152 and S153 is not performed, and the process proceeds to step S154.

When proceeding to the process of step S154, the main control CPU 600a checks whether the normal symbol per operation flag is set to ON, that is, whether the normal symbol per operation flag is set to 5AH (step S154). If 5AH is set in the normal design winning operation flag (step S154: ON), it is determined that the normal design is in the process of winning, and after updating the display data of the normal design (step S153), normal design processing is performed. finish.

On the other hand, if 5AH is not set to the operation flag per normal symbol (step S154: OFF), the processing state indicating the behavior of the normal symbol, that is, the value of the normal symbol operation status flag is confirmed (step S155). Then, if the normal design operation status flag is 00H, the main control CPU 600a judges that it is in a state before the start of fluctuation of the normal design, proceeds to step S156, and determines whether the number of start suspension balls of the normal design is 0 or not. Confirm (step S156).

The main control CPU 600a checks the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c in which the number of starting pending balls of the normal symbol is stored, and determines that it is 0 (step S156 :=0) normally finishes the design process after updating the display data of the normal design (step S153). On the other hand, if it is determined not to be 0 (step S156: ≠0), 1 is subtracted from the number of start-holding balls of normal symbols (step S157).

After that, the main control CPU 600a uses the normal symbol hit determination table NPP_TBL shown in FIG. Hit judgment is performed with a random value corresponding to the number of balls. That is, the main control CPU 600a, if the normal symbol probability variation flag indicating the game state is OFF, the random number is the lower limit value of the normal symbol hit determination table NPP_TBL (normal state) shown in FIG. 249) or more and the upper limit value (250 in the figure) or less is determined, and if the lower limit value or more and the upper limit value or less, the normal symbol hit determination flag is set to 5AH and turned ON. Otherwise, the normal symbol hit determination flag is turned OFF.

On the other hand, if the normal symbol probability variation flag indicating the gaming state is ON, the random number is the lower limit value (4 in the illustration) of the normal symbol hit determination table NPP_TBL (probability variation state) shown in FIG. A value (250 in the figure) is determined, and if it is equal to or more than the lower limit value and equal to or less than the upper limit value, 5AH is set to the normal symbol hit determination flag and turned ON. Otherwise, a process of setting the normal symbol hit determination flag to OFF is performed (step S158).

Then, the main control CPU 600a determines a stop symbol (normal symbol stop symbol) based on the lottery result determined in the random number lottery process (step S159).

Next, the main control CPU 600a confirms whether the normal pattern time saving flag for shortening the normal pattern fluctuation time is set to ON, and if it is set to ON, sets the normal pattern fluctuation timer to the corresponding fluctuation time. However, if it is set to OFF, a process of setting a normal variation time to the normal symbol variation timer is performed (step S160).

Next, the main control CPU 600a stores the random number used in the normal symbol win/loss lottery corresponding to the normal symbol starting ball number. The storage area is shifted (step S161). That is, assuming that the number of start-holding balls of the normal design can be reserved up to 4, the random number used for the lottery of the normal design corresponding to the number of start-holding balls of the normal design of 4 is set to the number of start-holding balls of the normal design of 3. Shift to the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c in which the random value used for the winning lottery of the corresponding normal symbol is stored, and the normal corresponding to the number of start suspension balls 3 of the normal symbol A normal RAM area 600ca of the main control RAM 600c (Fig. 9(a)) stores the random number used for the winning/failing lottery for the normal symbol corresponding to the number of start-holding balls 2 for the normal symbol. )), and the random number used for the lottery of the normal design corresponding to the number of starting suspension balls of the normal design of 2 is stored in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c.

After this process, the main control CPU 600a sets the normal symbol operation status flag used in step S155 to 01H, and the random number used for the normal symbol success/fail lottery corresponding to the normal symbol starting hold ball number 4 is 00H is set in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c (step S162).

Then, after completing the process of step S162, the main control CPU 600a updates the display data of the normal symbol (step S163), and ends the normal symbol process.

On the other hand, the main control CPU600a, in the above step S155, the processing state indicating the behavior of the normal symbol, that is, if the value of the normal symbol operation status flag is 01H, the main control CPU600a determines that the normal symbol is fluctuating. It judges, it progresses to step S164, and it confirms whether a normal design variation timer is 0 (step S164). If the normal symbol fluctuation timer is not 0 (step S164: ≠0), the normal symbol display data is updated (step S163), and the normal symbol processing is finished. Then, if the normal symbol variation timer is 0 (step S164: = 0), the main control CPU 600a sets 02H to the normal symbol operation status flag used in step S155, and the normal symbol lottery result is fixed. In order to maintain the time, for example, a period of about 600 ms is set in the normal symbol variation timer (step S165).

After completing the process of step S165, the main control CPU 600a updates the display data of the normal symbol (step S163), and ends the normal symbol process.

On the other hand, in the above step S155, the main control CPU 600a is in a processing state that indicates the behavior of the normal symbol, that is, if the value of the normal symbol operation status flag is 02H, the main control CPU 600a determines that the normal symbol is during the confirmation time (normal The symbol variation is finished and stopped), and the process proceeds to step S166 to confirm whether or not the normal symbol variation timer is 0 (step S166). If the normal symbol fluctuation timer is not 0 (step S166: ≠0), the normal symbol display data is updated (step S163), and the normal symbol processing is finished. Then, if the normal symbol variation timer is 0 (step S166:=0), the main control CPU 600a sets the normal symbol operation status flag used in step S155 to 00H (step S167), and determines the normal symbol hit. It is checked whether the flag is set to ON (5AH is set) (step S168).

Thus, if the normal symbol hit determination flag is set to OFF (5AH is not set) (step S168: OFF), the main control CPU 600a updates the normal symbol display data (step S163), Finish normal design processing. Then, if the normal symbol hit determination flag is set to ON (5AH is set) (step S168: ON), the main control CPU 600a turns ON the normal symbol hit operation flag used in step S154 (sets 5AH). (step S169), the normal design process is finished.

<Description of special symbol processing>
Next, with reference to FIGS. 32 to 37, the special symbol processing will be described in detail.

As shown in FIG. 32, in the special symbol processing, first, a game ball enters (winning ball) at the special symbol 1 starting port switch 44a (see FIG. 7) of the special symbol 1 starting port 44 (see FIG. 5). It is confirmed whether or not it is detected (step S200), and furthermore, at the special symbol 2 start port switch 45a (see FIG. 7) of the special symbol 2 start port 45 (see FIG. 5), the entering ball (winning ball) of the game ball is detected. It is checked whether or not it has been detected (step S201).

<Special symbol processing: Description of start port check processing>
This process will be explained in detail with reference to FIG. The level of the special pattern 1 starting port switch 44a of the pattern 1 starting port 44 or the special pattern 2 starting port switch 45a of the special pattern 2 starting port 45 is confirmed (step S250). Thereby, if the entry of the game ball (winning a prize) is not detected (step S250: NO), the special symbol processing is finished.

On the other hand, if the entry of a game ball (winning a prize) is detected (step S250: YES), the main control CPU 600a determines that the number of starting and holding balls that triggers the fluctuation of the special symbol is a predetermined number, and the normal RAM area 600ca of the main control RAM 600c. (See FIG. 9(a)) to confirm whether or not it is stored (step S251). If the starting pending ball number is less than 4 (step S251: ≠ MAX), the starting pending ball number is added by 1 (+1) (step S252).

Next, the main control CPU 600a stores the random number used when stopping the special symbols, the random number for the variation pattern, and the random number for judging the big hit in the main control RAM 600c, which stores the number of starting pending balls that trigger the variation of the special symbols. is stored in the RAM area 600ca (see FIG. 9A) (step 253).

Next, the main control CPU 600a confirms the current gaming state (whether or not the special symbol jackpot determination flag is set to ON, etc.), and determines whether or not the prefetching is prohibited (step S254). Then, if it is not in the pre-reading prohibited state (step S254: NO), the main control CPU 600a stores in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c in the above step S253. (Step S255), and further acquires a random number determination table (not shown) at the time of start-up winning (Step S256).

Next, the main control CPU 600a performs a jackpot lottery using the random number value for jackpot determination acquired in step S255 and the random number determination table (not shown) at the time of start-up winning acquired in step S256. At step S253, using the special symbol random number value stored in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c, the type of jackpot (rank-up bonus hit, normal jackpot, etc.) is determined. , Using the random number for the variation pattern, the variation pattern is determined, and a special symbol start opening winning command is generated accordingly (step S257). In addition, when generating this special symbol start opening winning command, a program for acquiring the variable time as shown in FIG. 11(b), FIG. 26, and FIG. 27 is executed.

Next, the main control CPU 600a generates a lower byte start pending addition command corresponding to the generated special symbol start opening winning command (step S258).

On the other hand, the main control CPU 600a finishes the processing of step S258, or the number of starting holding balls of special symbol 1 or 2 is 4 or more in step S251 (step S251:=MAX), or pre-reading If it is in the prohibited state (step S254: YES), a start suspension addition command of the upper byte corresponding to the increased number of start suspension balls is generated (step S259).

Next, the main control CPU 600a combines the low-order byte starting pending addition command generated in step S258 with the high-order byte starting pending addition command generated in step S259, and then outputs the starting pending addition command (effect A control command DI_CMD) is transmitted to the effect control board 90 (step S260). This starting pending addition command (effect control command DI_CMD) transmission processing is called by a CALL_S command and processed.

<Description of special symbol processing>
Thus, when the processing of steps S200 and S201 shown in FIG. 32 is finished, the main control CPU 600a determines whether the special symbol small hit operation flag is set to ON, that is, whether the special symbol small hit operation flag is set to 5AH. It is confirmed whether there is (step S202). If 5AH is set in the special symbol small hit operation flag (step S202: ON), it is determined that the special symbol is in the middle of a small hit, and after updating the display data of the special symbol (step S208), special Complete pattern processing.

On the other hand, if the special symbol small winning operation flag is not set to 5AH (step S202: OFF), is the special symbol big winning operation flag set to ON, that is, is the special symbol big winning operation flag set to 5AH? is confirmed (step S203). If 5AH is set in the special symbol big hit operation flag (step S203: ON), it is determined that the special symbol is in the midst of a big hit, and after updating the display data of the special symbol (step S208), special symbol processing is performed. finish.

On the other hand, if 5AH is not set in the special symbol jackpot operation flag (step S203: OFF), the processing state indicating the behavior of the special symbol, that is, the value of the special symbol operation status flag is confirmed (step S204). More specifically, if the value of the special symbol operation status flag is 00H or 01H, the main control CPU 600a is in a special symbol variation waiting state (a special symbol variation is not performed and it is in a standby state for the next variation. It indicates that there is), and performs special symbol variation start processing (step S205).

<Special symbol processing: Explanation of special symbol variation start processing>
This process will be described in detail with reference to FIG. 34. The main control CPU 600a confirms whether or not the number of starting pending balls, which triggers the variation of special symbols, is 0 (step S300). That is, the main control CPU 600a confirms whether or not it is stored in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c. :=0), and confirms whether or not the value of the special symbol operation status flag is 00H (step S301). If the value of the special symbol operation status flag is 00H (step S301: YES), the special symbol variation start process is terminated.

On the other hand, if the value of the special symbol operation status flag is not 00H (step S301: NO), the main control CPU 600a transmits the customer waiting demo command to the effect control board 90 as the effect control command DI_CMD (step S302). The customer waiting demo command (effect control command DI_CMD) transmission process is called by the CALL_S command and processed.

Next, the main control CPU 600a sets the special symbol operation status flag to 00H (step S303), and ends the special symbol variation start process.

On the other hand, when the main control CPU 600a determines that the number of start-holding balls is not 0 (step S300: ≠ 0), it subtracts 1 (-1) from the number of start-holding balls (step S304), and controls the start-holding subtraction command. It is transmitted to the effect control board 90 as a command DI_CMD (step S305). It should be noted that the start pending subtraction command (effect control command DI_CMD) transmission processing will be called by the CALL_S instruction and processed.

Next, the main control CPU 600a stores the random number used when stopping the special symbols, the random number for the variation pattern, and the random number for judging the big hit (see step S253 in FIG. 33). (See FIG. 9(a)) shifts the storage area in (step S306), and the normal RAM area 600ca of the main control RAM 600c where the random number used for the lottery of the special symbol corresponding to the start suspension 4 is stored. (See FIG. 9A) 0 is set in the area (step S307).

Next, the main control CPU600a, in step S253 of FIG. 33, the random number corresponding to each starting suspension ball number (starting suspension 1-4) stored in the normal RAM area 600ca of the main control RAM600c (see FIG. 9 (a)) A numerical value (random number for judging a big hit) indicates whether the special pattern is a big hit or a small hit using a special symbol big hit determination table SDH_TBL shown in FIG. 37(b) and a special symbol small hit determination table SDP_TBL shown in FIG. judge. That is, the main control CPU 600a, if the special symbol probability variable flag indicating the gaming state is OFF, the random number value for big hit determination is the lower limit value (illustrated Then, 10001) or more and the upper limit value (10164 in the figure) or less is determined, and if the lower limit value or more and the upper limit value or less, the special symbol jackpot determination flag is set to 5AH and turned ON. Otherwise, the special symbol jackpot determination flag is turned OFF.

On the other hand, if the special symbol probability variation flag indicating the gaming state is ON, the jackpot determination random number is the lower limit value (10001 in the illustration) of the special symbol jackpot determination table SDH_TBL (probability variation state) shown in FIG. 37(b) or more. It determines whether it is below the upper limit value (11640 in the figure), and if it is above the lower limit value and below the upper limit value, it sets 5AH to the special symbol jackpot determination flag and turns it ON. Otherwise, a process of setting the special symbol jackpot determination flag to OFF is performed.

On the other hand, if the special symbol 2 fluctuating flag is OFF, the main control CPU 600a determines that the random number value for big hit determination is the lower limit value (illustrated Then, 20001) or more and the upper limit value (20164 in the figure) or less is determined, and if the lower limit value or more and the upper limit value or less, 5AH is set to the special symbol small hit determination flag and turned ON. Otherwise, a process of setting the special symbol small hit determination flag to OFF is performed.

On the other hand, if the special symbol 2 fluctuating flag is ON, the random number for big hit determination is the lower limit value (20001 in the illustration) of the special symbol small hit determination table SDP_TBL (special symbol 2) shown in FIG. It determines whether or not it is below the upper limit value (20082 in the illustration), and if it is above the lower limit value and below the upper limit value, it sets 5AH to the special symbol small hit determination flag and turns it ON. Otherwise, a process of setting the special symbol small hit determination flag to OFF is performed (step S308).

Thus, after finishing the hit determination process (step S308) as described above, the main control CPU 600a stores in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c in step S253 of FIG. Using the random number value used when stopping the special symbol, a stop symbol of the special symbol is generated (step S309).

Next, the main control CPU 600a prepares to shift to one of the normal state, time saving state, latent probability variable state, and probability variable state (step S310).

Next, the main control CPU 600a generates a special symbol variation pattern using the variation pattern random number value stored in the normal RAM area 600ca (see FIG. 9A) of the main control RAM 600c in step S253 of FIG. Then, the variation pattern command of the generated special symbol variation pattern is transmitted to the effect control board 90 as the effect control command DI_CMD (step S311). At this time, a program for acquiring variable time as shown in FIG. 13(b) and FIG. 26(a) is executed, and variable time is set in the special symbol variable timer. It should be noted that the variation pattern command (effect control command DI_CMD) transmission processing is called by the CALL_S command and processed.

Next, the main control CPU 600a sets the special symbol fluctuating flag to 5AH and turns it ON (step S312).

Next, the main control CPU 600a generates a symbol designation command for designating a special symbol to be displayed on the liquid crystal display device 41 (step S313), and transmits the generated symbol designation command to the effect control board 90 as the effect control command DI_CMD. (step S314). Incidentally, the design designation command (effect control command DI_CMD) transmission processing is called by the CALL_S command and processed.

Next, the main control CPU 600a sets the special symbol operation status flag to 02H (step S315), and ends the special symbol variation start process.

<Description of special symbol processing>
On the other hand, as shown in FIG. 32, when the value of the special symbol operation status flag is 02H, the main control CPU 600a determines that the special symbol is fluctuating (indicating that the special symbol is currently fluctuating). During symbol variation processing is performed (step S206).

<Special symbol processing: Explanation of processing during special symbol fluctuation>
This process will be explained in detail using FIG. 35. First, the main control CPU 600a determines whether the variation time set in the special symbol variation timer in step S311 of FIG. is confirmed (step S350). If the special symbol variation timer is not 0 (step S350: NO), the main control CPU 600a ends the special symbol variation process.

On the other hand, if the special symbol variation timer is 0 (step S350: YES), the main control CPU 600a transmits the symbol stop command to the effect control board 90 as the effect control command DI_CMD (step S351). It should be noted that the design stop command (effect control command DI_CMD) transmission processing is called by the CALL_S command and processed.

Next, the main control CPU 600a sets the special symbol operation status flag to 03H, and sets the special symbol fluctuating flag to 00H. Further, the main control CPU 600a sets the special symbol variation timer to a time of about 500 ms, for example, in order to maintain the result of the special symbol lottery for a certain period of time (step S352). After that, the main control CPU 600a ends the special symbol fluctuation process.

<Description of special symbol processing>
On the other hand, as shown in FIG. 32, when the value of the special symbol operation status flag is 03H, the main control CPU 600a indicates that the special symbol is being confirmed (indicating that the special symbol variation is finished and stopped). It judges and performs processing during special design confirmation time (Step S207).

<Special symbol processing: Explanation of special symbol confirmation processing>
This process will be explained in detail using FIG. 36. First, the main control CPU 600a determines whether the variation time set in the special symbol variation timer in step S311 of FIG. is confirmed (step S400). If the special symbol variation timer is not 0 (step S400≠0), the main control CPU 600a ends the special symbol confirmation time processing.

On the other hand, if the special symbol variation timer is 0 (step S400=0), the main control CPU 600a sets the special symbol operation status flag to 01H (step S401), and whether the special symbol jackpot determination flag is set to ON. Confirm (whether 5AH is set) (step S402). If the special symbol jackpot determination flag is set to ON (if 5AH is set) (step S402: YES), the special symbol jackpot determination flag is set to 00H, and the special symbol jackpot operation flag is set to 5AH. , And set 00H to the normal symbol time saving flag, set 00H to the normal symbol probability variation flag, set 00H to the special symbol time saving flag, set 00H to the special symbol probability variation flag, and set the special symbol time saving number of times to be described later. A process of setting 00H to the counter and the special symbol probability variation counter is performed (step S403). After that, the main control CPU 600a ends the special symbol confirmation time processing.

On the other hand, if the special symbol big hit determination flag is not set to ON (if 5AH is not set) (step S402: NO), the main control CPU 600a determines whether the special symbol small hit determination flag is set to ON ( 5AH is set) (step S404). If the special symbol small hit determination flag is set to ON (if 5AH is set) (step S404: YES), the special symbol small hit determination flag is set to 00H, and the special symbol small hit operation flag is set to 5AH. is set (step S405).

After finishing the process of step S405, or if the special symbol small hit determination flag is not set to ON (if 5AH is not set) (step S404: NO), the main control CPU 600a It is checked whether the value of the number counter is 0 (step S406).

If the value of the special symbol time saving number counter is not 0 (step S406: NO), the value of the special symbol time saving number counter is subtracted by 1 (-1) (step S407), and the main control CPU 600a again, the special symbol time saving number of times It is checked whether the value of the counter is 0 (step S408). Then, if the value of the special symbol time reduction counter is 0 (step S408: YES), the normal symbol time reduction flag is set to 00H, the normal symbol probability variation flag is set to 00H, and the normal symbol time reduction flag is set to 00H. is set (step S409).

After finishing the process of step S409, or the value of the special symbol time saving number counter is 0 (step S406: YES), or the value of the special symbol time saving number counter is not 0 (step S408: NO), the main The control CPU 600a confirms whether or not the value of the special symbol probability variation counter is 0 (step S410). If the value of the special symbol probability variation counter is 0 (step S410: YES), the main control CPU 600a ends the special symbol confirmation time process.

On the other hand, if the value of the special symbol probability variation number counter is not 0 (step S410: NO), the main control CPU 600a subtracts 1 from the value of the special symbol probability variation number counter (-1) (step S411), and again special symbols. It is checked whether the value of the probability variation number counter is 0 (step S412). If the value of the special symbol probability variation counter is not 0 (step S412: NO), the main control CPU 600a ends the special symbol confirmation time process.

On the other hand, if the value of the special symbol probability variation counter is 0 (step S412: YES), the main control CPU 600a sets the normal symbol probability variation flag to 00H, sets the normal symbol probability variation flag to 00H, and sets the special symbol probability variation flag to 00H. is set to 00H, the special symbol probability variation flag is set to 00H (step S413), and the process during the special symbol confirmation time is terminated.

<Main control: Explanation of special symbol processing>
Thus, when one of the processes of steps S205, S206, and S207 shown in FIG. 32 is finished, the main control CPU 600a updates the special symbol display data (step S208), and then finishes the special symbol process. .

Thus, according to the present embodiment described above, the program capacity can be reduced, and the data capacity of the ROM can be reduced.

Further, according to the present embodiment, as described in the outline of the program stored in the normal program area 600ba of the main control ROM 600b shown in FIG. The ratio used in timer interrupt processing is higher than the ratio used from initialization processing to main loop processing that calls timer interrupt processing. Therefore, it is possible to further reduce the processing load of the program and reduce the program capacity.

1 pachinko game machine 60 main control board 600 one-chip microcomputer 600a main control CPU (game means, data reading means)
600a1 general-purpose register (storage means)
600a4 TP register (second address address information storage means)
600b Main control ROM (ROM)
600ba normal program area 600bc normal data area 600be measurement program area 600bg measurement data area

Claims (2)

game means capable of executing a symbol variation game;
a ROM storing a plurality of data relating to the symbol variation game;
data reading means for reading specific data designated from among the plurality of data into storage means;
a first address address information storage means for storing first address information relating to the address of the area in which the specific data is stored;
a second address address information storage means for storing second address information relating to the address addresses of the areas in which the plurality of data are stored;
a measurement process for measuring a predetermined value related to a game value to be provided to a game based on establishment of a predetermined condition in a predetermined game program;
Lottery processing for performing a lottery as to whether or not to generate a special game state;
a command transmission process related to command transmission;
The data reading means is
based on the first address information and the second address information, referring to a specific address where the specific data is stored, reading the specific data into the storage means ;
The ROM is
a first storage area identifiable by the second address information;
a second storage area that cannot be specified by the second address information;
a first process for performing a process using the data stored in the first storage area;
a second process for performing a process using the data stored in the second storage area;
executing a second address address information saving process for saving the second address information from the second address address information storage means to a predetermined storage area when shifting from the first process to the second process;
executing a second address address information return process for returning the second address information from the predetermined storage area to the second address address information storage means when shifting from the second process to the first process;
The predetermined game program includes a plurality of call instructions capable of calling predetermined modules,
the plurality of call instructions includes a first call instruction, a second call instruction, and a third call instruction;
wherein the first call instruction has no limit on the address address of the module to be called among the plurality of call instructions;
the second call instruction has a program code data amount smaller than that of the first call instruction, and among the plurality of call instructions, the address address of the module to be called is within a predetermined range;
the third call instruction has the smallest amount of program code data among the plurality of call instructions;
The predetermined game program has a normal program used during game processing and a measurement program used for the measurement processing,
The command transmission processing is a module in a normal program called by the third call instruction from the normal program,
The third call instruction for calling the command transmission process is used in a game program within an interrupt process that is executed based on a timer interrupt signal that occurs at predetermined intervals in the normal program. A game machine in which the frequency of use in a game program up to a main loop process in which the interrupt process is called is higher than that of the game program. game means capable of executing a symbol variation game;
a ROM storing a plurality of data relating to the program of the symbol variation game;
data reading means for reading specific data designated from among the plurality of data into storage means;
a first address address information storage means for storing first address information relating to the address of the area in which the specific data is stored;
a second address address information storage means for storing second address information relating to the address addresses of the areas in which the plurality of data are stored;
a measurement process for measuring a predetermined value related to a game value to be provided to a game based on establishment of a predetermined condition in a predetermined game program;
Lottery processing for performing a lottery as to whether or not to generate a special game state;
a command transmission process related to command transmission;
The data reading means is
based on the first address information and the second address information, referring to a specific address where the specific data is stored, reading the specific data into the storage means;
The ROM is
a first storage area identifiable by the second address information;
a second storage area that cannot be specified by the second address information;
a first process for performing a process using the data stored in the first storage area;
a second process for performing a process using the data stored in the second storage area;
The first process includes a first game process and a second game process related to the symbol variation game,
When shifting from the first game process to the second game process, a storage means save process for saving the data stored in the storage means to a predetermined storage area is executed. The second address information saving process for saving from the second address information storage means to a predetermined storage area is not executed,
When shifting from the second game process to the first game process, a storage means return process for returning the data saved in the predetermined storage area to the storage means is executed. from the predetermined storage area to the second address information storage means is not executed,
The predetermined game program includes a plurality of call instructions capable of calling predetermined modules,
the plurality of call instructions includes a first call instruction, a second call instruction, and a third call instruction;
wherein the first call instruction has no limit on the address address of the module to be called among the plurality of call instructions;
the second call instruction has a program code data amount smaller than that of the first call instruction, and among the plurality of call instructions, the address address of the module to be called is within a predetermined range;
the third call instruction has the smallest amount of program code data among the plurality of call instructions;
The predetermined game program has a normal program used during game processing and a measurement program used when measuring a predetermined value related to game value,
The command transmission processing is a module in a normal program called by the third call instruction from the normal program,
The third call instruction for calling the command transmission process is used in a game program within an interrupt process that is executed based on a timer interrupt signal that occurs at predetermined intervals in the normal program. A game machine in which the frequency of use in a game program up to a main loop process in which the interrupt process is called is higher than that of the game program.

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