JP7281535B2 - 深層学習ニューラルネットワークで使用されるアナログニューラルメモリシステムのメモリセルに対する温度補償及び漏れ補償 - Google Patents

深層学習ニューラルネットワークで使用されるアナログニューラルメモリシステムのメモリセルに対する温度補償及び漏れ補償 Download PDF

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JP7281535B2
JP7281535B2 JP2021510952A JP2021510952A JP7281535B2 JP 7281535 B2 JP7281535 B2 JP 7281535B2 JP 2021510952 A JP2021510952 A JP 2021510952A JP 2021510952 A JP2021510952 A JP 2021510952A JP 7281535 B2 JP7281535 B2 JP 7281535B2
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memory cells
array
flash memory
memory cell
temperature
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トラン、ヒュー、バン
ティワリ、ビピン
レイテン、マーク
ドー、ナン
レムケ、スティーブン
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Silicon Storage Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
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    • G06N3/00—Computing arrangements based on biological models
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    • G06N3/08—Learning methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/04—Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

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JP2021510952A 2018-08-27 2019-07-23 深層学習ニューラルネットワークで使用されるアナログニューラルメモリシステムのメモリセルに対する温度補償及び漏れ補償 Active JP7281535B2 (ja)

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US201862723398P 2018-08-27 2018-08-27
US62/723,398 2018-08-27
US16/183,250 2018-11-07
US16/183,250 US10755783B2 (en) 2018-08-27 2018-11-07 Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network
PCT/US2019/043101 WO2020046495A1 (en) 2018-08-27 2019-07-23 Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network

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JP2021536623A5 JP2021536623A5 (https=) 2022-08-01
JP7281535B2 true JP7281535B2 (ja) 2023-05-25

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CN (1) CN112602095B (https=)
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US12572786B2 (en) 2021-03-31 2026-03-10 International Business Machines Corporation NVM-based high-capacity neural network inference engine
US11521694B2 (en) * 2021-05-04 2022-12-06 Micron Technology, Inc. Adjustment to trim settings based on a use of a memory device
US11380373B1 (en) * 2021-05-12 2022-07-05 Globalfoundries U.S. Inc. Memory with read circuit for current-to-voltage slope characteristic-based sensing and method
US12579422B2 (en) * 2021-08-02 2026-03-17 Silicon Storage Technology, Inc. Input circuitry for analog neural memory in a deep learning artificial neural network
US11989440B2 (en) * 2021-08-11 2024-05-21 Silicon Storage Technology, Inc. Hybrid memory system configurable to store neural memory weight data in analog form or digital form
JP7733233B2 (ja) * 2021-11-12 2025-09-02 シリコン ストーリッジ テクノロージー インコーポレイテッド ニューラルネットワークにおける１つ以上のメモリセルに印加するためのバイアス電圧の決定
US20230306246A1 (en) * 2022-02-08 2023-09-28 Silicon Storage Technology, Inc. Calibration of electrical parameters in a deep learning artificial neural network
US11716089B1 (en) * 2022-03-16 2023-08-01 Xilinx, Inc. Delay-tracking biasing for voltage-to-time conversion
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EP4138079A1 (en) 2023-02-22
US20210090654A1 (en) 2021-03-25
JP2021536623A (ja) 2021-12-27
CN112602095B (zh) 2022-05-27
EP3844680A1 (en) 2021-07-07
US11521682B2 (en) 2022-12-06
WO2020046495A1 (en) 2020-03-05
TW202026955A (zh) 2020-07-16
US10755783B2 (en) 2020-08-25
KR102457394B1 (ko) 2022-10-21
US20200350015A1 (en) 2020-11-05
TWI754162B (zh) 2022-02-01
EP3844680B1 (en) 2022-11-23
CN112602095A (zh) 2021-04-02
US11158374B2 (en) 2021-10-26
EP4138079B1 (en) 2024-08-28
KR20210032538A (ko) 2021-03-24
US20200066345A1 (en) 2020-02-27

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