CN112602095B - 用于深度学习神经网络中使用的模拟神经存储器系统中的存储器单元的温度和泄漏补偿 - Google Patents
用于深度学习神经网络中使用的模拟神经存储器系统中的存储器单元的温度和泄漏补偿 Download PDFInfo
- Publication number
- CN112602095B CN112602095B CN201980055114.7A CN201980055114A CN112602095B CN 112602095 B CN112602095 B CN 112602095B CN 201980055114 A CN201980055114 A CN 201980055114A CN 112602095 B CN112602095 B CN 112602095B
- Authority
- CN
- China
- Prior art keywords
- memory cell
- array
- flash memory
- voltage
- memory cells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/044—Recurrent networks, e.g. Hopfield networks
- G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/0464—Convolutional networks [CNN, ConvNet]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/045—Combinations of networks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/04—Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Data Mining & Analysis (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- Life Sciences & Earth Sciences (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Molecular Biology (AREA)
- General Health & Medical Sciences (AREA)
- Biophysics (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Linguistics (AREA)
- Artificial Intelligence (AREA)
- Evolutionary Computation (AREA)
- Neurology (AREA)
- Databases & Information Systems (AREA)
- Algebra (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862723398P | 2018-08-27 | 2018-08-27 | |
| US62/723,398 | 2018-08-27 | ||
| US16/183,250 | 2018-11-07 | ||
| US16/183,250 US10755783B2 (en) | 2018-08-27 | 2018-11-07 | Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network |
| PCT/US2019/043101 WO2020046495A1 (en) | 2018-08-27 | 2019-07-23 | Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112602095A CN112602095A (zh) | 2021-04-02 |
| CN112602095B true CN112602095B (zh) | 2022-05-27 |
Family
ID=69586480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980055114.7A Active CN112602095B (zh) | 2018-08-27 | 2019-07-23 | 用于深度学习神经网络中使用的模拟神经存储器系统中的存储器单元的温度和泄漏补偿 |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US10755783B2 (https=) |
| EP (2) | EP4138079B1 (https=) |
| JP (1) | JP7281535B2 (https=) |
| KR (1) | KR102457394B1 (https=) |
| CN (1) | CN112602095B (https=) |
| TW (1) | TWI754162B (https=) |
| WO (1) | WO2020046495A1 (https=) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10755783B2 (en) * | 2018-08-27 | 2020-08-25 | Silicon Storage Technology | Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network |
| US11513797B2 (en) * | 2018-09-12 | 2022-11-29 | Mentium Technologies Inc. | Systems and methods for analog vector by matrix multiplier |
| JP7196803B2 (ja) * | 2018-10-18 | 2022-12-27 | 株式会社デンソー | 人工ニューラルネットワーク回路及び人工ニューラルネットワーク回路における学習値切替方法 |
| US11507641B2 (en) * | 2019-05-31 | 2022-11-22 | Advanced Micro Devices, Inc. | Temperature-based adjustments for in-memory matrix multiplication |
| US11074976B2 (en) * | 2019-08-26 | 2021-07-27 | Sandisk Technologies Llc | Temperature dependent impedance mitigation in non-volatile memory |
| US11875852B2 (en) * | 2020-07-06 | 2024-01-16 | Silicon Storage Technology, Inc. | Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network |
| US11809838B2 (en) * | 2020-09-08 | 2023-11-07 | Macronix International Co., Ltd. | Memory device and operation method thereof |
| US12106070B2 (en) * | 2020-09-08 | 2024-10-01 | Macronix International Co., Ltd. | Memory device and operation method thereof |
| US11630002B2 (en) * | 2021-02-08 | 2023-04-18 | Macronix International Co., Ltd. | Method for sensing temperature in memory die, memory die and memory with temperature sensing function |
| KR102553403B1 (ko) * | 2021-02-23 | 2023-07-11 | 한국과학기술원 | 우수한 선형성 특성을 갖는 뉴로모픽 시냅스 소자 및 그 동작 방법 |
| US12572786B2 (en) | 2021-03-31 | 2026-03-10 | International Business Machines Corporation | NVM-based high-capacity neural network inference engine |
| US11521694B2 (en) * | 2021-05-04 | 2022-12-06 | Micron Technology, Inc. | Adjustment to trim settings based on a use of a memory device |
| US11380373B1 (en) * | 2021-05-12 | 2022-07-05 | Globalfoundries U.S. Inc. | Memory with read circuit for current-to-voltage slope characteristic-based sensing and method |
| US12579422B2 (en) * | 2021-08-02 | 2026-03-17 | Silicon Storage Technology, Inc. | Input circuitry for analog neural memory in a deep learning artificial neural network |
| US11989440B2 (en) * | 2021-08-11 | 2024-05-21 | Silicon Storage Technology, Inc. | Hybrid memory system configurable to store neural memory weight data in analog form or digital form |
| JP7733233B2 (ja) * | 2021-11-12 | 2025-09-02 | シリコン ストーリッジ テクノロージー インコーポレイテッド | ニューラルネットワークにおける1つ以上のメモリセルに印加するためのバイアス電圧の決定 |
| US20230306246A1 (en) * | 2022-02-08 | 2023-09-28 | Silicon Storage Technology, Inc. | Calibration of electrical parameters in a deep learning artificial neural network |
| US11716089B1 (en) * | 2022-03-16 | 2023-08-01 | Xilinx, Inc. | Delay-tracking biasing for voltage-to-time conversion |
| TWI852248B (zh) * | 2022-12-29 | 2024-08-11 | 大陸商合肥創發微電子有限公司 | 動態溫度補償之方法及其系統 |
| US11955193B1 (en) * | 2023-12-05 | 2024-04-09 | Aspinity, Inc. | Compute-in-memory array multi-range temperature compensation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359499B1 (en) * | 2000-06-23 | 2002-03-19 | Marvell International Ltd. | Temperature and process independent CMOS circuit |
| CN102684683A (zh) * | 2012-05-14 | 2012-09-19 | 常熟银海集成电路有限公司 | 任意项全系数高精度温度补偿晶体振荡器 |
| CN107533668A (zh) * | 2016-03-11 | 2018-01-02 | 慧与发展有限责任合伙企业 | 用于计算神经网络的节点值的硬件加速器 |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3668440A (en) | 1970-10-16 | 1972-06-06 | Motorola Inc | Temperature stable monolithic multiplier circuit |
| US5029130A (en) | 1990-01-22 | 1991-07-02 | Silicon Storage Technology, Inc. | Single transistor non-valatile electrically alterable semiconductor memory device |
| US6560152B1 (en) * | 2001-11-02 | 2003-05-06 | Sandisk Corporation | Non-volatile memory with temperature-compensated data read |
| US6747310B2 (en) | 2002-10-07 | 2004-06-08 | Actrans System Inc. | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication |
| JP2007059024A (ja) * | 2005-08-26 | 2007-03-08 | Micron Technol Inc | 温度補償された読み出し・検証動作をフラッシュ・メモリにおいて生成するための方法及び装置 |
| JP2007164960A (ja) * | 2005-11-15 | 2007-06-28 | Nec Electronics Corp | 半導体集積回路装置 |
| US8102201B2 (en) * | 2006-09-25 | 2012-01-24 | Analog Devices, Inc. | Reference circuit and method for providing a reference |
| ITRM20060652A1 (it) * | 2006-12-06 | 2008-06-07 | Micron Technology Inc | Compensazione di temperatura di segnali di memoria impiegando segnali digitali |
| US7889575B2 (en) * | 2008-09-22 | 2011-02-15 | Sandisk Corporation | On-chip bias voltage temperature coefficient self-calibration mechanism |
| KR101868332B1 (ko) * | 2010-11-25 | 2018-06-20 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것을 포함한 데이터 저장 장치 |
| US8873316B2 (en) * | 2012-07-25 | 2014-10-28 | Freescale Semiconductor, Inc. | Methods and systems for adjusting NVM cell bias conditions based upon operating temperature to reduce performance degradation |
| KR102215204B1 (ko) * | 2013-11-29 | 2021-02-16 | 삼성디스플레이 주식회사 | 표시 장치, 그 보상 데이터 산출 방법 및 그 구동 방법 |
| US9330790B2 (en) * | 2014-04-25 | 2016-05-03 | Seagate Technology Llc | Temperature tracking to manage threshold voltages in a memory |
| DE102015112276B3 (de) * | 2015-07-28 | 2016-06-30 | Océ Printing Systems GmbH & Co. KG | Verfahren und Vorrichtung zur Verbesserung des Tonertransfers in einem elektrographischen Digitaldrucker |
| US9899450B2 (en) * | 2015-09-15 | 2018-02-20 | The Regents Of The University Of California | Memristors and method for fabricating memristors |
| US10564900B2 (en) * | 2016-03-04 | 2020-02-18 | Western Digital Technologies, Inc. | Temperature variation compensation |
| KR102182583B1 (ko) | 2016-05-17 | 2020-11-24 | 실리콘 스토리지 테크놀로지 인크 | 비휘발성 메모리 어레이를 사용하는 딥러닝 신경망 분류기 |
| US10269440B2 (en) * | 2016-05-17 | 2019-04-23 | Silicon Storage Technology, Inc. | Flash memory array with individual memory cell read, program and erase |
| WO2018150295A1 (ja) * | 2017-02-15 | 2018-08-23 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US10748630B2 (en) | 2017-11-29 | 2020-08-18 | Silicon Storage Technology, Inc. | High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks |
| US11443175B2 (en) * | 2018-07-11 | 2022-09-13 | Silicon Storage Technology, Inc. | Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network |
| US10528643B1 (en) * | 2018-08-01 | 2020-01-07 | Sandisk Technologies Llc | Vector-matrix multiplication using non-volatile memory cells |
| US10755783B2 (en) * | 2018-08-27 | 2020-08-25 | Silicon Storage Technology | Temperature and leakage compensation for memory cells in an analog neural memory system used in a deep learning neural network |
-
2018
- 2018-11-07 US US16/183,250 patent/US10755783B2/en active Active
-
2019
- 2019-07-23 WO PCT/US2019/043101 patent/WO2020046495A1/en not_active Ceased
- 2019-07-23 JP JP2021510952A patent/JP7281535B2/ja active Active
- 2019-07-23 CN CN201980055114.7A patent/CN112602095B/zh active Active
- 2019-07-23 EP EP22201333.6A patent/EP4138079B1/en active Active
- 2019-07-23 KR KR1020217007006A patent/KR102457394B1/ko active Active
- 2019-07-23 EP EP19790890.8A patent/EP3844680B1/en active Active
- 2019-08-20 TW TW108129667A patent/TWI754162B/zh active
-
2020
- 2020-07-16 US US16/930,777 patent/US11158374B2/en active Active
- 2020-11-11 US US17/095,661 patent/US11521682B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359499B1 (en) * | 2000-06-23 | 2002-03-19 | Marvell International Ltd. | Temperature and process independent CMOS circuit |
| CN102684683A (zh) * | 2012-05-14 | 2012-09-19 | 常熟银海集成电路有限公司 | 任意项全系数高精度温度补偿晶体振荡器 |
| CN107533668A (zh) * | 2016-03-11 | 2018-01-02 | 慧与发展有限责任合伙企业 | 用于计算神经网络的节点值的硬件加速器 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP4138079A1 (en) | 2023-02-22 |
| US20210090654A1 (en) | 2021-03-25 |
| JP2021536623A (ja) | 2021-12-27 |
| EP3844680A1 (en) | 2021-07-07 |
| US11521682B2 (en) | 2022-12-06 |
| WO2020046495A1 (en) | 2020-03-05 |
| TW202026955A (zh) | 2020-07-16 |
| US10755783B2 (en) | 2020-08-25 |
| KR102457394B1 (ko) | 2022-10-21 |
| US20200350015A1 (en) | 2020-11-05 |
| TWI754162B (zh) | 2022-02-01 |
| EP3844680B1 (en) | 2022-11-23 |
| CN112602095A (zh) | 2021-04-02 |
| US11158374B2 (en) | 2021-10-26 |
| EP4138079B1 (en) | 2024-08-28 |
| JP7281535B2 (ja) | 2023-05-25 |
| KR20210032538A (ko) | 2021-03-24 |
| US20200066345A1 (en) | 2020-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112602095B (zh) | 用于深度学习神经网络中使用的模拟神经存储器系统中的存储器单元的温度和泄漏补偿 | |
| CN112567391B (zh) | 包括多个矢量-矩阵乘法阵列和共享部件的用于深度学习神经网络的模拟神经存储器系统 | |
| CN112585623B (zh) | 用于深度学习神经网络的可配置模拟神经存储器系统 | |
| CN111837190B (zh) | 用于在深度学习人工神经网络中对模拟神经存储器进行编程的方法和设备 | |
| CN114902339A (zh) | 用于补偿人工神经网络中的模拟神经存储器中的数据漂移的电路 | |
| KR102616977B1 (ko) | 딥 러닝 인공 신경망에서의 아날로그 신경 메모리 내의 기준 트랜지스터들 및 메모리 셀들에 대한 보상 | |
| CN120851100A (zh) | 用于深度学习人工神经网络中的模拟神经存储器的解码系统和物理布局 | |
| CN115968495A (zh) | 用于人工神经网络中的模拟神经存储器阵列的自适应偏置解码器 | |
| CN120660097A (zh) | 包括共模电路的电流-电压转换器 | |
| CN120604240A (zh) | 用于神经网络阵列的多路复用器 | |
| CN117813653A (zh) | 用于深度学习人工神经网络中的模拟神经存储器的输出电路 | |
| CN119744417A (zh) | 人工神经网络阵列中的多行编程操作 | |
| JP2026509342A (ja) | 不揮発性メモリセルの行列によるベクトル乗算アレイのための出力ブロック | |
| CN117751406A (zh) | 可配置为以模拟形式或数字形式存储神经存储器权重数据的混合存储器系统 | |
| CN117178324A (zh) | 用于深度学习人工神经网络中模拟神经存储器的分裂阵列架构 | |
| CN117716427A (zh) | 用于深度学习人工神经网络中的模拟神经存储器的输入电路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |