JP7266352B2 - 垂直型トランジスタのための自己整合された底部スペーサを形成する方法及び半導体デバイス - Google Patents
垂直型トランジスタのための自己整合された底部スペーサを形成する方法及び半導体デバイス Download PDFInfo
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- JP7266352B2 JP7266352B2 JP2020534321A JP2020534321A JP7266352B2 JP 7266352 B2 JP7266352 B2 JP 7266352B2 JP 2020534321 A JP2020534321 A JP 2020534321A JP 2020534321 A JP2020534321 A JP 2020534321A JP 7266352 B2 JP7266352 B2 JP 7266352B2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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Description
SiGe40%+2GeO2→SiGe60%+SiO2+2GeO。GeOは、揮発性種である。
102:分離領域
103:ハードマスク・キャップ
110、111:半導体デバイス(トランジスタ)
120、121:フィン
201:フィン・スペーサ層
404、405、2200、2204:半導体材料
606:犠牲層
707:ゲルマニウム含有層
1110、1112:ゲート誘電体層
1111、1113:仕事関数金属層
1201:平坦化層
1330:誘電体層
1404、1707、2001:酸化物層
1550:上部スペーサ
1990、1991:半導体層
2000:ライナ
2101、2201、2203:底部コンタクト(ソース/ドレイン・コンタクト)
Claims (25)
- 半導体デバイスを製造する方法であって、
基板上にフィンを形成することと、
前記フィンの両側の前記基板上に配置されたソース/ドレイン領域を形成することと、
前記ソース/ドレイン領域上に半導体層を堆積することと、
前記フィン及び前記半導体層上にゲルマニウム含有層を堆積することと、
前記半導体層を前記ゲルマニウム含有層と化学的に反応させ、酸化シリコン層を形成するように構成されたアニール操作を適用することと、
を含む、方法。 - 前記半導体層は、シリコンゲルマニウムを含む、請求項1に記載の方法。
- アニール後、前記酸化シリコン層は、前記半導体層より高いゲルマニウム含有量を含むシリコンゲルマニウム層上に配置される、請求項2に記載の方法。
- 前記シリコンゲルマニウムは、20原子パーセント(%)から60原子パーセント(%)までのゲルマニウムを含む、請求項2に記載の方法。
- より高いゲルマニウム含有量を含む前記シリコンゲルマニウム層は、40原子%から80原子%までのゲルマニウムを含む、請求項3に記載の方法。
- 前記ゲルマニウム含有層は、酸化ゲルマニウムを含む、請求項1に記載の方法。
- 半導体デバイスを形成する方法であって、
基板上にフィンを形成することと、
前記フィンの両側の前記基板上に配置されたソース/ドレイン領域を形成することと、
前記ソース/ドレイン領域上に第1のシリコンゲルマニウム層を堆積することと、
前記フィン及び前記第1のシリコンゲルマニウム層上にゲルマニウム含有層を堆積することと、
アニールを行って、前記第1のシリコンゲルマニウム層を前記ゲルマニウム含有層と化学的に反応させ、前記第1のシリコンゲルマニウム層よりも増大したゲルマニウム含有量を有する第2のシリコンゲルマニウム層上に配置された酸化シリコン層を形成することと、
窒化プロセスを行って、前記酸化シリコン層の窒素含有量を増大させ、底部スペーサを形成することと、
を含む、方法。 - 前記窒化プロセスは、急速熱窒化又はプラズマ窒化を含む、請求項7に記載の方法。
- 前記ゲルマニウム含有層は、GeO2を含む、請求項7に記載の方法。
- 前記窒化プロセスを行った後、前記底部スペーサはSiONを含む、請求項7に記載の方法。
- 前記窒化プロセスを行った後、前記フィンの側壁上の前記ゲルマニウム含有層はGeONを形成する、請求項7に記載の方法。
- 前記GeONを除去し、前記底部スペーサ上に金属ゲートを形成することをさらに含む、請求項11に記載の方法。
- 半導体デバイスを製造する方法であって、
基板上に配置されたソース/ドレイン領域上に第1のシリコンゲルマニウム層を堆積することと、
前記基板上に形成されたフィン及び前記第1のシリコンゲルマニウム層上に酸化ゲルマニウム層を堆積することと、
前記第1のシリコンゲルマニウム層を前記酸化ゲルマニウム層と化学的に反応させて、前記第1のシリコンゲルマニウム層より増大したゲルマニウム含有量を有する第2のシリコンゲルマニウム層上に配置された酸化シリコン層を形成することと、
を含む、方法。 - 前記第2のシリコンゲルマニウム層は、前記第1のシリコンゲルマニウム層よりも20原子%乃至30原子%多いゲルマニウムを含む、請求項13に記載の方法。
- 窒化プロセスを行って、前記酸化シリコン層の窒素含有量を増大させることをさらに含む、請求項13に記載の方法。
- 前記窒化プロセスは、600℃から800℃までの温度で行われる、請求項15に記載の方法。
- 前記窒化プロセスは、前記第2のシリコンゲルマニウム層上にSiON層を形成する、請求項15に記載の方法。
- 前記酸化シリコン層は、純SiO2を含む、請求項13に記載の方法。
- 基板上に配置されたフィンと、
前記フィンに隣接して前記基板上に配置されたソース/ドレイン領域と、
前記ソース/ドレイン領域上に配置されたシリコンゲルマニウム層及び前記シリコンゲルマニウム層上に配置された酸窒化シリコン層を含む底部ゲート・スペーサと、
を含む、半導体デバイス。 - 前記シリコンゲルマニウム層は、40原子%から80原子%までのゲルマニウムを含む、請求項19に記載の半導体デバイス。
- 前記フィンの側壁上に配置されたゲルマニウム含有層をさらに含む、請求項19に記載の半導体デバイス。
- 前記ゲルマニウム含有層は、酸窒化ゲルマニウムを含む、請求項21に記載の半導体デバイス。
- 基板上に配置されたフィンと、
前記フィンの側壁上に配置されたゲルマニウム含有層と、
前記フィンに隣接して前記基板上に配置されたソース/ドレイン領域と、
前記ソース/ドレイン領域上に配置された酸化シリコン層及びシリコンゲルマニウム層を含む底部ゲート・スペーサと、
を含む、半導体デバイス。 - 前記ゲルマニウム含有層は、酸化ゲルマニウムを含む、請求項23に記載の半導体デバイス。
- 前記シリコンゲルマニウム層は、40原子%から80原子%までのゲルマニウムを含む、請求項23に記載の半導体デバイス。
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