CN111480238A - 垂直晶体管的自对准底部间隔物的形成 - Google Patents

垂直晶体管的自对准底部间隔物的形成 Download PDF

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CN111480238A
CN111480238A CN201880081159.7A CN201880081159A CN111480238A CN 111480238 A CN111480238 A CN 111480238A CN 201880081159 A CN201880081159 A CN 201880081159A CN 111480238 A CN111480238 A CN 111480238A
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layer
germanium
silicon
fin
disposed
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CN111480238B (zh
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李忠贤
望月省吾
鲍如强
H.贾甘纳坦
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International Business Machines Corp
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract

一种制造半导体器件的方法，包括在衬底上形成鳍片。在鳍片相对侧上的衬底上布置源极/漏极区域。该方法包括在源极/漏极区域上沉积半导体层。该方法包括在鳍片和半导体层上沉积含锗层。该方法还包括施加退火操作，该退火操作被配置为使半导体层与含锗层化学反应并形成氧化硅层。

Description

垂直晶体管的自对准底部间隔物的形成
背景技术
本发明总体上涉及用于半导体器件的制造方法和所得结构。更具体地，本发明涉及用于垂直晶体管的自对准底部间隔物的形成。
半导体器件是利用晶片的有源区域形成的。有源区域由用于分开和电隔离相邻半导体器件的隔离区域域限定。例如，在具有多个金属氧化物半导体场效应晶体管(MOSFET)的集成电路中，每个MOSFET具有通过在半导体材料层中注入n型或p型杂质而在半导体层的有源区域中形成的源极和漏极。在源极和漏极之间布置的是沟道(或主体)区域。栅电极布置在主体区域之上。栅电极和主体被栅记电介质层隔开。
发明内容
本发明的实施例涉及一种用于制造半导体器件的方法。该方法的非限制性示例包括在衬底上形成鳍片。在鳍片相对侧上的衬底上布置源极/漏极区域。该方法包括在源极/漏极区域上沉积半导体层。该方法包括在鳍片和半导体层上沉积含锗层。该方法还包括施加退火操作，该退火操作被配置为使半导体层与含锗层化学反应并形成氧化硅层。
该方法的另一个非限制性示例包括在衬底上形成鳍片。在鳍片相对侧上的衬底上布置源极/漏极区域。该方法包括在源极/漏极区域上沉积第一硅锗层。该方法包括在鳍片和第一硅锗层上沉积含锗层。该方法还包括退火以使第一硅锗层与含锗层化学反应，并形成布置在第二硅锗层上的氧化硅层，该第二硅锗层具有比第一硅锗层增加的锗含量。该方法包括执行氮化工艺以增加氧化硅层的氮含量并形成底部间隔物。
该方法的另一个非限制性示例包括在布置在衬底上的源极/漏极区域上沉积第一硅锗层。该方法包括在鳍片和第一硅锗层上沉积氧化锗层。该方法还包括使第一硅锗层与氧化锗层化学反应以形成第二氧化硅层，该氧化硅层布置在第二锗锗层上，该第二锗锗层具有比第一硅锗层增加的锗含量。
本发明的实施例涉及一种半导体器件。半导体器件的非限制性示例包括布置在衬底上的鳍片。该半导体器件包含布置在衬底上与鳍片相邻的源极/漏极区域。该半导体器件还包含底部栅极间隔物，该底部栅极间隔物包含布置在源极/漏极区域上的硅锗层和布置在硅锗层上的氮氧化硅层。
半导体器件的另一个非限制性示例包括布置在衬底上的鳍片和布置在鳍片的侧壁上的含锗层。该半导体器件包含布置在衬底上与鳍片相邻的源极/漏极区域。该半导体器件还包含底部栅极间隔物，该底部栅极间隔物包含布置在源极/漏极区域上的氧化硅层和硅锗层。
通过本发明的技术实现了附加的技术特征和益处。本文详细描述本发明的实施例和各个方面，并且将其视为所要求保护的主题的一部分。为了更好的理解，请参考具体实施方式和附图。
附图说明
在说明书的结尾处的权利要求书中特别指出并明确要求保护本文所述的专有权的细节。通过以下结合附图的具体实施方式，本发明的实施例的前述以及其他特征和优点将变得显而易见，其中：
图1-22示出了根据本发明实施例的制造半导体器件的方法，其中：
图1示出了在衬底上形成有鳍片的半导体器件的截面侧视图；
图2示出了在鳍片上沉积鳍片间隔层之后的截面侧视图；
图3示出了使鳍片凹陷的截面侧视图；
图4示出了沉积半导体材料之后的截面侧视图；
图5示出了退火之后的截面侧视图；
图6示出了沉积牺牲层之后的截面侧视图；
图7示出了沉积含锗层之后的截面侧视图；
图8示出了退火之后的截面侧视图；
图9示出了在执行氮化工艺之后的截面侧视图；
图10示出了从鳍片去除含锗层之后的截面侧视图；
图11示出了在预清洁和沉积栅极电介质层和功函数金属层之后的截面侧视图；
图12示出了在沉积平坦化层并对栅极堆叠构图之后的截面侧视图；
图13示出了在去除平坦化层并沉积电介质层之后的截面侧视图；
图14示出了沉积氧化物层之后的截面侧视图；
图15示出了在形成顶部间隔物之后的截面侧视图；
图16示出了隔离晶体管之后的截面侧视图；
图17示出了沉积氧化物层之后的截面侧视图；
图18示出了使氧化物层凹陷后的截面侧视图；
图19示出了在沉积半导体层之后的截面侧视图；
图20示出了在沉积衬里和另一氧化物层之后的截面侧视图；
图21示出了根据实施例的在形成触点之后的截面侧视图；以及
图22示出了根据实施例的在形成触点之后的截面侧视图。
本文所描绘的图是说明性的。在不脱离本发明的精神的情况下，本文描述的图或操作可以有许多变化。例如，可以以不同的顺序执行动作，或者可以添加、删除或修改动作。同样，术语“耦合”及其变型描述了在两个元件之间具有通信路径，并且并不意味着元件之间的直接连接，而在它们之间没有中间元件/连接。所有这些变体都被视为说明书的一部分。
在附图和以下对所描述的实施例的具体实施方式中，在附图中示出的各个元件设置有两位或三位附图标记。除少数例外，每个附图标记的最左边的数字与该元素的第一个插图相对应。
具体实施方式
为了简洁起见，本文中可能会或可能不会详细描述与半导体器件和集成电路(IC)制造相关的常规技术。此外，本文描述的各种任务和工艺步骤可以被合并到具有本文未详细描述的附加步骤或功能的更全面的过程或工艺中。特别地，半导体器件和基于半导体的IC的制造中的各个步骤是众所周知的，因此，为了简洁起见，本文将仅简要提及许多常规步骤，或者将在不提供众所周知的工艺细节的情况下将其完全省略。
现在转向与本发明的各个方面更具体相关的技术的概述，因为将MOSFET缩放到较小的尺寸，所以采用了各种设计和技术来改善器件性能。其中源极/漏极区域布置在被栅极围绕的垂直沟道区域(或鳍片)的相对端上的垂直晶体管是用于缩小尺寸的有吸引力的候选者。因此，垂直晶体管可以提供更高的密度缩放比例，从而减轻线中(MOL)制造的复杂性。
在垂直晶体管中，顶部和底部栅极间隔物分别布置在栅极与顶部和底部源极/漏极区域之间。栅极间隔物可以包含氮化硅和/或氧化硅，这两者都会带来挑战。可以使用高密度等离子体(HDP)形成氮化硅间隔物，HDP会引起鳍片通道的氧化硅侧壁衬里氮化，从而在鳍片侧壁上形成SiON。鳍片侧壁上的SiON可能难以通过蚀刻去除，这也可能导致底部间隔物和鳍片硬掩模(二者都包含氮化硅)的非选择性蚀刻。尽管使用氧化硅作为底部间隔物可以避免鳍片侧壁的上述氮化以及由此产生的蚀刻非选择性，但是使用氧化硅提出了另一组挑战。在将氧化硅沉积在衬底和鳍片上并回蚀以形成底部间隔物之后，间隔物的形状可以在鳍片与衬底的界面处为弯月形，这会导致栅极可控性的损失。由于这些原因，优选氮化硅底部间隔物。
现在转向本发明的各个方面的概述，本发明的一个或多个实施例通过提供一种形成SiON底部间隔物的方法来解决现有技术的上述缺点。在本发明的实施例中，通过使氧化锗(GeO2)与硅锗(SiGe)反应并退火以形成氧化硅(SiO2)底部间隔物层来形成SiON底部间隔层。氮化氧化硅层以形成SiON底部间隔物。
本发明的上述各个方面通过提供一种简单有效的方法来确保用于NFET和PFET器件的SiON底部间隔物层的厚度基本相等且均匀，而没有任何构图，从而解决了现有技术的缺点。底部间隔物的均匀厚度在器件中提供了可预测的准确通道长度。该方法提供了一种结构，该结构减轻了在去除鳍片侧壁衬里期间鳍片硬掩模和底部间隔物的损失。
现在转向对本发明各方面的更详细描述。图1-22示出了根据本发明实施例的制造半导体器件的方法。图1示出了在衬底101上形成有鳍片120、121的半导体器件的截面侧视图。第一鳍片120是第一半导体器件120的一部分，第二鳍片121是第二半导体器件的一部分。根据示例性实施例，第一半导体器件110是NFET，并且第二半导体器件111是PFET。
合适的衬底101材料的非限制性示例包括Si(硅)、应变Si、SiC(碳化硅)、Ge(锗)、SiGe(硅锗)、SiGeC(硅锗碳)、Si合金、Ge合金、III-V材料(例如GaAs(砷化镓)、InAs(砷化铟)、InP(磷化铟)或砷化铝(AlAs))、II-VI材料(例如CdSe(硒化镉)、CdS(硫化镉)、CdTe(碲化镉)、ZnO(氧化锌)、ZnSe(硒化锌)、ZnS(硫化锌)或ZnTe(碲化锌))或其任意组合。
鳍片120，121均包含硬掩模盖103。鳍片120，121可以通过在衬底101上沉积硬掩模材料，随后构图和蚀刻而在衬底101中形成。鳍片110还可以通过例如侧壁成像转印在衬底中构图。
隔离区域102在第一晶体管110和第二晶体管111的有源区域之间形成。隔离区域102可以通过本领域中任何已知的方法形成，包含例如光刻和刻蚀以在衬底101中形成沟槽，然后用诸如二氧化硅的绝缘材料填充沟槽。在形成隔离区域102之后，将有源区域定义为一对隔离区域之间的区域。根据一个或多个实施例，隔离区域102是浅沟槽隔离区域(STI)。然而，隔离区域可以是沟槽隔离区域、场氧化物隔离区域(未示出)或本领域中已知的任何其他等效物。隔离区域102在相邻的栅极结构区域之间提供隔离，并且可以在相邻的栅极具有相反的电导率时(例如NFET和PFET)使用。这样，至少一个隔离区域可以将NFET器件区域与PFET器件区域分开。
图2示出了在鳍片120、121上沉积鳍片间隔物层201之后的截面侧视图。鳍片间隔物层201是鳍片120、121的侧壁上的保护层间隔物。沉积鳍片120、121上的鳍片间隔物层201后，蚀刻鳍片间隔物层201以暴露鳍片120、121(或硬掩模帽103)的顶表面。
鳍片间隔物层201的材料的非限制性示例包括电介质氧化物(例如，氧化硅)，电介质氮化物(例如，氮化硅)，电介质氮氧化物或它们的任意组合。通过诸如化学气相沉积(CVD)或物理气相沉积(PVD)的沉积工艺来沉积间隔物材料。间隔物材料可以通过干法蚀刻工艺(例如RIE工艺)来蚀刻。
图3示出了使鳍片120、121凹陷的截面侧视图。鳍片120、121的底部在与衬底101的界面处凹陷。鳍片间隔层201保留在适当位置以保护有源鳍片并避免从鳍片120、121的侧壁表面形成底部源极/漏极(见图4)。垂直蚀刻衬底101的表面以暴露鳍片120、121的侧壁表面。
图4示出了在衬底101上沉积半导体材料404、405以形成底部源极/漏极之后的截面侧视图。半导体材料405形成第一晶体管110的底部源极/漏极，并且半导体材料404形成第二晶体管111的底部源极/漏极。
根据一个或多个实施例，半导体材料404，405是外延生长的半导体材料。鳍片侧壁上的鳍片间隔层201在外延生长过程中保护鳍片免于半导体材料的沉积。外延层可以从气态或液态前体生长。可以使用气相外延(VPE)、分子束外延(MBE)、液相外延(LPE)或其他合适的工艺来生长外延生长。例如，可以在沉积期间在外延硅、硅锗和/或碳掺杂的硅(Si：C)中通过添加掺杂剂或杂质形成硅化物来对其进行掺杂。取决于晶体管的类型，半导体材料404、405掺杂有n型掺杂剂(例如，磷、砷或锑)或p型掺杂剂(例如，硼)。
在一些示例性实施例中，第一晶体管110是NFET，并且半导体材料405是掺杂有磷的外延生长的硅。在其他示例性实施例中，第二晶体管111是PFET，并且半导体材料404是掺杂有硼的外延生长的硅锗。
图5示出了退火后的截面侧视图。进行退火以将掺杂剂从半导体材料404、405驱动到源极/漏极结处的衬底101和鳍片120、121中。源极/漏极区域被布置在每个鳍片120、121的相对侧上的衬底101上。
例如，通过在炉内加热或在包含纯惰性气体(例如，氮气或氩气)的气氛中进行快速热处理来进行退火。退火工艺可以是例如快速热退火(RTA)或快速热处理(RTP)。
图6示出了在源极/漏极区域的半导体材料404、405上沉积牺牲层606之后的截面侧视图。牺牲层606是未掺杂的半导体材料，并且在第一晶体管110和第二晶体管111的源极/漏极区域上形成。牺牲层606被沉积在半导体材料404、405和两个晶体管上。
根据一个或多个实施例，牺牲层606是未掺杂的外延生长的硅锗。根据一些实施例，硅锗层包含约20至约40原子％的锗。根据其他实施例，硅锗层包含约20至约60原子％的锗。因为其他暴露的表面被电介质覆盖，所以在包含隔离区域102的其他暴露的表面上不会发生外延生长。
图7示出了在鳍片120、121和源极/漏极区域上的牺牲层606上沉积含锗层707之后的截面侧视图。含锗层707是保形的。
根据一个或多个实施例，通过原子层沉积(ALD)沉积含锗层，并且包含氧化锗(GeO2)。含锗层707的厚度通常是变化的，并且不希望受到限制。然而，根据一些实施例，含锗层707具有约4至约8nm的厚度。
图8示出了退火后的截面侧视图。退火引起牺牲层606的材料和含锗层707的材料之间的化学反应，从而形成层707a和606a。层606a和707a各自包含由牺牲层606和含锗层707的反应产生的化学反应产物。在鳍片120、121的侧壁上的含锗层707保持未反应。
退火例如通过在炉内加热或在包含纯惰性气体(例如，氮气或氩气)的气氛中进行快速热处理来进行。在示例性实施例中，在环境N2环境中在约400至约650℃下执行退火约1至30秒。
在一些示例性实施例中，在退火之前，牺牲层606包含具有40原子％的锗的硅锗，并且含锗层707包含氧化锗。退火之后，硅锗层的锗含量增加约20至30原子％，以形成层606a，该层包含具有60至70原子％的锗的硅锗。退火之后，层707a然后包含基本上纯的氧化硅(SiO2)的顶层。在实施方案中发生以下反应：SiGe 40％+2GeO2→SiGe 60％+SiO2+2GeO。GeO是挥发性物质。
在其他示例性实施例中，牺牲层606包含具有约20至约60原子％的锗的硅锗，并且在退火之后，硅锗层的锗含量增加以形成具有约40至约80原子％的锗的层606a。来自含锗层707的锗向下移动到牺牲层606(形成层606a)中，并且在顶表面上形成纯氧化硅层，将其进一步处理以形成底部栅极间隔物。
图9示出了可选地执行氮化过程之后的截面侧视图。氮化工艺将氮添加到鳍片侧壁上的含锗层707中，形成层201a，并添加到源极/漏极区域上的层707a中，从而形成层707b。根据一个或多个实施例，层201a包含氮氧化锗(GeON)，并且层707b包含SiON。向氧化硅中添加氮以形成SiON是有利的，因为它比氧化硅更稳定。鳍片侧壁上包含GeON的层201a也容易被洗去以暴露鳍片120、121。
根据一些实施例，通过在低温下快速热氮化(RTN)来执行氮化工艺。RTN可以在例如大约NH3的环境气氛中在例如大约600至大约800℃的温度下进行。根据其他实施例，通过等离子体氮化来执行氮化工艺。
图10示出了从鳍片侧壁去除层201a之后的截面侧视图。当层201a包含GeON时，可以通过例如用去离子水洗涤/蚀刻来去除层201。然后暴露鳍片120、121的侧壁和硬掩模103，从而在源极/漏极区域上留下层707b。层707b将形成底部栅极间隔物。
图11示出了在预清洁和沉积栅极电介质层1110、1112和功函数金属层1111、1113之后的截面侧视图。栅极电介质层1110、1112和功函数金属层1111、1113是其中的一部分栅极堆叠。
在沉积栅极堆叠层之前，执行预清洁以去除化学残留物。所述预清洁工艺可以包含轻的、非选择性的、非反应性的蚀刻，例如等离子体蚀刻。根据一些实施例，预清洁包含氢氟酸(HF)和盐酸(HCl)。
栅极电介质层1110、1112和功函数金属层1111、1113对于晶体管的类型是特定的。栅极介电材料可以是介电常数大于约3.9，约7.0或约10.0的介电材料。用于介电材料的合适材料的非限制性示例包括氧化物，氮化物、氧氮化物、硅酸盐(例如金属硅酸盐)、铝酸盐、钛酸盐、氮化物或其任意组合。高k材料(介电常数大于7.0)的示例包含但不限于金属氧化物，例如氧化铪、氧化硅铪铪、氮氧化铪硅、氧化镧、氧化铝镧、氧化锆、锆硅氧化物、锆氮氧化硅、钽氧化物、钛氧化物、锶锶钛氧化物、钡钛氧化物、锶钛氧化物、钇氧化物、氧化铝、钽钽酸铅和铌酸铅锌。高k材料可以进一步包含掺杂剂，例如镧和铝。
功函数金属层1111、1113布置在栅极介电材料上。功函数金属的类型取决于晶体管的类型并且可以在第一晶体管110和第二晶体管111之间不同。合适的功函数金属的非限制性示例包括p型功函数金属材料和n型功函数金属材料。P型功函数材料包含诸如氮化钛(TiN)、氮化钽(TaN)、钌、钯、铂、钴、镍和导电金属氧化物或其任意组合的成分。N型金属材料包含诸如铪、锆、钛、钽、铝、金属碳化物(例如碳化铪、碳化锆、碳化钛和碳化铝)、铝化物或它们的任意组合的成分。可以通过合适的沉积工艺(例如，CVD、PECVD、PVD、电镀、热或电子束蒸发以及溅射)来沉积功函数金属。
图12示出了在沉积平坦化层1201和对栅极堆叠构图之后的截面侧视图。平坦化层1201可以是旋涂或有机平坦化层(OPL)。平坦化层1201沉积在鳍片120、121和衬底101上，然后例如通过蚀刻而凹陷。栅极电介质层1110、1112和功函数金属层1111、1113被暴露并且可以通过一种或多种蚀刻工艺来蚀刻，使得如果需要的话，它们被凹陷在硬掩模盖103下方。
图13示出了在去除平坦化层1201并沉积电介质层1330之后的截面侧视图。电介质层1330封装了鳍片120，121和围绕鳍片的栅极堆叠。根据一个或多个实施例，电介质层1330包含电介质氧化物(例如，氧化硅)、电介质氮化物(例如，氮化硅)、电介质氮氧化物或其任意组合。
图14示出在沉积氧化物层1404(层间电介质(ILD))之后的截面侧视图。氧化物层1404可以包含但不限于原硅酸四乙酯(TEOS)氧化物、高纵横比等离子体(HARP)氧化物、高温氧化物(HTO)、高密度等离子体(HDP)氧化物、通过原子层沉积(ALD)工艺形成的氧化物(例如，氧化硅)或其任意组合。在鳍片120、121上的硬掩模盖103的水平下方氧化物层1404部分凹陷。
图15示出了在栅极堆叠的顶部上形成顶部间隔物1550之后的截面侧视图。顶部间隔物1550包含绝缘材料，例如二氧化硅、氮化硅、SiOCN或SiBCN。顶部间隔物1550的材料的其他非限制性示例包括电介质氧化物(例如，氧化硅)、电介质氮化物(例如，氮化硅)、电介质氮氧化物或其任意组合。在沉积之后，间隔物材料被蚀刻。
图16示出了在隔离两个晶体管110和111之后的截面侧视图。使用顶部间隔物1550作为图案来蚀刻氧化物层1404。去除在晶体管110、111之间的隔离区域102上方的栅极电介质层1110、1112、功函数金属层1111、1113和电介质层1330的部分，从而暴露出隔离区域102。
图17示出了沉积氧化物层1707之后的截面侧视图。氧化物层1707可包含但不限于原硅酸四乙酯(TEOS)氧化物、高纵横比等离子体(HARP)氧化物、高温氧化物(HTO)、高密度等离子体(HDP)氧化物、通过原子层沉积(ALD)工艺形成的氧化物(例如，氧化硅)或其任意组合。
图18示出了在使氧化物层1707凹陷之后的截面侧视图。将氧化物层1707凹陷到鳍片硬掩模盖103下方的水平。还去除了硬掩模盖103，并且使顶部间隔物1550部分地凹陷以暴露鳍片120、121的顶部，在鳍片120、121的顶部将形成顶部源极/漏极。
图19示出了分别在鳍片120、121上沉积半导体层1990、1991之后的截面侧视图。半导体材料1990、1991形成顶部源极/漏极，并且可以包含外延半导体材料，如以上关于图4所描述的。如上面相对于图5所描述的，外延半导体材料可以包含掺杂剂，并且退火可以用于将掺杂剂驱入到顶部源极/漏极区域的鳍片120、121中。
图20示出了在顶部源极/漏极上沉积衬里2000和另一个氧化物层2001(ILD)之后的截面侧视图。衬里2000封装了源极/漏极。当形成顶部源极/漏极触点时，衬里2000用作蚀刻停止衬里。
图21示出了根据实施例的在形成底部触点2101(源极/漏极触点)之后的截面侧视图。可以选择性地蚀刻包含高或增加的锗含量的层606a，以提供用于底部触点2101的大接触面积。通过蚀刻沟槽，在氧化物层2001、1707中形成底部触点2101。底部源极/漏极接触2101延伸穿过氧化物层2001、1707并到达形成底部源极/漏极区域的半导体材料404、405。可以沉积抗蚀剂(例如光刻胶)，并对其进行构图以形成接触沟槽。执行诸如RIE的蚀刻工艺以去除氧化物层2001、1707、层707b和层606a。接触沟槽填充有导电材料或导电材料的组合。因为层606a包含高锗含量，所以层606a用作蚀刻停止层。在蚀刻工艺中将去除更多的层606a，这导致形成倒“T”形触点。蚀刻工艺将在半导体材料404、405上停止。导电材料(例如导电金属，例如铝(A1)、铂(Pt)、金(Au)、钨(W)、钛(Ti)、钴(Co)或其任何组合)沉积在沟槽中。
图22示出了根据实施例的在形成底部触点2201、2203之后的截面侧视图。在氧化物层2001、1707中形成沟槽之后，并且在沉积触点金属之前，分别在半导体材料405和404上沉积半导体材料2200和2204。
根据一些实施例，半导体材料2200、2204是外延生长的半导体材料。在一个或多个实施例中，外延生长的半导体材料2200与第一晶体管110中的半导体材料405相同。在一些实施例中，半导体材料405和半导体材料2200掺杂有磷。在一些实施例中，半导体材料2204是掺杂有镓的外延生长的锗。
在此参考相关附图描述了本发明的各种实施例。在不脱离本发明范围的情况下，可以设计出替代实施例。尽管在以下描述和附图中在元件之间阐述了各种连接和位置关系(例如，在上方，下方，相邻等)，但是本领域技术人员将认识到，本文所述的许多位置关系是定向的-即使更改了方向，在保持所描述的功能时也可以独立使用。除非另有说明，否则这些连接和/或位置关系可以是直接的或间接的，并且本发明并不意图在这方面进行限制。因此，实体的耦合可以指直接或间接耦合，并且实体之间的位置关系可以是直接或间接的位置关系。作为间接位置关系的示例，在本说明书中提及在层“B”上形成层“A”包含其中一个或多个中间层(例如，层“C”)在层“A”和层“B”之间的情况，只要中间层基本不改变层“A”和层“B”的相关特征和功能。
以下定义和缩写用于解释权利要求和说明书。如本文所使用的，术语“包含(现在时)”，“包含(进行时)”，“包括(现在时)”，“包括(进行时)”，“具有(现在时)”，“具有(进行时)”，“含有(现在时)”或“含有(进行时)”或其任何其他变型旨在涵盖非-独家包容。例如，包含一系列元素的组合物、混合物、过程、方法、物品或设备不一定仅限于那些元素，而是可以包含未明确列出或对此类组合物、混合物、过程、方法、物品或设备所固有的其他元素。
另外，术语“示例性”在本文中用于表示“用作示例、实例或说明”。本文中被描述为“示例性”的任何实施例或设计不必被解释为比其他实施例或设计更优选或有利。术语“至少一个”和“一个或多个”应理解为包含大于或等于一的任何整数，即一个、两个、三个、四个等。术语“多个”应理解为包含大于或等于2的任何整数，即两个、三个、四个、五个等。术语“连接”可以包含间接“连接”和直接“连接”。
在说明书中对“一个实施例”，“一个实施例”，“示例实施例”等的引用指示所描述的实施例可以包含特定的特征、结构或特性，但是每个实施例可以包含或可以不包含特定的特征、结构或特征。而且，这样的短语不一定指相同的实施例。此外，当结合一个实施例描述特定的特征、结构或特性时，可以认为无论是否明确地结合其他实施例影响这种特征、结构或特性，都属于本领域技术人员的知识范围。
为了下文描述的目的，术语“上部”、“下部”、“右侧”、“左侧”、“垂直”、“水平”、“顶部”、“底部”及其派生词应与以附图为导向的所描述的结构和方法。术语“覆盖”、“顶部”，“在顶部”、“位于...之上”或“位于顶部”是指第一元素(例如第一结构)存在于第二元素(例如第二结构)上，其中在第一元件和第二元件之间可以存在诸如界面结构的中间元件。术语“直接接触”是指第一元件(例如第一结构)和第二元件(例如第二结构)在两个元件的界面处没有任何中间导电、绝缘或半导体层的情况下被连接。
短语“对......有选择性”，例如“对第二元素有选择性的第一元素”，是指可以蚀刻第一元素，并且第二元素可以用作蚀刻停止层。
术语“大约”、“基本上”、“约莫”及其变体旨在包含与基于提交申请时可用的设备的特定数量的测量相关的误差程度。例如，“约”可以包含给定值的±8％或5％或2％的范围。
如本文先前所指出，为了简洁起见，本文中可能会或可能不会详细描述与半导体器件和集成电路(IC)制造相关的常规技术。然而，通过背景技术，现在将提供可用于实现本发明的一个或多个实施例的半导体器件制造工艺的更一般的描述。尽管可以单独知道用于实现本发明的一个或多个实施例的特定制造操作，但是所描述的本发明的操作和/或所得结构的组合是独特的。因此，结合根据本发明的半导体器件的制造所描述的操作的独特组合利用了在半导体(例如，硅)衬底上执行的各种单独已知的物理和化学过程，其中一些在下文中紧接着的段落描述。
通常，用于形成将被封装到IC中的微芯片的各种工艺分为四大类，即膜沉积、去除/蚀刻、半导体掺杂和构图/光刻。沉积是将材料生长、涂覆或以其他方式转移到晶片上的任何过程。可用的技术包含物理气相沉积(PVD)、化学气相沉积(CVD)、电化学沉积(ECD)、分子束外延(MBE)以及最近的原子层沉积(ALD)等。去除/蚀刻是从晶片去除材料的任何工艺。示例包含蚀刻工艺(湿法或干法)和化学机械平坦化(CMP)等。半导体掺杂通过掺杂例如晶体管的源极和漏极(通常通过扩散和/或通过离子注入)来改变电性能。这些掺杂过程之后是炉子退火或快速热退火(RTA)。退火用于激活注入的掺杂剂。导体(例如，多晶硅、铝，铜等)和绝缘体(例如，各种形式的二氧化硅、氮化硅等)的二者的膜都用于连接和隔离晶体管及其组件。半导体衬底的各个区域的选择性掺杂允许衬底的电导率随着施加的电压而改变。通过创建这些各种组件的结构，可以构建数百万个晶体管并将其布线在一起，以形成现代微电子器件的复杂电路。半导体光刻是在半导体衬底上形成三维浮雕图像或图案，以便随后将图案转移到衬底上。在半导体光刻中，图案由称为光致抗蚀剂的光敏聚合物形成。为了构建组成晶体管的复杂结构以及连接电路中数百万个晶体管的许多导线，光刻和蚀刻图案转移步骤要重复多次。印刷在晶片上的每个图案都与先前形成的图案对齐，然后慢慢地建立导体、绝缘体和选择性掺杂的区域，以形成最终的器件。
附图中的流程图和框图示出了根据本发明的各个实施例的制造和/或操作方法的可能的实施方式。该方法的各种功能/操作在流程图中由框表示。在一些替代实施方式中，方框中指出的功能可以不按图中指出的顺序发生。例如，取决于所涉及的功能，实际上可以基本上同时执行连续示出的两个框，或者有时可以以相反的顺序执行这些框。
为了说明的目的已经给出了对本发明的各种实施例的描述，但是这些描述并不旨在是穷举的或限于所描述的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。选择本文使用的术语是为了最好地解释实施例的原理，对市场上发现的技术的实际应用或技术上的改进，或使本领域的其他普通技术人员能够理解本文所述的实施例。

Claims (25)

1.一种制造半导体器件的方法，所述方法包括：
在衬底上形成鳍片；
在所述鳍片的相对侧上形成布置在所述衬底上的源极/漏极区域；
在所述源极/漏极区域上沉积半导体层；
在所述鳍片和所述半导体层上沉积含锗层；以及
施加退火操作，所述退火操作被配置为使所述半导体层与所述含锗层化学反应并形成氧化硅层。
2.如权利要求1所述的方法，其中，所述半导体层包含硅锗。
3.如权利要求2所述的方法，其中，在退火之后，将所述氧化硅层布置在硅锗层上，所述硅锗层包含比所述半导体层高的锗含量。
4.如权利要求2所述的方法，其特征在于，所述硅锗包含约20至约60原子百分比(％)的锗。
5.如权利要求3所述的方法，其中，包含较高含量的锗的所述硅锗层包含约40至约80原子％的锗。
6.如权利要求1所述的方法，其中，所述含锗层包含氧化锗。
7.一种形成半导体器件的方法，所述方法包括：
在衬底上形成鳍片；
在所述鳍片的相对侧上形成布置在所述衬底上的源极/漏极区域；
在所述源极/漏极区域上沉积第一硅锗层；
在所述鳍片和所述第一硅锗层上沉积含锗层；
退火以使所述第一硅锗层与所述含锗层发生化学反应，并形成布置在第二硅锗层上的氧化硅层，所述第二硅锗层具有比所述第一硅锗层增加的锗含量；以及
进行氮化工艺以增加所述氧化硅层的氮含量并形成底部间隔物。
8.如权利要求7所述的方法，其中，所述氮化工艺包含快速热氮化或等离子体氮化。
9.如权利要求7所述的方法，其中，所述含锗层包含GeO2。
10.如权利要求7所述的方法，其中，在执行所述氮化工艺之后，所述底部间隔物包含SiON。
11.如权利要求7所述的方法，其中，在执行所述氮化工艺之后，在所述鳍片的侧壁上的所述含锗层形成GeON。
12.如权利要求11所述的方法，还包含去除所述GeON并在所述底部间隔物上形成金属栅极。
13.一种制造半导体器件的方法，所述方法包括：
在布置在衬底上的源极/漏极区域上沉积第一硅锗层，
在鳍片和所述第一硅锗层上沉积氧化锗层；以及
使所述第一硅锗层与所述氧化锗层化学反应以形成布置在第二硅锗层上的氧化硅层，所述第二硅锗层具有比所述第一硅锗层增加的锗含量。
14.如权利要求13所述的方法，其中，所述第二硅锗层比所述第一硅锗层包含的锗多约20至约30原子％。
15.如权利要求13所述的方法，还包含执行氮化工艺以增加所述氧化硅层的氮含量。
16.如权利要求15所述的方法，其中所述氮化工艺在约600至约800℃的温度下进行。
17.如权利要求13所述的方法，其中，所述氮化工艺在所述第二硅锗层上形成SiON层。
18.如权利要求13所述的方法，其中，所述氧化硅层包含基本上纯的SiO2。
19.一种半导体器件，包括：
布置在衬底上的鳍片；
布置在所述衬底上与所述鳍片相邻的源极/漏极区域；以及
包含布置在所述源极/漏极区域上的硅锗层和布置在所述硅锗层上的氮氧化硅层的底部栅极间隔物。
20.如权利要求19所述的半导体器件，其中所述硅锗层包含约40至约80原子％的锗。
21.如权利要求19所述的半导体器件，还包含布置在所述鳍片的侧壁上的含锗层。
22.如权利要求19所述的半导体器件，其中所述含锗层包含氮氧化锗。
23.一种半导体器件，包括：
布置在衬底上的鳍片；
布置在所述鳍片的侧壁上的含锗层；
布置在所述衬底上与所述鳍片相邻的源极/漏极区域；以及
包含布置在所述源极/漏极区域上的氧化硅层和硅锗层的底部栅极间隔物。
24.如权利要求23所述的半导体器件，其中所述含锗层包含氧化锗。
25.如权利要求23所述的半导体装置，其中所述硅锗层包含约40至约80原子％的锗。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117135923B (zh) * 2023-10-23 2024-01-26 北京超弦存储器研究院 半导体结构及其制备方法、电子设备

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10541273B2 (en) * 2017-11-28 2020-01-21 Sandisk Technologies Llc Vertical thin film transistors with isolation
US10276687B1 (en) 2017-12-20 2019-04-30 International Business Machines Corporation Formation of self-aligned bottom spacer for vertical transistors
US10930758B2 (en) * 2018-08-13 2021-02-23 International Business Machines Corporation Space deposition between source/drain and sacrificial layers
US20200135585A1 (en) * 2018-10-29 2020-04-30 International Business Machines Corporation Maskless top source/drain epitaxial growth on vertical transport field effect transistor
US20200135873A1 (en) * 2018-10-30 2020-04-30 International Business Machines Corporation Device variation control of vertical transport fin field effect transistor devices by selective oxide deposition for shallow trench isolation formation
US11309405B2 (en) * 2019-06-18 2022-04-19 Samsung Electronics Co., Ltd. Vertical field effect transistor device having protruded shallow trench isolation and method for manufacturing the same
US11355633B2 (en) * 2020-01-03 2022-06-07 International Business Machines Corporation Vertical field effect transistor with bottom source-drain region
US11515427B2 (en) * 2020-06-15 2022-11-29 International Business Machines Corporation Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance
US11521894B2 (en) * 2020-07-18 2022-12-06 International Business Machines Corporation Partial wrap around top contact
CN112271161A (zh) * 2020-10-26 2021-01-26 上海华力集成电路制造有限公司 一种改善鳍式晶体管Fin尺寸的方法
US11757036B2 (en) 2021-07-29 2023-09-12 International Business Machines Corporation Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices
US20230107182A1 (en) * 2021-10-05 2023-04-06 International Business Machines Corporation Bottom Air Spacer by Oxidation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627511B1 (en) * 2016-06-21 2017-04-18 International Business Machines Corporation Vertical transistor having uniform bottom spacers
US9647112B1 (en) * 2016-09-22 2017-05-09 International Business Machines Corporation Fabrication of strained vertical P-type field effect transistors by bottom condensation
US9773901B1 (en) * 2016-10-26 2017-09-26 International Business Machines Corporation Bottom spacer formation for vertical transistor
US20170288039A1 (en) * 2016-03-31 2017-10-05 International Business Machines Corporation Fabrication of vertical field effect transistor structure with controlled gate length

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2868202B1 (fr) * 2004-03-25 2006-05-26 Commissariat Energie Atomique Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium.
EP1659623B1 (en) * 2004-11-19 2008-04-16 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for fabricating a germanium on insulator (GeOI) type wafer
US20090166770A1 (en) * 2008-01-02 2009-07-02 International Business Machines Corporation Method of fabricating gate electrode for gate of mosfet and structure thereof
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
EP2378557B1 (en) * 2010-04-19 2015-12-23 Imec Method of manufacturing a vertical TFET
US8753942B2 (en) * 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
JP5232261B2 (ja) * 2011-03-25 2013-07-10 株式会社東芝 電界効果トランジスタ及びその製造方法
US9171715B2 (en) * 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
US8957476B2 (en) * 2012-12-20 2015-02-17 Intel Corporation Conversion of thin transistor elements from silicon to silicon germanium
US9368619B2 (en) * 2013-02-08 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for inducing strain in vertical semiconductor columns
US9093326B2 (en) 2013-10-21 2015-07-28 International Business Machines Corporation Electrically isolated SiGe fin formation by local oxidation
US9112033B2 (en) * 2013-12-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure of semiconductor device
US9379218B2 (en) * 2014-04-25 2016-06-28 International Business Machines Corporation Fin formation in fin field effect transistors
US9577101B2 (en) * 2015-03-13 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain regions for fin field effect transistors and methods of forming same
US9530700B1 (en) 2016-01-28 2016-12-27 International Business Machines Corporation Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch
US9728466B1 (en) 2016-04-28 2017-08-08 International Business Machines Corporation Vertical field effect transistors with metallic source/drain regions
US9755073B1 (en) 2016-05-11 2017-09-05 International Business Machines Corporation Fabrication of vertical field effect transistor structure with strained channels
US9773875B1 (en) 2016-07-20 2017-09-26 International Business Machines Corporation Fabrication of silicon-germanium fin structure having silicon-rich outer surface
US9911804B1 (en) * 2016-08-22 2018-03-06 International Business Machines Corporation Vertical fin field effect transistor with air gap spacers
US9741716B1 (en) 2016-09-23 2017-08-22 International Business Machines Corporation Forming vertical and horizontal field effect transistors on the same substrate
US10276687B1 (en) 2017-12-20 2019-04-30 International Business Machines Corporation Formation of self-aligned bottom spacer for vertical transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170288039A1 (en) * 2016-03-31 2017-10-05 International Business Machines Corporation Fabrication of vertical field effect transistor structure with controlled gate length
US9627511B1 (en) * 2016-06-21 2017-04-18 International Business Machines Corporation Vertical transistor having uniform bottom spacers
US9647112B1 (en) * 2016-09-22 2017-05-09 International Business Machines Corporation Fabrication of strained vertical P-type field effect transistors by bottom condensation
US9773901B1 (en) * 2016-10-26 2017-09-26 International Business Machines Corporation Bottom spacer formation for vertical transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117135923B (zh) * 2023-10-23 2024-01-26 北京超弦存储器研究院 半导体结构及其制备方法、电子设备

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