JP7262945B2 - GATE DRIVE CIRCUIT AND DRIVING METHOD OF VOLTAGE DRIVE WIDE GAP SEMICONDUCTOR - Google Patents

Description

The present invention relates to a gate drive circuit for a voltage-driven wide-gap semiconductor device.

IGBTs (Insulated Gate Bipolar Transistors), which are capable of high-speed switching and high-power control, are widely used in everything from small-capacity inverters for home use to large-capacity inverters used in railways and the like. there is 2. Description of the Related Art As a circuit for driving a voltage-driven semiconductor element such as an IGBT, a gate driver, which is a gate driving circuit for controlling on/off of a semiconductor element by controlling a voltage applied to a gate, is used. In recent years, in place of Si (silicon) IGBTs, low-loss SiC (silicon carbide) MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) have been applied to power inverters and other devices. Conversion devices are becoming popular, and drive systems and gate drivers suitable for driving SiC-MOSFETs are also required for electric vehicles such as railways and automobiles. Patent Document 1 shows the configuration of a gate drive circuit of an inverter to which SiC-SBDs (Schottky Barrier Diodes) and Si-IGBTs are applied.

JP 2014-147237

As a result of intensive studies on reducing switching loss and noise in voltage-driven wide-gap semiconductor devices such as SiC-MOSFETs, the following findings were obtained.

SiC-MOSFETs have a smaller turn-off loss than Si-IGBTs. Since the Si-IGBT is a bipolar element, a tail current is generated due to recombination of carriers during turn-off, resulting in a large turn-off loss. On the other hand, since the SiC-MOSFET is a unipolar element, no tail current is generated in principle and the turn-off loss is small. For this reason, SiC elements with small switching loss are advantageous for high frequency operation, and SiC elements are required to further reduce switching loss for high frequency driving.

In order to reduce switching loss, in the gate drive circuit that charges and discharges the gate capacitance of the semiconductor element, by reducing the gate resistance for adjusting the charging and discharging speed, the switching speed is reduced, thereby reducing the switching loss. It is commonly practiced to However, by reducing the gate resistance, the switching loss can be reduced, but on the other hand, the time rate of change (dv/dt and di/dt) of the voltage and current during switching increases, and generally the noise emitted from the semiconductor device increases. There is a problem. That is, in driving a semiconductor device, there is a trade-off relationship between reduction in switching loss and reduction in noise, and low-loss and low-noise driving is an issue.

As described above, it is desirable that the driving method of the gate driver for driving the SiC-MOSFET has characteristics of reducing switching loss without increasing noise. Japanese Patent Laid-Open No. 2002-200300 discloses a prior art related to a driving technique for an element to which SiC is applied.

However, in the driving method described in Patent Document 1, when a SiC-SBD is used as a free wheel diode, in order to suppress violent voltage and current oscillations (ringing) that occur when the IGBT of the pair arm is turned on, During the turn-on operation of the IGBT, the IGBT gate-emitter capacitance (Cge) is discharged for a certain period of time. Therefore, the collector-emitter voltage (Vce) of the IGBT changes from a decrease to an increase during the discharge period, and the IGBT is turned on. There is a problem that loss increases.

As in Patent Document 1, when a SiC-SBD is applied as a freewheeling diode and the Si-IGBT of the paired arm is driven, it is effective to give priority to suppression of ringing and allow a certain increase in turn-on loss. . However, when driving a SiC-MOSFET as a semiconductor element, if the driving method of Patent Document 1 is applied, the switching speed during the mirror period, which is the period during which turn-on loss occurs, will be decelerated, resulting in a significant increase in turn-on loss. do.

An object of the present invention is to reduce both noise and switching loss during switching of a voltage-driven wide-gap semiconductor device.

The present invention relates to driving a voltage-driven wide-gap semiconductor device such that the gate current increases during the mirror period.

According to the present invention, since the gate current increases during the mirror period, the turn-on loss can be reduced without increasing the current change rate (di/dt) at turn-on of the voltage-driven wide-gap semiconductor device. Therefore, it is possible to achieve highly reliable and low-loss driving with an improved trade-off between noise and switching loss.

Configuration diagram of a railway inverter system FIG. 1 is a configuration diagram of a gate driver according to the first embodiment; Schematic diagram of a turn-on waveform of a semiconductor device showing the effect of Example 1 Explanatory diagram of the trade-off relationship between di/dt and turn-on loss, showing the effect of the first embodiment. FIG. 4 is an explanatory diagram of a timing range for starting an increase in gate current for the effects of the first embodiment to appear; Configuration diagram of a gate driver according to the second embodiment Configuration diagram of a gate driver according to the third embodiment Explanatory diagram of turn-on operation according to the third embodiment

The embodiments disclose a gate drive circuit for driving a voltage-driven wide-gap semiconductor device, which has means for increasing the gate current during the mirror period.

Further, the embodiment discloses a method of driving a voltage-driven wide-gap semiconductor device in which the gate current is increased during the mirror period.

The embodiments also disclose increasing the gate current during the mirror period.

Also, the embodiments disclose that the gate current starts increasing during the turn-on period and after the drain current reaches the on-current.

Also, the embodiments disclose starting the gate current increase during the turn-on period and before the drain-source voltage reaches the on-voltage.

Further, the embodiments disclose controlling the gate voltage of the semiconductor element using a voltage driving circuit connected to a constant voltage source.

Further, the embodiments disclose that the increase of the gate current is started after a predetermined time has elapsed from the input of the command to drive the semiconductor element.

Further, the embodiments disclose that the gate current starts to increase after the gate-source voltage of the voltage-driven wide-gap semiconductor device reaches a predetermined value.

Also, the embodiments disclose reducing the gate resistance to increase the gate current.

The embodiments also disclose increasing the gate current by increasing the gate drive voltage.

Further, the embodiments disclose that the voltage-driven wide-gap semiconductor device is a SiC-MOSFET.

Further, the embodiments disclose a power conversion device equipped with a gate drive circuit and an electric vehicle equipped with the power conversion device.

The above and other novel features and effects of the present invention will be described below with reference to the drawings. The drawings are used exclusively for understanding the invention and do not limit the scope of rights.

FIG. 1 is a configuration diagram of a railway inverter system according to this embodiment.

In the railroad inverter system according to this embodiment, a power unit 100 is configured by a MOSFET 101 and a filter capacitor 103, which are voltage-driven wide-gap semiconductor devices. In each of the UVW phases, MOSFETs 101 are connected in series, and freewheeling diodes 102 are connected in parallel to each MOSFET 101 so that the conduction direction is opposite. In the case of a SiC-MOSFET, a diode incorporated in the MOSFET 101 may be used as the freewheeling diode 102, in which case the freewheeling diode 102 is not necessarily required.

Each MOSFET 101 is provided with a gate driver 104 for driving the MOSFET according to a command from the command logic unit 105 . A connection point between the upper MOSFET (upper arm) and the lower MOSFET (lower arm) of each UVW phase is connected to the motor 106 as the output of the power unit 100 .

Electric power from the overhead line 107 is input to the high-voltage side of the filter capacitor 103 for smoothing the DC power and removing noise through the current collector 108, the plurality of circuit breakers 109 and the filter reactor 110. The low-voltage side of the filter capacitor 103 is connected via wheels 111 to a rail 112 which is an electrical ground. The railway inverter system alternately switches the UVW-phase MOSFETs in the power unit to generate a three-phase alternating current and send it to the motor 106 . A gate driver 104 arranged in the power unit 100 together with the MOSFET 101 and the filter capacitor 103 drives the MOSFET 101 in accordance with a command from the command logic section 105 . The command logic unit 105 includes an arithmetic device, memory, and input/output means, and outputs a command to drive the MOSFET according to a predetermined program. In the gate driver according to the present embodiment, an example in which a MOSFET is driven as a semiconductor element will be described, but the semiconductor element is not limited to a MOSFET and may be a voltage-driven element such as an IGBT.

FIG. 2 is a configuration diagram of a gate driver according to this embodiment. As shown in FIG. 2, the gate driver 104 includes a gate driver positive power supply 1 (power supply voltage = +Vp1), a gate driver negative power supply 2 (power supply voltage = -Vm), a P-type MOSFET 3a, an N-type MOSFET 4, an ON It is composed of a side gate resistor 5 (Ron1), an off-side gate resistor 6, a drive controller 7, a timer circuit 8, and a gate resistance reduction circuit 9.

The source of the P-type MOSFET 3a is connected to the positive power supply 1, and the drain is connected to the on-side gate resistor 5. As shown in FIG. The N-type MOSFET 4 has a source connected to the negative power supply 2 and a drain connected to the off-side gate resistor 6 . A connection point between the on-side gate resistor 5 and the off-side gate resistor 6 serves as an output part of the gate driver 104 and is connected to the gate of the semiconductor element 101 . Gates of the P-type MOSFET 3 a and the N-type MOSFET 4 are both connected to the output section of the drive control device 7 . The command logic section 105 is connected to the input section of the drive control device 7 and the input section of the timer circuit 8 .

The gate resistance reducing circuit 9 is composed of a P-type MOSFET 3b, a driving device 10, and a gate current increasing resistor 11 (Ron2). The output part of the timer circuit 8 is connected to the input part of the driving device 10, and the output part of the driving device 10 is connected to the gate of the P-type MOSFET 3b. The source of the P-type MOSFET 3b is connected to the positive power supply 1, and the drain of the P-type MOSFET 3b is connected to the output of the gate driver 104, that is, the gate of the semiconductor element 101 through the gate current increasing resistor 11.

When a gate drive command is input from the command logic unit 105 to the drive control unit 7, the drive control unit 7 controls the P-type MOSFET 3a and the N-type MOSFET 4 in the output stage of the gate driver so as to complementarily turn on and off the semiconductor. A charge is charged and discharged to the gate of element 101 . The charging and discharging speeds can be controlled by the resistance values of the on-side gate resistor 5 and the off-side gate resistor 6, respectively.

When the P-type MOSFET 3a is on and the N-type MOSFET 4 is off, the gate of the MOSFET 101 is charged through the P-type MOSFET 3a. Transition from off to on state (turn on). At this time, a turn-on loss corresponding to the time integral of the product of the drain-source voltage (Vds) of the MOSFET 101 and the drain current (Id) occurs.

When the P-type MOSFET 3a is off and the N-type MOSFET 4 is on, charge is discharged from the gate of the MOSFET 101 via the N-type MOSFET 4, and when Vgs falls below Vth, the MOSFET 101 shifts from on to off (turn off). At this time, a turn-off loss corresponding to the time integration of the product of Vds and Id of MOSFET 101 occurs.

In this embodiment, the gate resistance reduction circuit 9 is operated during the mirror period of the turn-on operation of the semiconductor element 101 to increase the charging speed of the gate charge at the time of turn-on, thereby quickly completing the turn-on operation. Loss can be reduced. The circuit operation for realizing the above will be described below with reference to FIG.

The timer circuit 8 operates starting from the time when the gate drive command (ON command) is input from the command logic unit 105 to the drive control device 7, and the gate resistance reduction circuit 9 operates after a certain delay time determined by the timer circuit 8 has passed. do. At this time, when the drive circuit 10 turns on the P-type MOSFET 3b, the gate of the MOSFET 101 is supplied with electric charge from the positive power supply 1 via the P-type MOSFET 3b. is increased (gate current is increased), and the turn-on operation is completed quickly, so the turn-on loss generated in MOSFET 101 can be reduced.

At this time, the resistance value (Ron2) of the gate current increasing resistor 11 is made smaller than the resistance value (Ron1) of the on-side gate resistor 5 (Ron1>Ron2), so that after the gate resistance reduction circuit 9 operates, the gate You can increase the current.

A mechanism for reducing turn-on losses without increasing the time rate of change of current at turn-on (di/dt) is described below with reference to FIGS.

FIG. 3 is a schematic diagram of a turn-on waveform of a semiconductor device, showing the effect of this embodiment. A dashed line waveform indicates a case where the gate resistance at turn-on is fixed to a constant value Rg1. The solid line waveform shows the case where the gate resistance at turn-on is Rg1 before the mirror period and is reduced to Rg2 (<Rg1) during the mirror period. The waveform of the drain current (Id) overlaps the solid line and the dashed line.

Before time t0, the drain-source voltage (Vds) is approximately equal to the power supply voltage Vcc and the drain current (Id) is zero. At time t0, the gate-source voltage of MOSFET 101 reaches the threshold voltage (Vgs=Vth), and drain current (Id) begins to flow. At time t1, the drain current reaches the ON current (Id=Ion), and after time t1, Vds decreases and Vgs enters a mirror period in which it is almost constant. At time t2, Vds drops to the ON voltage (Von) and the turn-on operation is completed.

At this time, in the turn-on operation of the MOSFET 101, the drain current (Id) reaches the on-current (Ion) by adjusting the delay time determined by the timer circuit 8 so that the gate resistance reduction circuit 9 starts operating during the mirror period. Since the gate current can be made to increase after switching on, only the time rate of change of Vds at turn-on (dv/dt) is increased without increasing the time rate of change of current at turn-on (di/dt). Therefore, the turn-on loss determined by the time integral of the product of Vds and Id can be reduced.

Furthermore, since the gate resistance reduction circuit 9 is a voltage drive circuit connected to the positive power supply 1 of the gate driver, which is a constant voltage source, the voltage of the positive power supply 1 of the gate driver is the absolute maximum of the gate voltage of the MOSFET 101. As long as it is below the rating, the gate voltage of the MOSFET 101 can be controlled below the absolute maximum rating even after the gate resistance reduction circuit 9 is activated, and the reliability of the device is ensured.

FIG. 4 is an explanatory diagram of the trade-off relationship between di/dt and turn-on loss, showing the effect of this embodiment. In contrast to driving with the gate resistance fixed at a constant value (Ron1), the same noise level (di/ dt), the turn-on loss can be reduced and the trade-off between noise and loss can be improved. As a result of investigation by the present inventors, in a switching test of a SiC-MOSFET at a power supply voltage Vcc = 1500 V to which this gate driver is applied, it was confirmed that the turn-on loss can be reduced by about 20% compared with the same di/dt level. .

FIG. 5 is an explanatory diagram of the timing range for starting the increase of the gate current for the effect of the present embodiment to appear. FIG. 5 is a schematic diagram of a locus (trajectory) plotted with the drain current (Id) on the vertical axis and the drain-source voltage (Vds) on the horizontal axis for the turn-on waveform of FIG. Point (A) indicates the start time of turn-on (when Id begins to flow), point (B) indicates the time when the mirror period begins, and point (C) indicates the time point when turn-on ends (when Vds reaches the on-voltage Von). Among these, the timing to start increasing the gate current may be between points (B) and (C). After point (B), the drain current (Id) during the turn-on period reaches the on-current (Ion). This is because only loss can be reduced. Furthermore, since the decrease in turn-on loss increases as the gate current is increased as soon as possible after the point (B), the timing of the best mode is immediately after the point (B).

This embodiment monitors the gate-source voltage (Vgs) of the semiconductor element as a means for determining the timing to start increasing the gate current in contrast to the configuration of the gate driver of the first embodiment. It is different in that it detects when it reaches the above. The following description will focus on the differences from the first embodiment.

FIG. 6 is a configuration diagram of a gate driver according to this embodiment. Since the timer circuit 8 of the first embodiment is unnecessary, it is removed. Instead of the timer circuit 8, a gate voltage detection circuit 12 is connected between the output section of the gate driver 104 and the gate resistance reduction circuit 9 in this embodiment. Other connection modes are the same as in the first embodiment.

As an embodiment of the gate voltage detection circuit 12, as shown in FIG. 6, an example configured with a comparator 13 is shown. The -input terminal of the comparator 13 is connected to the output section of the gate driver 104, and the +input terminal is connected to the negative side power supply 2 of the gate driver via a reference voltage source (Vref). The output terminal of comparator 13 is connected to gate resistance reduction circuit 9 .

The voltage of the - input terminal of the comparator 13 is equal to the gate-source voltage (Vgs) of the MOSFET 101, and when the voltage of the + input terminal is exceeded (Vgs>Vref), the output of the comparator 13 goes from high to low, and the gate The resistance reduction circuit 9 is activated. Therefore, by designing Vref so that the gate resistance reduction circuit 9 operates during the mirror period, the turn-on loss can be reduced without increasing di/dt.

When the device temperature of the MOSFET 101 and the substrate temperature of the gate driver 104 change, the delay time from the input of the gate drive command (ON command) from the command logic unit 105 to the MOSFET 101 entering the mirror period can also change. However, in this embodiment, since the gate-source voltage (Vgs) during actual driving at the temperature is monitored, even if the temperature changes, the timing to start increasing the gate current is less likely to fluctuate from the mirror period. There is

This embodiment differs from the configuration of the gate driver of the second embodiment in that a method of increasing the gate drive voltage is used instead of a method of reducing the gate resistance as means for increasing the gate current. In the following, differences from the first and second embodiments will be mainly described.

FIG. 7 is a configuration diagram of a gate driver according to this embodiment. Since the gate resistance reduction circuit 9 shown in the first and second embodiments is unnecessary, it is removed. Instead of the gate resistance reduction circuit 9, in this embodiment, a gate voltage increase circuit 14 is connected between the output of the gate voltage detection circuit 12 and the drain of the P-type MOSFET 3a. Other connection modes are the same as in the second embodiment.

The gate voltage increasing circuit 14 is composed of a first positive power supply 1, a second positive power supply 15, a one-shot IC 16, a P-type MOSFET 17, and an N-type MOSFET 18 of the gate driver. The input of one-shot IC 16 is connected to the output of gate voltage detection circuit 12 . The drain of the P-type MOSFET 17 and the drain of the N-type MOSFET 18 are both connected to the drain of the P-type MOSFET 3a. The gate of the P-type MOSFET 17 and the gate of the N-type MOSFET 18 are both connected to the output of the one-shot IC 16 . The source of the P-type MOSFET 17 is connected to the second positive power supply 15 of the gate driver, and the source of the N-type MOSFET 18 is connected to the first positive power supply 1 of the gate driver.

The voltage (+Vp2) of the second positive power supply 15 is set higher than the voltage (+Vp1) of the first positive power supply 1 and lower than the absolute maximum rating (+Vgs_abs) of the gate voltage of the semiconductor element 101. (+Vp1<+Vp2<+Vgs_abs).

When the gate voltage of the MOSFET 101 is lower than the reference voltage of the gate voltage detection circuit 12, the output of the comparator 13 becomes high due to the relation of the input voltage of the comparator 13 (Vgs<Vref). At this time, the output of the one-shot IC 16 in the gate voltage increasing circuit 14 is held high, the P-type MOSFET 17 is turned off, and the N-type MOSFET 18 is turned on. Therefore, the potential of the drain of the P-type MOSFET 3a becomes equal to the voltage of the first positive power supply 1 (+Vp1).

When the gate voltage of the MOSFET 101 is higher than the reference voltage of the gate voltage detection circuit 12, the output of the comparator 13 becomes low due to the relationship between the input voltages of the comparator 13 (Vgs>Vref). At this time, the output of the one-shot IC 16 in the gate voltage increasing circuit 14 changes from high to low for a certain period (ΔT) determined by the internal circuit of the one-shot IC 16, and only during this period ΔT, The P-type MOSFET 17 is turned on and the N-type MOSFET 18 is turned off. Therefore, the potential of the drain of the P-type MOSFET 3a becomes equal to the voltage (+Vp2) of the second positive power supply 15 only during the period ΔT.

From the above circuit operation, in the turn-on operation of the MOSFET 101, the potential of the drain of the P-type MOSFET 3a can be set to +Vp1 in the first half period (Vgs<Vref), and the potential of the drain of the P-type MOSFET 3a can be set to +Vp1 in the second half period (Vgs>Vref). +Vp2 (>+Vp1).

By setting the reference voltage (Vref) of the gate voltage detection circuit 12 so that the branch point between the first half section and the second half section is after the time when the semiconductor element 101 reaches the mirror period, the gate is driven during the mirror period. The voltage can be boosted from +Vp1 to +Vp2. Therefore, turn-on loss can be reduced without increasing di/dt. The one-shot IC 16 has the role of outputting a low output for a certain period of time (ΔT) triggered by the low output of the comparator 13, and any element having similar functions may be used instead of the one-shot IC.

FIG. 8 is an explanatory diagram of the turn-on operation according to this embodiment. A broken line waveform indicates a case where the gate drive voltage at turn-on is fixed to a constant value +Vp1. The solid line waveform shows the case where the gate drive voltage at turn-on is set to +Vp1 before the mirror period and is boosted to +Vp2 (>+Vp1) during the mirror period. The waveform of the drain current (Id) overlaps the solid line and the dashed line.

By adjusting the reference voltage (Vref) of the gate voltage detection circuit 12 so that the gate voltage increase circuit 14 starts operating during the mirror period, the gate current increases, the turn-on loss can be reduced by increasing only the time rate of change (dv/dt) of Vds at turn-on without increasing di/dt.

The period ΔT during which the output of the one-shot IC 16 is low is preferably longer than the mirror period (T1) of the MOSFET 101 . Also, the period ΔT must be shorter than the period (T2) until the next turn-on (T1<ΔT<T2), not shown in FIG. ΔT>T1 is a condition for keeping the gate current increasing during the mirror period of the MOSFET 101, and ΔT<T2 is the condition that the potential of the drain of the P-type MOSFET 3a is set to the gate driver until the next turn-on operation starts. This is a condition necessary for returning the voltage (+Vp2) of the second positive power supply 15 to the voltage (+Vp1) of the first positive power supply 1.

In this embodiment, the power supply voltage of the second positive power supply 15 of the gate driver is made higher than the power supply voltage of the first positive power supply 1 within the range of less than the absolute maximum rating of the gate voltage of the semiconductor element 101 +Vgs_abs. By (+Vp1<+Vp2<+Vgs_abs), there is an advantage that the gate current can be further increased compared to the first and second embodiments, and the turn-on loss can be further reduced.

1: (first) positive power supply for gate driver 2: negative power supply for gate driver 3a, 3b, 17: P-type MOSFET
4, 18: N-type MOSFET
5: ON-side gate resistor 6: OFF-side gate resistor 7: Drive control device 8: Timer circuit 9: Gate resistance reduction circuit 10: Driving device 11: Gate current increasing resistor 12: Gate voltage detection circuit 13: Comparator 14: Gate voltage increasing circuit 15: second positive side power supply for gate driver 16: one-shot IC
100: Power unit 101: MOSFET
102: freewheeling diode 103: filter capacitor 104: gate driver 105: command logic unit 106: motor 107: overhead wire 108: current collector 109: circuit breaker 110: filter reactor 111: wheel 112: rail Vgs: gate-source voltage Vds : Drain-source voltage Ig: Gate current Id: Drain current Rg: Gate resistance Vth: Threshold voltage Ion: ON current Von: ON voltage Vcc: Power supply voltage

Claims (4)

In a gate drive circuit that drives a voltage-driven wide-gap semiconductor device represented by a SiC-MOSFET ,
comprising means for controlling the gate voltage of the semiconductor element using a voltage drive circuit connected to a plurality of constant voltage sources;
During the turn-on period of the semiconductor element, after the drain current of the semiconductor element reaches the on-current, and from the point of input of the gate drive command of the semiconductor element , the means controls the voltage between the gate and the source of the semiconductor element. becomes a predetermined value or more , the gate voltage is increased to increase the gate current of the semiconductor element.
A gate drive circuit characterized by : A power converter equipped with the gate drive circuit according to claim 1 . An electric vehicle equipped with the power converter according to claim 2. In a gate driving method for driving a voltage-driven wide-gap semiconductor device represented by a SiC-MOSFET ,
controlling the gate voltage of the semiconductor element using a voltage drive circuit connected to a plurality of constant voltage sources;
During the turn-on period of the semiconductor element, after the drain current of the semiconductor element reaches the on-current, and from the time of inputting the gate drive command of the semiconductor element , the gate-source voltage of the semiconductor element is equal to or higher than a predetermined value. , the gate voltage is increased to increase the gate current of the semiconductor element
A gate driving method characterized by :

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