JP7245833B2 - 構成可能なハードウェアの実行時の最適化 - Google Patents

構成可能なハードウェアの実行時の最適化 Download PDF

Info

Publication number
JP7245833B2
JP7245833B2 JP2020529105A JP2020529105A JP7245833B2 JP 7245833 B2 JP7245833 B2 JP 7245833B2 JP 2020529105 A JP2020529105 A JP 2020529105A JP 2020529105 A JP2020529105 A JP 2020529105A JP 7245833 B2 JP7245833 B2 JP 7245833B2
Authority
JP
Japan
Prior art keywords
program code
computational
portions
groups
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020529105A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020530175A5 (enExample
JPWO2019028253A5 (enExample
JP2020530175A (ja
Inventor
エラド ラズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Next Silicon Ltd
Original Assignee
Next Silicon Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Next Silicon Ltd filed Critical Next Silicon Ltd
Publication of JP2020530175A publication Critical patent/JP2020530175A/ja
Publication of JP2020530175A5 publication Critical patent/JP2020530175A5/ja
Publication of JPWO2019028253A5 publication Critical patent/JPWO2019028253A5/ja
Application granted granted Critical
Publication of JP7245833B2 publication Critical patent/JP7245833B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
  • Advance Control (AREA)
JP2020529105A 2017-08-03 2018-08-02 構成可能なハードウェアの実行時の最適化 Active JP7245833B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762540849P 2017-08-03 2017-08-03
US62/540,849 2017-08-03
US201762558090P 2017-09-13 2017-09-13
US62/558,090 2017-09-13
PCT/US2018/045008 WO2019028253A1 (en) 2017-08-03 2018-08-02 EXECUTION OPTIMIZATION OF CONFIGURABLE EQUIPMENT

Publications (4)

Publication Number Publication Date
JP2020530175A JP2020530175A (ja) 2020-10-15
JP2020530175A5 JP2020530175A5 (enExample) 2021-09-09
JPWO2019028253A5 JPWO2019028253A5 (enExample) 2022-11-28
JP7245833B2 true JP7245833B2 (ja) 2023-03-24

Family

ID=65229554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020529105A Active JP7245833B2 (ja) 2017-08-03 2018-08-02 構成可能なハードウェアの実行時の最適化

Country Status (7)

Country Link
US (1) US10817309B2 (enExample)
EP (1) EP3662384A4 (enExample)
JP (1) JP7245833B2 (enExample)
KR (1) KR102668340B1 (enExample)
CN (1) CN111164583B (enExample)
SG (1) SG11202000752RA (enExample)
WO (1) WO2019028253A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102668340B1 (ko) 2017-08-03 2024-05-22 넥스트 실리콘 리미티드 설정가능한 하드웨어 런타임 최적화
EP3682353A4 (en) 2017-09-13 2021-12-08 Next Silicon Ltd DIRECTED AND INTERCONNECTED GRID DATA FLOW ARCHITECTURE
CN110704360B (zh) * 2019-09-29 2022-03-18 华中科技大学 一种基于异构fpga数据流的图计算优化方法
KR20220139304A (ko) * 2019-12-30 2022-10-14 스타 알리 인터내셔널 리미티드 구성 가능한 병렬 계산을 위한 프로세서
US11269526B2 (en) 2020-04-23 2022-03-08 Next Silicon Ltd Interconnected memory grid with bypassable units
US11175957B1 (en) * 2020-09-22 2021-11-16 International Business Machines Corporation Hardware accelerator for executing a computation task
US12333231B1 (en) 2024-11-03 2025-06-17 Next Silicon Ltd. Reconfigurable integrated circuit (IC) device and a system and method of configuring thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002526826A (ja) 1998-09-30 2002-08-20 インフィネオン テクノロジース アクチエンゲゼルシャフト リコンフィギュレーション可能な回路を用いて個別アルゴリズムを実行するための方法およびこのような方法を実施するための装置
JP2005505030A (ja) 2001-09-14 2005-02-17 インテル コーポレイション 複数のハードウェア構成を有する再構成可能なハードウェア・アーキテクチャにおけるスケジューリング方法
WO2008026731A1 (en) 2006-08-31 2008-03-06 Ipflex Inc. Method and system for mounting circuit design on reconfigurable device
JP2009163328A (ja) 2007-12-28 2009-07-23 Toshiba Corp 情報処理装置及びその制御方法
JP2009238221A (ja) 2008-03-19 2009-10-15 Panasonic Corp ルータを利用した配置後ルーティングによるタイミング再調整
WO2017029743A1 (ja) 2015-08-20 2017-02-23 株式会社日立製作所 情報処理装置および情報処理システム

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321806A (en) 1991-08-21 1994-06-14 Digital Equipment Corporation Method and apparatus for transmitting graphics command in a computer graphics system
US5367653A (en) 1991-12-26 1994-11-22 International Business Machines Corporation Reconfigurable multi-way associative cache memory
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US6732126B1 (en) 1999-05-07 2004-05-04 Intel Corporation High performance datapath unit for behavioral data transmission and reception
US6347346B1 (en) 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6871341B1 (en) * 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US7269174B2 (en) 2003-03-28 2007-09-11 Modular Mining Systems, Inc. Dynamic wireless network
US7957266B2 (en) 2004-05-28 2011-06-07 Alcatel-Lucent Usa Inc. Efficient and robust routing independent of traffic pattern variability
US7536370B2 (en) 2004-06-24 2009-05-19 Sun Microsystems, Inc. Inferential diagnosing engines for grid-based computing systems
US20120001371A1 (en) 2004-07-10 2012-01-05 Mann+Hummel Gmbh Method for Producing a Ceramic Filter Element
US7877350B2 (en) 2005-06-27 2011-01-25 Ab Initio Technology Llc Managing metadata for graph-based computations
EP1808774A1 (en) 2005-12-22 2007-07-18 St Microelectronics S.A. A hierarchical reconfigurable computer architecture
US7904848B2 (en) 2006-03-14 2011-03-08 Imec System and method for runtime placement and routing of a processing array
US8156307B2 (en) 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US20110213950A1 (en) 2008-06-11 2011-09-01 John George Mathieson System and Method for Power Optimization
JP5294304B2 (ja) 2008-06-18 2013-09-18 日本電気株式会社 再構成可能電子回路装置
EP2310952A4 (en) 2008-07-01 2014-09-03 S K Nandy PROCESS AND CHIP SYSTEM (SOC) FOR CUSTOMIZING A CONVERTIBLE HARDWARE FOR ONE TIME APPLICATION
US8554074B2 (en) 2009-05-06 2013-10-08 Ciena Corporation Colorless, directionless, and gridless optical network, node, and method
US8230176B2 (en) 2009-06-26 2012-07-24 International Business Machines Corporation Reconfigurable cache
KR101076869B1 (ko) 2010-03-16 2011-10-25 광운대학교 산학협력단 코어스 그레인 재구성 어레이에서의 메모리 중심 통신 장치
US8880866B2 (en) * 2010-10-15 2014-11-04 Coherent Logix, Incorporated Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configuration
US8621151B2 (en) 2010-11-23 2013-12-31 IP Cube Partners (IPC) Co., Ltd. Active memory processor system
US8504778B2 (en) 2010-11-24 2013-08-06 IP Cube Partners (ICP) Co., Ltd. Multi-core active memory processor system
US8589628B2 (en) 2010-11-29 2013-11-19 IP Cube Partners (ICP) Co., Ltd. Hybrid active memory processor system
WO2012154612A1 (en) 2011-05-06 2012-11-15 Xcelemor, Inc. Computing system with hardware scheduled reconfiguration mechanism and method of operation thereof
US8782645B2 (en) * 2011-05-11 2014-07-15 Advanced Micro Devices, Inc. Automatic load balancing for heterogeneous cores
US9024655B2 (en) 2012-02-21 2015-05-05 Wave Semiconductor, Inc. Multi-threshold flash NCL circuitry
US8767501B2 (en) 2012-07-17 2014-07-01 International Business Machines Corporation Self-reconfigurable address decoder for associative index extended caches
US9563401B2 (en) 2012-12-07 2017-02-07 Wave Computing, Inc. Extensible iterative multiplier
US9588773B2 (en) 2013-01-07 2017-03-07 Wave Computing, Inc. Software based application specific integrated circuit
CN104238995B (zh) * 2013-06-21 2017-03-15 中国人民解放军信息工程大学 一种非线性反馈移位寄存器
US9590629B2 (en) 2013-11-02 2017-03-07 Wave Computing, Inc. Logical elements with switchable connections
US10057135B2 (en) * 2013-12-02 2018-08-21 Ciena Corporation Unified management of computing networks
US9460012B2 (en) 2014-02-18 2016-10-04 National University Of Singapore Fusible and reconfigurable cache architecture
US20150268963A1 (en) 2014-03-23 2015-09-24 Technion Research & Development Foundation Ltd. Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware
US9553818B2 (en) 2014-06-27 2017-01-24 Adtran, Inc. Link biased data transmission
GB201415796D0 (en) 2014-09-07 2014-10-22 Technion Res & Dev Foundation Logical-to-physical block mapping inside the disk controller: accessing data objects without operating system intervention
US9946832B2 (en) 2014-11-13 2018-04-17 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Optimized placement design of network and infrastructure components
US9692419B2 (en) 2014-11-15 2017-06-27 Wave Computing, Inc. Compact logic evaluation gates using null convention
US20160342396A1 (en) 2015-05-20 2016-11-24 Ab lnitio Technology LLC Visual program specification and compilation of graph-based computation
US10503524B2 (en) * 2016-03-22 2019-12-10 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Interception of a function call, selecting a function from available functions and rerouting the function call
US10884761B2 (en) * 2016-03-22 2021-01-05 Lenovo Enterprise Solutions (Singapore) Pte. Ltd Best performance delivery in heterogeneous computing unit environment
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10467183B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods for pipelined runtime services in a spatial array
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
KR102668340B1 (ko) 2017-08-03 2024-05-22 넥스트 실리콘 리미티드 설정가능한 하드웨어 런타임 최적화
EP3682353A4 (en) 2017-09-13 2021-12-08 Next Silicon Ltd DIRECTED AND INTERCONNECTED GRID DATA FLOW ARCHITECTURE

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002526826A (ja) 1998-09-30 2002-08-20 インフィネオン テクノロジース アクチエンゲゼルシャフト リコンフィギュレーション可能な回路を用いて個別アルゴリズムを実行するための方法およびこのような方法を実施するための装置
JP2005505030A (ja) 2001-09-14 2005-02-17 インテル コーポレイション 複数のハードウェア構成を有する再構成可能なハードウェア・アーキテクチャにおけるスケジューリング方法
WO2008026731A1 (en) 2006-08-31 2008-03-06 Ipflex Inc. Method and system for mounting circuit design on reconfigurable device
JP2009163328A (ja) 2007-12-28 2009-07-23 Toshiba Corp 情報処理装置及びその制御方法
JP2009238221A (ja) 2008-03-19 2009-10-15 Panasonic Corp ルータを利用した配置後ルーティングによるタイミング再調整
WO2017029743A1 (ja) 2015-08-20 2017-02-23 株式会社日立製作所 情報処理装置および情報処理システム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
佐野 雅彦 他，ＦＰＧＡ化のためのｋ－ａｒｙ ｎ－ｃｕｂｅ型相互結合網用のルータの設計，情報処理学会研究報告，社団法人情報処理学会，1996年05月16日，第96巻 第39号，第31頁－第36頁

Also Published As

Publication number Publication date
KR102668340B1 (ko) 2024-05-22
US10817309B2 (en) 2020-10-27
CN111164583B (zh) 2024-02-27
EP3662384A4 (en) 2021-05-05
KR20200052277A (ko) 2020-05-14
EP3662384A1 (en) 2020-06-10
SG11202000752RA (en) 2020-02-27
WO2019028253A1 (en) 2019-02-07
CN111164583A (zh) 2020-05-15
US20190042282A1 (en) 2019-02-07
JP2020530175A (ja) 2020-10-15

Similar Documents

Publication Publication Date Title
JP7245833B2 (ja) 構成可能なハードウェアの実行時の最適化
Nguyen et al. Fifer: Practical acceleration of irregular applications on reconfigurable architectures
CN109213523B (zh) 具有存储器系统性能、功率减小和原子支持特征的可配置空间加速器的处理器、方法和系统
US11119768B2 (en) Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric
US11687327B2 (en) Control and reconfiguration of data flow graphs on heterogeneous computing platform
US11010161B2 (en) Multiple types of thread identifiers for a multi-threaded, self-scheduling reconfigurable computing fabric
CN109597458B (zh) 用于空间阵列中的可配置时钟门控的处理器和方法
CN109597459B (zh) 用于空间阵列中的特权配置的处理器和方法
US20210224068A1 (en) Execution Control of a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric
US11204745B2 (en) Dataflow graph programming environment for a heterogenous processing system
US20190303144A1 (en) Backpressure Control Using a Stop Signal for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric
CN118708534A (zh) 一种用于数据流图处理的处理器、方法、设备、及一种非暂时性机器可读介质
JP7183197B2 (ja) 高スループットプロセッサ
US11113030B1 (en) Constraints for applications in a heterogeneous programming environment
US10817344B2 (en) Directed and interconnected grid dataflow architecture
Jain et al. Coarse grained FPGA overlay for rapid just-in-time accelerator compilation
US10476492B2 (en) Structures and operations of integrated circuits having network of configurable switches
KR100681199B1 (ko) 코어스 그레인 어레이에서의 인터럽트 처리 방법 및 장치
Akabe et al. Imax: A power-efficient multilevel pipelined cgla and applications
Tareen et al. Hihispmv: Sparse matrix vector multiplication with hierarchical row reductions on fpgas with high bandwidth memory
Li et al. FPGA overlays: hardware-based computing for the masses
Jmaa et al. An efficient hardware implementation of timsort and mergesort algorithms using high level synthesis
Kobayashi et al. An open-source FPGA library for data sorting
Rettkowski et al. Application-specific processing using high-level synthesis for networks-on-chip
Fell et al. Streaming FFT on REDEFINE-v2: An application-architecture design space exploration

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210729

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210729

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7426

Effective date: 20210729

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20210730

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220809

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220816

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221116

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20221116

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230214

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230313

R150 Certificate of patent or registration of utility model

Ref document number: 7245833

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150