JP7245833B2 - 構成可能なハードウェアの実行時の最適化 - Google Patents

構成可能なハードウェアの実行時の最適化 Download PDF

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JP7245833B2
JP7245833B2 JP2020529105A JP2020529105A JP7245833B2 JP 7245833 B2 JP7245833 B2 JP 7245833B2 JP 2020529105 A JP2020529105 A JP 2020529105A JP 2020529105 A JP2020529105 A JP 2020529105A JP 7245833 B2 JP7245833 B2 JP 7245833B2
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エラド ラズ
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Next Silicon Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2020529105A 2017-08-03 2018-08-02 構成可能なハードウェアの実行時の最適化 Active JP7245833B2 (ja)

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US201762540849P 2017-08-03 2017-08-03
US62/540,849 2017-08-03
US201762558090P 2017-09-13 2017-09-13
US62/558,090 2017-09-13
PCT/US2018/045008 WO2019028253A1 (en) 2017-08-03 2018-08-02 EXECUTION OPTIMIZATION OF CONFIGURABLE EQUIPMENT

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JP2020530175A JP2020530175A (ja) 2020-10-15
JP2020530175A5 JP2020530175A5 (enExample) 2021-09-09
JPWO2019028253A5 JPWO2019028253A5 (enExample) 2022-11-28
JP7245833B2 true JP7245833B2 (ja) 2023-03-24

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EP (1) EP3662384A4 (enExample)
JP (1) JP7245833B2 (enExample)
KR (1) KR102668340B1 (enExample)
CN (1) CN111164583B (enExample)
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WO (1) WO2019028253A1 (enExample)

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WO2019055675A1 (en) 2017-09-13 2019-03-21 Next Silicon, Ltd. DATA ARCHITECTURE WITH DIRECTED AND INTERCONNECTED GRID
CN110704360B (zh) * 2019-09-29 2022-03-18 华中科技大学 一种基于异构fpga数据流的图计算优化方法
WO2021138189A1 (en) * 2019-12-30 2021-07-08 Star Ally International Limited Processor for configurable parallel computations
US11269526B2 (en) 2020-04-23 2022-03-08 Next Silicon Ltd Interconnected memory grid with bypassable units
US11175957B1 (en) * 2020-09-22 2021-11-16 International Business Machines Corporation Hardware accelerator for executing a computation task
US12333231B1 (en) 2024-11-03 2025-06-17 Next Silicon Ltd. Reconfigurable integrated circuit (IC) device and a system and method of configuring thereof

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SG11202000752RA (en) 2020-02-27
KR102668340B1 (ko) 2024-05-22
CN111164583B (zh) 2024-02-27
EP3662384A4 (en) 2021-05-05
US20190042282A1 (en) 2019-02-07
EP3662384A1 (en) 2020-06-10
US10817309B2 (en) 2020-10-27
KR20200052277A (ko) 2020-05-14
WO2019028253A1 (en) 2019-02-07
JP2020530175A (ja) 2020-10-15
CN111164583A (zh) 2020-05-15

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