SG11202000752RA - Runtime optimization of configurable hardware - Google Patents

Runtime optimization of configurable hardware

Info

Publication number
SG11202000752RA
SG11202000752RA SG11202000752RA SG11202000752RA SG11202000752RA SG 11202000752R A SG11202000752R A SG 11202000752RA SG 11202000752R A SG11202000752R A SG 11202000752RA SG 11202000752R A SG11202000752R A SG 11202000752RA SG 11202000752R A SG11202000752R A SG 11202000752RA
Authority
SG
Singapore
Prior art keywords
configurable hardware
runtime optimization
runtime
optimization
configurable
Prior art date
Application number
SG11202000752RA
Inventor
Elad Raz
Original Assignee
Next Silicon Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Next Silicon Ltd filed Critical Next Silicon Ltd
Publication of SG11202000752RA publication Critical patent/SG11202000752RA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5072—Grid computing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
SG11202000752RA 2017-08-03 2018-08-02 Runtime optimization of configurable hardware SG11202000752RA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762540849P 2017-08-03 2017-08-03
US201762558090P 2017-09-13 2017-09-13
PCT/US2018/045008 WO2019028253A1 (en) 2017-08-03 2018-08-02 Runtime optimization of configurable hardware

Publications (1)

Publication Number Publication Date
SG11202000752RA true SG11202000752RA (en) 2020-02-27

Family

ID=65229554

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202000752RA SG11202000752RA (en) 2017-08-03 2018-08-02 Runtime optimization of configurable hardware

Country Status (7)

Country Link
US (1) US10817309B2 (en)
EP (1) EP3662384A4 (en)
JP (1) JP7245833B2 (en)
KR (1) KR102668340B1 (en)
CN (1) CN111164583B (en)
SG (1) SG11202000752RA (en)
WO (1) WO2019028253A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11202000752RA (en) 2017-08-03 2020-02-27 Next Silicon Ltd Runtime optimization of configurable hardware
WO2019055675A1 (en) 2017-09-13 2019-03-21 Next Silicon, Ltd. Directed and interconnected grid dataflow architecture
CN110704360B (en) * 2019-09-29 2022-03-18 华中科技大学 Graph calculation optimization method based on heterogeneous FPGA data flow
US11269526B2 (en) 2020-04-23 2022-03-08 Next Silicon Ltd Interconnected memory grid with bypassable units

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Also Published As

Publication number Publication date
WO2019028253A1 (en) 2019-02-07
JP7245833B2 (en) 2023-03-24
CN111164583B (en) 2024-02-27
CN111164583A (en) 2020-05-15
KR102668340B1 (en) 2024-05-22
US20190042282A1 (en) 2019-02-07
JP2020530175A (en) 2020-10-15
EP3662384A1 (en) 2020-06-10
EP3662384A4 (en) 2021-05-05
KR20200052277A (en) 2020-05-14
US10817309B2 (en) 2020-10-27

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