JP2020530175A5 - - Google Patents

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JP2020530175A5
JP2020530175A5 JP2020529105A JP2020529105A JP2020530175A5 JP 2020530175 A5 JP2020530175 A5 JP 2020530175A5 JP 2020529105 A JP2020529105 A JP 2020529105A JP 2020529105 A JP2020529105 A JP 2020529105A JP 2020530175 A5 JP2020530175 A5 JP 2020530175A5
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program code
calculation
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pattern
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JP2020529105A
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JP7245833B2 (ja
JPWO2019028253A5 (enExample
JP2020530175A (ja
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JP2020529105A 2017-08-03 2018-08-02 構成可能なハードウェアの実行時の最適化 Active JP7245833B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762540849P 2017-08-03 2017-08-03
US62/540,849 2017-08-03
US201762558090P 2017-09-13 2017-09-13
US62/558,090 2017-09-13
PCT/US2018/045008 WO2019028253A1 (en) 2017-08-03 2018-08-02 EXECUTION OPTIMIZATION OF CONFIGURABLE EQUIPMENT

Publications (4)

Publication Number Publication Date
JP2020530175A JP2020530175A (ja) 2020-10-15
JP2020530175A5 true JP2020530175A5 (enExample) 2021-09-09
JPWO2019028253A5 JPWO2019028253A5 (enExample) 2022-11-28
JP7245833B2 JP7245833B2 (ja) 2023-03-24

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JP2020529105A Active JP7245833B2 (ja) 2017-08-03 2018-08-02 構成可能なハードウェアの実行時の最適化

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US (1) US10817309B2 (enExample)
EP (1) EP3662384A4 (enExample)
JP (1) JP7245833B2 (enExample)
KR (1) KR102668340B1 (enExample)
CN (1) CN111164583B (enExample)
SG (1) SG11202000752RA (enExample)
WO (1) WO2019028253A1 (enExample)

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EP3682353A4 (en) 2017-09-13 2021-12-08 Next Silicon Ltd DIRECTED AND INTERCONNECTED GRID DATA FLOW ARCHITECTURE
CN110704360B (zh) * 2019-09-29 2022-03-18 华中科技大学 一种基于异构fpga数据流的图计算优化方法
KR20220139304A (ko) * 2019-12-30 2022-10-14 스타 알리 인터내셔널 리미티드 구성 가능한 병렬 계산을 위한 프로세서
US11269526B2 (en) 2020-04-23 2022-03-08 Next Silicon Ltd Interconnected memory grid with bypassable units
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US12333231B1 (en) 2024-11-03 2025-06-17 Next Silicon Ltd. Reconfigurable integrated circuit (IC) device and a system and method of configuring thereof

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