JP7229124B2 - メモリ装置 - Google Patents
メモリ装置 Download PDFInfo
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- JP7229124B2 JP7229124B2 JP2019150528A JP2019150528A JP7229124B2 JP 7229124 B2 JP7229124 B2 JP 7229124B2 JP 2019150528 A JP2019150528 A JP 2019150528A JP 2019150528 A JP2019150528 A JP 2019150528A JP 7229124 B2 JP7229124 B2 JP 7229124B2
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- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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Description
Claims (20)
- メインクロック信号を受信し、内部メインクロック信号をコア回路に提供するクロックバッファと、
データクロック信号を受信するデータクロックバッファと、
前記データクロック信号に基づいて、前記データクロック信号に関するレイテンシ情報を生成し、該当レイテンシ情報をデータ入出力回路に提供するレイテンシ制御回路とを含み、
前記レイテンシ制御回路は、
前記データクロック信号に基づいて、複数の2分周クロック信号を生成する第1の分周器と、
前記2分周クロック信号のうち、2つの2分周クロック信号を分周して、複数の4分周クロック信号を生成する第2の分周器と、
クロック同期化信号に応答して、前記2分周クロック信号のうち、他の2つの2分周クロック信号と前記データクロック信号の間の同期/非同期を示す2分周整列信号を出力する第1の同期検出器と、
前記2分周整列信号に基づいて、自動で前記4分周クロック信号の位相を判別し、前記判別された4分周クロック信号の位相に基づいて、データの書込み・読出しに関する前記メインクロック信号のレイテンシを調節して、前記レイテンシ情報を出力するレイテンシ選択器とを含むメモリ装置。 - 前記レイテンシ選択器は、前記2分周整列信号に応答して、前記4分周クロック信号と前記データクロック信号の間の同期/非同期を示す4分周整列信号を生成し、前記4分周整列信号の少なくとも1つ及び対応する前記4分周クロック信号の少なくとも1つを用いて、前記レイテンシを調節する請求項1に記載のメモリ装置。
- 前記2分周クロック信号は、第1~第4の2分周クロック信号を含み、
前記2つの2分周クロック信号は、互いに180度の位相差を有する前記第2及び第4の2分周クロック信号を含み、
前記他の2つの2分周クロック信号は、互いに180度の位相差を有する前記第1及び第3の2分周クロック信号を含み、
前記第1の2分周クロック信号と前記第2の2分周クロック信号は、互いに90度の位相差を有する請求項1又は2に記載のメモリ装置。 - 前記第1の同期検出器は、前記クロック同期化信号の活性化区間で、前記第2の2分周クロック信号の立下りエッジが感知されると、前記2分周整列信号のうち、第1の2分周整列信号を活性化させる請求項3に記載のメモリ装置。
- 前記第1の同期検出器は、前記クロック同期化信号の活性化区間で、前記第4の2分周クロック信号の立下りエッジが感知されると、前記2分周整列信号のうち、第2の2分周整列信号を活性化させる請求項3に記載のメモリ装置。
- 前記レイテンシ選択器は、
前記2分周整列信号のうち、第1の2分周整列信号に基づいて、前記4分周クロック信号のうち、第1及び第2の4分周クロック信号と前記データクロック信号の間の同期/非同期を示す第1及び第2の4分周整列信号を出力する第2の同期検出器と、
前記2分周整列信号のうち、第2の2分周整列信号に基づいて、前記4分周クロック信号のうち、第3及び第4の4分周クロック信号と前記データクロック信号の間の同期/非同期を示す第3及び第4の4分周整列信号を出力する第3の同期検出器と、
前記第1~第4の4分周クロック信号を受信し、前記第1~第4の4分周整列信号に基づいて、前記第1~第4の4分周クロック信号のそれぞれに関するレイテンシを調節し、前記調節されたレイテンシのいずれか1つを、前記レイテンシ情報として選択する選択回路とを含む請求項1~5のうち何れか一項に記載のメモリ装置。 - 前記選択回路は、前記第1~第4の4分周整列信号のうち、活性化される1つに対応する、前記1~第4の4分周クロック信号のいずれか1つに関するレイテンシを調節し、前記調節されたレイテンシを、前記レイテンシ情報として出力する請求項6に記載のメモリ装置。
- 前記第2の同期検出器は、
前記第1の2分周整列信号のエッジで、前記第1の4分周クロック信号がロウレベルである場合、前記第1の4分周整列信号を活性化させ、
前記第1の2分周整列信号のエッジで、前記第2の4分周クロック信号がロウレベルである場合、前記第2の4分周整列信号を活性化させる請求項6に記載のメモリ装置。 - 前記第3の同期検出器は、
前記第2の2分周整列信号のエッジで、前記第3の4分周クロック信号がロウレベルである場合、前記第3の4分周整列信号を活性化させ、
前記第2の2分周整列信号のエッジで前記第4の4分周クロック信号がロウレベルである場合、前記第4の4分周整列信号を活性化させる請求項6に記載のメモリ装置。 - 前記第2の同期検出器は、
前記第1の4分周クロック信号を反転させる第1のインバータと、
前記第1の2分周整列信号のエッジで、前記第1のインバータの出力をラッチし、前記第1の4分周整列信号として出力する第1のフリップフロップと、
前記第2の4分周クロック信号を反転させる第2のインバータと、
前記第1の2分周整列信号のエッジで、前記第2のインバータの出力をラッチし、前記第2の4分周整列信号として出力する第2のフリップフロップとを含む請求項6に記載のメモリ装置。 - 前記第3の同期検出器は、
前記第3の4分周クロック信号を反転させる第3のインバータと、
前記第2の2分周整列信号のエッジで、前記第3のインバータの出力をラッチし、前記第3の4分周整列信号として出力する第3のフリップフロップと、
前記第4の4分周クロック信号を反転させる第4のインバータと、
前記第2の2分周整列信号のエッジで、前記第4のインバータの出力をラッチし、前記第4の4分周整列信号として出力する第4のフリップフロップとを含む請求項10に記載のメモリ装置。 - 前記選択回路は、
前記メインクロック信号に関するレイテンシを受信し、前記第1の4分周クロック信号を用いて、前記レイテンシを調節し、前記第1の4分周整列信号が活性化される場合、前記調節された第1のレイテンシを、第1のサブレイテンシ情報として出力する第1のレイテンシ調節回路と、
前記メインクロック信号に関するレイテンシを受信し、前記第2の4分周クロック信号を用いて、前記レイテンシを調節し、前記第2の4分周整列信号が活性化される場合、前記調節された第2のレイテンシを、第2のサブレイテンシ情報として出力する第2のレイテンシ調節回路と、
前記メインクロック信号に関するレイテンシを受信し、前記第3の4分周クロック信号を用いて、前記レイテンシを調節し、前記第3の4分周整列信号が活性化される場合、前記調節された第3のレイテンシを、第3のサブレイテンシ情報として出力する第3のレイテンシ調節回路と、
前記メインクロック信号に関するレイテンシを受信し、前記第4の4分周クロック信号を用いて、前記レイテンシを調節し、前記第4の4分周整列信号が活性化される場合、前記調節された第4のレイテンシを、第4のサブレイテンシ情報として出力する第4のレイテンシ調節回路と、
前記第1~第4のサブレイテンシ情報に対してオア演算を行い、前記レイテンシ情報を出力するオアゲートとを含む請求項6に記載のメモリ装置。 - 前記第1~第4のレイテンシ調節回路のいずれか1つは、前記第1~第4の4分周整列信号に応答して活性化される請求項12に記載のメモリ装置。
- 前記選択回路は、
前記メインクロック信号に関するレイテンシを受信し、前記第1の4分周クロック信号を用いて、前記レイテンシを調節し、第1のサブレイテンシ情報として出力する第1のレイテンシ調節回路と、
前記メインクロック信号に関するレイテンシを受信し、前記第2の4分周クロック信号を用いて、前記レイテンシを調節し、第2のサブレイテンシ情報として出力する第2のレイテンシ調節回路と、
前記メインクロック信号に関するレイテンシを受信し、前記第3の4分周クロック信号を用いて、前記レイテンシを調節し、第3のサブレイテンシ情報として出力する第3のレイテンシ調節回路と、
前記メインクロック信号に関するレイテンシを受信し、前記第4の4分周クロック信号を用いて、前記レイテンシを調節し、第4のサブレイテンシ情報として出力する第4のレイテンシ調節回路と、
前記第1~第4の4分周整列信号に応答して、前記第1~第4のサブレイテンシ情報のいずれか1つを選択し、前記レイテンシ情報として出力するマルチプレクサとを含む請求項6に記載のメモリ装置。 - 複数のバンクアレイを備えるメモリセルアレイと、
メインクロック信号に同期化されたクロック同期化コマンドを受信し、クロック同期化信号を出力するコマンドデコーダと、
アドレス信号に含まれるバンクアドレスに基づいて、前記バンクアレイを制御するバンク制御信号を出力するバンク制御ロジックと、
データクロック信号に基づいて、複数の2分周クロック信号を生成し、前記クロック同期化信号に応答して、前記2分周クロック信号のいずれか1つを、内部データクロック信号に出力するクロック同期化回路と、
前記2分周クロック信号の一部に基づいて、4分周クロック信号を生成し、前記クロック同期化信号に応答して、前記2分周クロック信号と前記データクロック信号の同期/非同期を示す2分周整列信号を生成し、前記2分周整列信号に応答して、前記4分周クロック信号の位相を判別し、前記判別された4分周クロック信号の位相に基づいて、前記メインクロック信号のレイテンシを調節し、前記内部データクロック信号に関するレイテンシ情報を出力するレイテンシ制御回路と、
前記レイテンシ情報に対応するレイテンシにより、前記内部データクロック信号を用いて、データを受信・伝送するデータ入出力回路とを含み、
前記バンクアレイのそれぞれは、複数のワード線と複数のビット線に連結される複数のダイナミックメモリセルを含むメモリ装置。 - 前記レイテンシ制御回路は、
前記2分周クロック信号のうち、2つの2分周クロック信号を分周して、前記複数の4分周クロック信号を生成する分周器と、
前記クロック同期化信号に応答して、前記2分周クロック信号のうち、他の2つの2分周クロック信号と、前記データクロック信号の間の同期/非同期を示す前記2分周整列信号を出力する第1の同期検出器と、
前記2分周整列信号に応答して、自動で前記4分周クロック信号の位相を判別し、前記判別された前記4分周クロック信号の位相に基づいて、前記メインクロック信号の前記レイテンシを調節し、前記レイテンシ情報を出力するレイテンシ選択器とを含む請求項15に記載のメモリ装置。 - 前記レイテンシ選択器は、前記2分周整列信号に応答して、前記4分周クロック信号と前記データクロック信号の間の同期/非同期を示す4分周整列信号を生成し、前記4分周整列信号の少なくとも1つ、及び対応する前記4分周クロック信号の少なくとも1つを用いて、前記レイテンシを調節する請求項16に記載のメモリ装置。
- 更に、前記データに対して、ECC符号化及びECC復号化を行うECCエンジンを含む請求項15~17のうち何れか一項に記載のメモリ装置。
- 更に、前記データクロック信号を受信し、前記データクロック信号を、前記クロック同期化回路及び前記レイテンシ制御回路に提供するデータクロックバッファを含む請求項15~18のうち何れか一項に記載のメモリ装置。
- 少なくとも1つの緩衝ダイと、
前記少なくとも1つの緩衝ダイの上部に積層され、複数の貫通ラインを介して、データを通信する複数のメモリダイとを含み、
前記複数のメモリダイの少なくとも1つは、データを格納するメモリセルアレイを含み、
前記少なくとも1つの緩衝ダイは、
データクロック信号に基づいて、複数の2分周クロック信号を生成し、クロック同期化信号に応答して、前記2分周クロック信号のいずれか1つを、内部データクロック信号に出力するクロック同期化回路と、
前記2分周クロック信号の一部に基づいて、4分周クロック信号を生成し、クロック同期化信号に応答して、前記2分周クロック信号と前記データクロック信号の同期/非同期を示す2分周整列信号を生成し、前記2分周整列信号に応答して、前記4分周クロック信号の位相を判別し、前記判別された4分周クロック信号の位相に基づいて、メインクロック信号のレイテンシを調節し、前記内部データクロック信号に関するレイテンシ情報を出力するレイテンシ制御回路と、
前記レイテンシ情報に対応するレイテンシにより、前記内部データクロック信号を用いて、データを受信・伝送するデータ入出力回路とを含むメモリ装置。
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