JP7190880B2 - 半導体膜の形成方法及び成膜装置 - Google Patents
半導体膜の形成方法及び成膜装置 Download PDFInfo
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Description
(第1の実施形態)
第1の実施形態の半導体膜の形成方法について、ポリシリコン膜を形成する場合を例に挙げて説明する。図1は、第1の実施形態のポリシリコン膜の形成方法の一例を示すフローチャートである。図2は、図1の各工程における温度とガス供給状態の一例を示す図である。
次に、第2の実施形態の半導体膜の形成方法について、ポリシリコン膜を形成する場合を例に挙げて説明する。図4は、第2の実施形態のポリシリコン膜の形成方法の一例を示すフローチャートである。図5は、図4の各工程における温度とガス供給状態の一例を示す図である。
上記の半導体膜の形成方法を実施できる成膜装置について、多数枚の基板に対して一括で熱処理を行うバッチ式の縦型熱処理装置を例に挙げて説明する。但し、成膜装置は、バッチ式の装置に限定されるものではなく、例えば基板を1枚ずつ処理する枚葉式の装置であってもよい。
実施例1では、真空引き工程の時間を制御することでポリシリコン膜のグレインサイズを制御できることを確認するために行った実験結果について説明する。実施例1では、上記の縦型熱処理装置1を用いて、前述のポリシリコン膜の形成方法におけるステップS11~S16を行った。シード層形成工程では、処理温度を380℃、圧力を1Torr(133Pa)、シード層用のシリコン原料ガスをSi2H6とするプロセス条件で、厚さが2nmのシード層を形成した。また、シリコン膜形成工程では、処理温度を470℃、圧力を0.4Torr(53Pa)、シリコン原料ガスをSiH4とするプロセス条件で、厚さが28nmのアモルファスシリコン膜を形成した。また、真空引き工程の時間を0分、5分、60分と変化させた。さらに、EBSD(Electron Back Scatter Diffraction Patterns)法により、形成したポリシリコン膜のグレインサイズを評価した。
実施例2では、シード層形成工程の時間を制御することでポリシリコン膜のグレインサイズを制御できることを確認するために行った実験結果について説明する。実施例2では、上記の縦型熱処理装置1を用いて、前述のポリシリコン膜の形成方法におけるステップS21,S22,S23,S25,S26を行った。シード層形成工程では、処理温度を350℃、圧力を1Torr(133Pa)、シード層用のシリコン原料ガスをアミノシラン系ガスとするプロセス条件で、第1のシード層を形成した。また、処理温度を350℃、圧力を4Torr(533Pa)、シード層用のシリコン原料ガスをSi2H6とするプロセス条件で、第1のシード層の上に第2のシード層を形成した。このとき、第2のシード層を形成する際の時間を0分、50分、150分と変化させた。また、シリコン膜形成工程では、処理温度を520℃、圧力を0.3Torr(40Pa)、シリコン原料ガスをSiH4、不純物含有ガスをPH3とするプロセス条件で、リンがドープされたアモルファスシリコン膜を28nmの厚さで形成した。さらに、EBSD法により、形成したポリシリコン膜のグレインサイズを評価した。
34 反応管
40 ガス供給手段
41 排気手段
42 加熱手段
95 制御手段
Claims (6)
- 基板の上に所望のグレインサイズを有する結晶化された半導体膜を形成する方法であって、
処理容器内に収容された前記基板の上にシード層を形成する工程と、
前記シード層が形成された前記基板を収容した状態で前記処理容器内の圧力を中真空以下に真空引きする工程と、
前記処理容器内を真空引きした後、前記シード層の上にアモルファス半導体膜を形成する工程と、
前記アモルファス半導体膜を熱処理により結晶化させる工程と、
を有し、
前記真空引きする工程は、前記所望のグレインサイズに応じた時間、前記処理容器内を排気する、
半導体膜の形成方法。 - 前記シード層を形成する工程の後に行われ、水素雰囲気で前記基板を第1の温度から前記第1の温度よりも高い第2の温度に昇温する工程と、
前記基板が前記第2の温度に昇温した後、水素雰囲気で温度を安定化させる工程と、
を有し、
前記真空引きする工程は、前記温度を安定化させる工程の後に行われる、
請求項1に記載の半導体膜の形成方法。 - 前記真空引きする工程は、前記処理容器内にガスを供給することなく行われる、
請求項1又は2に記載の半導体膜の形成方法。 - 前記シード層を形成する工程は、前記基板に一分子中に2つ以上のSiを含む高次シラン系ガス、アミノシラン系ガス、水素化シランガスとハロゲン含有シリコンガスの混合ガスの少なくともいずれかを含むガスを供給する工程を含み、
前記アモルファス半導体膜を形成する工程は、前記基板にシリコン原料ガスを供給する工程を含む、
請求項1乃至3のいずれか一項に記載の半導体膜の形成方法。 - 前記アモルファス半導体膜は、アモルファスシリコン膜である、
請求項1乃至4のいずれか一項に記載の半導体膜の形成方法。 - 基板の上に所望のグレインサイズを有する結晶化された半導体膜を形成する成膜装置であって、
前記基板を収容する処理容器と、
前記処理容器内にガスを供給する供給部と、
前記処理容器内を排気する排気部と、
前記基板を加熱する加熱部と、
制御部と、
を有し、
前記制御部は、
前記処理容器内に収容された前記基板の上にシード層を形成する工程と、
前記シード層が形成された前記基板を収容した状態で前記処理容器内の圧力を中真空以下に真空引きする工程と、
前記処理容器内を真空引きした後、前記シード層の上にアモルファス半導体膜を形成する工程と、
前記アモルファス半導体膜を熱処理により結晶化させる工程と、
を実行するように前記供給部、前記排気部及び前記加熱部を制御するよう構成され、
前記制御部は、前記真空引きする工程において、前記所望のグレインサイズに応じた時間、前記処理容器内を排気するように前記排気部を制御するよう構成される、
成膜装置。
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| KR1020190150886A KR102696672B1 (ko) | 2018-11-26 | 2019-11-22 | 반도체막의 형성 방법 및 성막 장치 |
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| US20200168455A1 (en) | 2020-05-28 |
| US11114297B2 (en) | 2021-09-07 |
| JP2020088175A (ja) | 2020-06-04 |
| KR20200062050A (ko) | 2020-06-03 |
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