JP7171705B2 - 多層スタックを使用したデバイスの作製 - Google Patents
多層スタックを使用したデバイスの作製 Download PDFInfo
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- JP7171705B2 JP7171705B2 JP2020512459A JP2020512459A JP7171705B2 JP 7171705 B2 JP7171705 B2 JP 7171705B2 JP 2020512459 A JP2020512459 A JP 2020512459A JP 2020512459 A JP2020512459 A JP 2020512459A JP 7171705 B2 JP7171705 B2 JP 7171705B2
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- 238000000034 method Methods 0.000 claims description 67
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- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 15
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- 229910052782 aluminium Inorganic materials 0.000 claims description 6
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- 238000000926 separation method Methods 0.000 description 2
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- 229920001486 SU-8 photoresist Polymers 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- UZKWTJUDCOPSNM-UHFFFAOYSA-N methoxybenzene Substances CCCCOC=C UZKWTJUDCOPSNM-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/094—Multilayer resist systems, e.g. planarising layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Description
100 金属層
101 保護層
102 支持層
103 フォトレジスト層
104 フォトレジスト領域
Claims (19)
- デバイスを作製する方法であって、
主面を有する基板上に多層スタックを形成するステップであって、前記多層スタックが、
前記基板の前記主面上に形成された第1の層であって、第1のポリマー材料である第1の層、
前記第1の層上に形成された支持層であって、第2のポリマー材料である支持層、および
前記支持層上に形成されたフォトレジスト層
を含む、形成するステップと、
前記フォトレジスト層が前記支持層によってアンダーカットされ、前記支持層が前記第1の層によってオーバーカットされるように少なくとも1つの開口を形成するために前記多層スタックをパターニングするステップと、
前記基板を異方的にドライエッチングするステップと
を含む、方法。 - 前記フォトレジスト層および前記第1の層が、揃えられたそれぞれのエッジを有する、請求項1に記載の方法。
- 前記第1のポリマー材料が、電子ビーム照射に反応する、請求項1または2に記載の方法。
- 前記第1のポリマー材料がメタクリル酸メチルである、請求項1から3のいずれか一項に記載の方法。
- 前記第1のポリマー材料がポリメタクリル酸メチルである、請求項1から4のいずれか一項に記載の方法。
- 前記第1のポリマー材料がメタクリル酸である、請求項1または2に記載の方法。
- 前記多層スタックをパターニングするステップが、
現像液を使用して前記フォトレジスト層を現像するステップ
を含む、請求項1から6のいずれか一項に記載の方法。 - 前記支持層が、前記現像液に溶解する、請求項7に記載の方法。
- 前記現像液がアルカリである、請求項7または8に記載の方法。
- 前記第2のポリマー材料が、電子ビーム照射に反応する、請求項1から9のいずれか一項に記載の方法。
- 前記第2のポリマー材料がポリジメチルグルタルイミド(PMGI)である、請求項1から10のいずれか一項に記載の方法。
- 前記第2のポリマー材料がメタクリル酸メチルである、請求項1から10のいずれか一項に記載の方法。
- 前記第2のポリマー材料がポリメタクリル酸メチルである、請求項1から10または12のいずれか一項に記載の方法。
- 前記第2のポリマー材料がメタクリル酸である、請求項1から10のいずれか一項に記載の方法。
- 前記多層スタックをパターニングするステップが、
プラズマアッシングを行うステップ
を含む、請求項1から14のいずれか一項に記載の方法。 - 前記デバイスが、量子情報処理デバイスである、請求項1から15のいずれか一項に記載の方法。
- 前記基板が、前記基板の前記主面上に配置された金属層を含む、請求項1から16のいずれか一項に記載の方法。
- 前記基板がシリコンを含み、前記金属層がアルミニウムを含む、請求項17に記載の方法。
- 請求項1から18のいずれか一項に記載の方法によって取得可能なデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762552743P | 2017-08-31 | 2017-08-31 | |
US62/552,743 | 2017-08-31 | ||
PCT/US2017/065018 WO2019045763A1 (en) | 2017-08-31 | 2017-12-07 | FABRICATION OF A DEVICE USING A MULTILAYER STACK |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020532865A JP2020532865A (ja) | 2020-11-12 |
JP7171705B2 true JP7171705B2 (ja) | 2022-11-15 |
Family
ID=60788720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020512459A Active JP7171705B2 (ja) | 2017-08-31 | 2017-12-07 | 多層スタックを使用したデバイスの作製 |
Country Status (8)
Country | Link |
---|---|
US (1) | US11935748B2 (ja) |
EP (1) | EP3676882B1 (ja) |
JP (1) | JP7171705B2 (ja) |
KR (1) | KR102400989B1 (ja) |
CN (1) | CN111095584A (ja) |
AU (1) | AU2017429631C1 (ja) |
CA (1) | CA3074121A1 (ja) |
WO (1) | WO2019045763A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN112320752A (zh) * | 2019-08-05 | 2021-02-05 | 上海新微技术研发中心有限公司 | 负性光刻胶图形化膜层的制备方法 |
EP4009387B1 (en) | 2020-12-07 | 2023-06-07 | IQM Finland Oy | Josephson junction fabrication method |
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2017
- 2017-12-07 JP JP2020512459A patent/JP7171705B2/ja active Active
- 2017-12-07 KR KR1020207008406A patent/KR102400989B1/ko active IP Right Grant
- 2017-12-07 EP EP17818714.2A patent/EP3676882B1/en active Active
- 2017-12-07 AU AU2017429631A patent/AU2017429631C1/en active Active
- 2017-12-07 CN CN201780094508.4A patent/CN111095584A/zh active Pending
- 2017-12-07 US US16/640,411 patent/US11935748B2/en active Active
- 2017-12-07 WO PCT/US2017/065018 patent/WO2019045763A1/en active Search and Examination
- 2017-12-07 CA CA3074121A patent/CA3074121A1/en active Pending
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KR102400989B1 (ko) | 2022-05-23 |
US20200365397A1 (en) | 2020-11-19 |
CA3074121A1 (en) | 2019-03-07 |
EP3676882B1 (en) | 2021-06-30 |
AU2017429631B2 (en) | 2021-02-25 |
US11935748B2 (en) | 2024-03-19 |
AU2017429631A1 (en) | 2020-03-05 |
AU2017429631C1 (en) | 2022-07-14 |
WO2019045763A1 (en) | 2019-03-07 |
JP2020532865A (ja) | 2020-11-12 |
CN111095584A (zh) | 2020-05-01 |
EP3676882A1 (en) | 2020-07-08 |
KR20200040862A (ko) | 2020-04-20 |
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