JP7167662B2 - Thin film transistor array and manufacturing method thereof - Google Patents

Description

The present invention relates to a thin film transistor array and its manufacturing method.

2. Description of the Related Art In recent years, research and development of printed electronics, in which functional elements are produced by printing using inked functional materials, have been actively conducted.

As for printed electronics, the development of organic functional elements using organic materials, such as organic EL elements, organic solar cells, and organic thin-film transistors, has been actively carried out. These organic functional elements generally require pattern formation of a functional material layer having a thickness of several nanometers to several micrometers on a substrate.

There are various printing methods used in the field of printed electronics. Typical examples include traditional printing methods such as relief printing, intaglio printing, planographic printing, and stencil printing, as well as relatively new printing methods such as ink jet printing. etc., can be selected in a variety of ways. Relief printing, intaglio printing, lithographic printing, stencil printing, etc. are called plate printing because a plate is created and used for the desired printing pattern. On the other hand, ink jet printing is called plateless printing because ink is directly transferred to a desired position and no plate is used regardless of the pattern.

In addition, each printing method is further subdivided according to the materials used. For example, in letterpress printing, a printing method that uses a printing plate called a flexographic plate made of resin, rubber, or the like is sometimes called flexographic printing to distinguish it from others.

In addition, there are relatively simple film forming methods such as spin coating and bar coating. However, these methods are good at uniformly forming a film over the entire surface or almost the entire surface of a substrate, and are not suitable for patterning and separate coating of materials. Therefore, in general, patterning is performed using photolithography or the like in combination with film formation by itself.

In this way, there are various printing methods, each of which has advantages and disadvantages. Therefore, in printed electronics, it is important to select the appropriate printing method according to the target structure, materials, functionality, etc. is necessary.

The advantages of letterpress printing, especially flexographic printing, in printed electronics are that continuous printing is stable, ink selectivity is wide, and relatively low to high viscosity inks can be printed. Another reason is that it is difficult to scratch the printed material due to the use of a flexible plate.

The use of the letterpress printing method in the field of printed electronics will be described using organic thin-film transistors using organic semiconductor inks, which have been attracting attention in recent years, as an example. For example, among letterpress printing methods, a technique of forming a semiconductor layer using flexographic printing (see Patent Document 1) has already been developed.

An example of a letterpress printing apparatus will be described with reference to FIG. The letterpress printing apparatus shown in FIG. 10 includes a rotary plate cylinder 307 on which a printing letterpress 308 is mounted, an anilox roll 306 for supplying ink 305 to the plate surface of the letterpress 308, and ink 305 on the anilox roll 306. It has an ink chamber 303 for supplying ink, a doctor 304 for scraping off excess ink on the anilox roll, and a substrate platen 301 on which a substrate to be printed 302 is placed. As the doctor 304, a blade made of a metal plate, a resin plate, or the like, or a roll having an outer circumference formed of resin, rubber, or the like is often used.

In flexographic printing, when an independent pattern such as a dot is formed, the printed matter is strongly affected by the flow and drying of the ink on the plate, so that the film thickness and shape are likely to vary. For this reason, research has been conducted on techniques such as a stripe-shaped semiconductor layer formed across a plurality of channels (see Patent Document 2).

JP-A-2006-63334 Japanese Patent Application Laid-Open No. 2008-235861 WO2016/067591

Although not limited to flexographic printing, printed matter formed by flexographic printing tends to exhibit a mountain-shaped cross-sectional shape (hereinafter, mountain-shaped) in which the film thickness is thicker at the central portion than at the end portions. In addition, the low uniformity of the film thickness obtained by the printing method may cause deterioration of the uniformity of transistor characteristics in a transistor array in which the semiconductor layer is formed by the printing method. For this reason, for example, research has been conducted on a technique for obtaining more appropriate transistor characteristics by controlling the mountain shape when semiconductor layers forming a transistor array are formed by printing (see Patent Document 3).

However, depending on the material and formation layer, the mountain shape may not provide sufficient characteristics. For example, the effect of a protective layer for protecting a semiconductor layer from the external environment and upper laminated films is particularly pronounced in a bottom-contact type thin film transistor.

In a bottom-contact thin film transistor, the lower portion of the semiconductor layer contributes most to the transistor function, so the thicker the semiconductor layer, the less likely it is to be affected by external factors such as oxygen and ozone. However, since it is generally difficult to completely prevent external influences only by adjusting the thickness of the semiconductor layer, a protective layer is formed on the semiconductor layer.

For example, if the semiconductor layer is flat, the film thickness required for the protective layer is constant, but if the semiconductor is mountain-shaped, the film thickness of the protective layer needs to be thicker at the edges where the semiconductor layer is thinner. be. Therefore, when forming a solid flat film as a protective layer by a spin coating method or the like, it is sufficient to form a flat film with a required film thickness at the edges. A thick portion of the protective layer overlaps with the thick portion, and a thin portion of the protective layer overlaps with the thin portion of the semiconductor layer, and the transistor characteristics of the thin end portions of the semiconductor layer and the protective layer deteriorate.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film transistor array that is less susceptible to external influences and has highly uniform transistor characteristics.

One aspect of the invention for solving the above problems is at least an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a channel region between the source and drain electrodes. A thin film transistor array in which thin film transistor elements including a semiconductor layer and a protective layer formed on the semiconductor layer are arranged in a matrix on a substrate, wherein the protective layer covers a plurality of thin film transistor elements in a striped shape so as to cover a channel region. and the cross section of the protective layer cut along a plane orthogonal to the long axis direction of the stripe shape has a shape having regions having a thicker film thickness than the center on both sides of the center in the short axis direction of the stripe shape, and a semiconductor The layer is a thin film transistor array in which the semiconductor layer cross section cut along the stripe-shaped long axis direction has a shape in which the film thickness gradually decreases from the center toward both ends in the short axis direction.

In addition, in the protective layer cross section, the relationship between the distance A in the short axis direction between the thickest portions of each region where the film thickness is thicker than the center and the distance B between both ends in the short axis direction of the protective layer is
BA≦20 μm
may be

Also, the relationship between the distance B between both ends of the protective layer in the minor axis direction and the distance C between both ends of the semiconductor layer in the minor axis direction is
C<B
may be

In addition, in the cross section of the protective layer, the relationship between the distance A in the minor axis direction between the thickest portions of each of the regions thicker than the center and the distance C between both ends in the minor axis direction of the semiconductor layer is
|AC|≦10 μm
may be

Further, the distance D between the centers of the protective layer and the semiconductor layer in the short axis direction may be 10 μm or less.

Also, the relationship between the distance M between both ends of the channel region in the minor axis direction and the distance C between both ends of the semiconductor layer in the minor axis direction is
0≦MC≦40 μm
may be

Further, the distance E in the minor axis direction between the thickest portion of the semiconductor layer cross section and the center of the channel region in the minor axis direction may be 10 μm or less.

Another aspect of the present invention is a method for manufacturing the thin film transistor array described above, which includes the step of forming a protective layer by letterpress printing.

According to the present invention, by printing a protective layer having a cross-sectional shape that is recessed in the center and thicker in the vicinity of the edge than in the center, it is less likely to be affected by the outside, and the uniformity of the transistor characteristics and the improvement of the transistor characteristics are improved. A tall thin film transistor array can be provided.

1 is a schematic cross-sectional view of a thin film transistor element according to an embodiment of the present invention; FIG. Cross-sectional schematic diagram of a thin film transistor element for explaining the film thickness of the protective layer Cross-sectional schematic diagram of a thin film transistor element for explaining the film thickness of the protective layer Cross-sectional schematic diagram of a thin film transistor element for explaining the film thickness of the protective layer Cross-sectional schematic diagram of a thin film transistor element for explaining the film thickness of the protective layer The figure which shows the formation method of the protective layer using the ink transfer process by the letterpress printing method. The figure which shows the formation method of the protective layer using the ink transfer process by the letterpress printing method. FIG. 2 is a diagram showing the positional relationship of each part of a thin film transistor element according to an embodiment of the present invention; FIG. 2 is a diagram showing the positional relationship of each part of a thin film transistor element according to an embodiment of the present invention; A diagram showing a configuration example of a general letterpress printing apparatus

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, the same or corresponding constituent elements are denoted by the same reference numerals, and overlapping descriptions among the embodiments are omitted.

FIG. 1 shows a cross-sectional view of a bottom contact-bottom gate type thin film transistor element 1 used in a thin film transistor array according to one embodiment of the present invention.

In the thin film transistor element 1, a gate electrode 103 and a capacitor electrode (not shown) are formed on an insulating substrate 101, and a gate insulating film 102 is laminated thereon. A source electrode 104 and a drain electrode 105 are formed on the gate insulating film 102 . The thin film transistor element 1 is formed by forming the semiconductor layer 106 on the gate insulating film 102 in the channel region overlapping the gate electrode 103 in plan view and sandwiched between the source electrode 104 and the drain electrode 105 . In the thin film transistor element 1, a protective layer 107, an interlayer insulating film 108, an upper pixel electrode, and the like may be appropriately formed on the semiconductor layer 106 as necessary (partially omitted in the drawing). Note that in the drawings used for the following description, illustration of some configurations that are not mentioned may be omitted as appropriate.

When the semiconductor layer 106 is formed by flexographic printing, as shown in FIG. 2, it has a mountain-shaped cross-sectional shape in which the thickness is the thickest in the center and becomes thinner toward the ends. Therefore, the film thickness 109 required for the protective layer 107 for protecting the semiconductor layer 106 from the external environment increases from the center toward the end. However, if the protective layer 107 is formed by general flexographic printing, it will have a shape similar to that of the semiconductor layer 106, and as shown in FIG.

As countermeasures, it is conceivable to form the protective layer 107 with a wider patterning area than the semiconductor layer 106, or to make the film thickness of the protective layer 107 extremely thick (FIG. 4). However, none of them can be said to be the optimum countermeasure in view of the patterning property and the utilization efficiency of the area in the array.

A partial cross-sectional view of a thin film transistor device 1 according to one embodiment of the present invention is shown in FIG. As shown in FIG. 5, in the thin film transistor element 1 according to the present embodiment, the vicinity of the end portion is sufficiently thick so as to match the film thickness 109 required for the protective layer 107 for protecting the semiconductor layer 106 from the external environment. A protective layer 107 having a cross-sectional shape with a recessed center was formed. As a result, a thin protective layer 107 is applied to a portion where the semiconductor layer 106 is thick and can mitigate the influence of the external environment to some extent, and a thick protective layer 107 is applied to a portion where the semiconductor layer 106 is thin and is strongly affected by the external environment. well formed.

The semiconductor layer 106 can be formed in a stripe shape so as to straddle a plurality of thin film transistors. In the semiconductor layer 106 formed in a stripe shape, the film thickness in a cross-sectional shape (corresponding to a semiconductor layer cross section in the claims) taken along a plane orthogonal to the long axis direction of the stripe extends from the center to the outside (both ends) in the short axis direction. It becomes a shape that gradually becomes thinner toward the edge. For example, when the flat semiconductor layer 106 is formed by spin coating or the like, there is no problem in using the present invention, but the effect of the present invention is not so great. Further, the protective layer 107 can also be formed in a stripe shape so as to straddle a plurality of thin film transistors. The protective layer 107 formed in a striped shape has a cross-sectional shape (corresponding to a protective layer cross section in the claims) taken along a plane perpendicular to the long axis direction of the striped shape. It is a shape having a portion where the film thickness is thicker (hereinafter also referred to as the thickest portion).

Note that the film thickness of the semiconductor layer 106 here is not the height of the semiconductor layer 106 . That is, the film thickness of the semiconductor layer 106 on the source electrode 104 and the drain electrode 105 is obtained by subtracting the height of the source electrode 104 or the drain electrode 105 from the height of the semiconductor layer 106 . In FIG. 5, the peak (maximum value) of the height of the semiconductor layer 106 is shown to be larger than the film thicknesses of the source electrode 104 and the drain electrode 105, but the maximum film thickness of the semiconductor layer 106 is It may be smaller than or equal to the film thickness (thickness) of the drain electrode 105 . Further, the end portion of the semiconductor layer 106 may be formed to cover the surfaces of the source electrode 104 and the drain electrode 105 on the channel region side, as shown in FIG.

A method of forming the protective layer 107 of the thin film transistor array according to this embodiment will be described with reference to FIGS. 6 and 7 are diagrams showing a method of forming a protective layer by flexographic printing.

First, formation of a protective layer using a general flexographic printing process will be described with reference to FIG. A flexographic plate 203 is inked with an ink 202 in which a protective layer material is dissolved ((a) in FIG. 6). When the flexo plate 203 is pressed against the substrate 201 to be printed, the ink 202 inked on the convex portions of the flexo plate 203 escapes onto the substrate 201 to be printed and the side surface of the flexo plate 203 (FIG. 6(b)). When the flexographic plate 203 is pulled up from the substrate 201 to be printed, the convex portions of the flexographic plate 203 and the substrate 201 to be printed cause ink to scramble, resulting in a lump of semi-dry ink 204 in a convex shape upward (FIG. 6(c)). . If the solvent in the ink does not evaporate extremely, the mass of the semi-dry ink 204 will level as it is and form a flat film. A printed material 205 (protective layer) having a convex mountain shape is formed ((d) in FIG. 6).

Next, the case of forming the protective layer 107 of the present invention using a flexographic printing process will be described. The ink 202 in which the material of the protective layer 107 is dissolved is applied to the flexographic plate 203 ((a) in FIG. 7), and the solvent (ink solvent) in the ink 202 is dried while pressing the flexographic plate 203 against the substrate 201 to be printed. (evaporation) (FIG. 7(b)). If the ink solvent dries while the ink 202 is escaping to the side surface of the flexographic plate 203, the ink 202 becomes semi-dry and becomes a mass of ink 204 with lower leveling properties than usual. After that, even if the flexographic plate 203 is pulled up from the substrate 201 to be printed, the ink flowability is poor, so that the protrusions of the flexographic plate 203 and the substrate 201 to be printed have less contact with the ink than usual ((c in FIG. 7). )), and the leveling property is also poor, so that the printed matter 205 (protective layer 107) is formed while maintaining a somewhat recessed cross-sectional shape ((d) in FIG. 7).

In order to accelerate the drying of the ink solvent in the state of FIG. 7B, a material that dries (evaporates) easily is used as the ink solvent, nitrogen gas or the like is sprayed during transfer, or the substrate 201 is slightly heated during transfer. Alternatively, the outside air around the printing press may be warmed. However, if the ink solvent dries too much, the transfer of the ink itself may be hindered, or a printing defect may occur in which the center of the cross section is not printed instead of the concave cross-sectional shape. It is necessary to make adjustments including the pattern size of the plate.

In addition, by using an ink that originally has a low leveling property, or by using a combination of an ink and a flexographic plate that are poorly wetted to the flexographic plate, it is easier to form a printed matter 205 having a cross-sectional shape with a recessed center. However, it is likely to cause deterioration in printability such as difficulty in inking the flexographic plate, and in-plane stability is reduced, so fine balance adjustment is required.

In order to protect the semiconductor layer 106 by the protective layer 107 required in the present invention, the positional relationship between the protective layer 107 and each layer is important. 8 and 9 are explanatory diagrams of the positional relationship between the protective layer 107 and each layer.

FIG. 8(a) is a plan view showing an example of the channel region and the semiconductor layer 106 sandwiched between the source electrode 104 and the drain electrode 105, and FIG. 8(b) is a corresponding sectional view. In FIG. 8(a), arrows indicate the long axis and short axis directions of the stripe shape. In this description, the distance between both ends of the stripe shape of the semiconductor layer 106 (channel region width) in the minor axis direction of the channel region is defined as the distance M. FIG. A distance E is the center of the distance M, that is, the distance between the center of the channel region and the center of the semiconductor layer 106 in the minor axis direction.

The semiconductor layer 106 straddles a plurality of thin film transistors and is formed in a stripe shape, the short axis direction of the stripe shape is aligned with the width direction of the channel region of the thin film transistor, and the thickness in the short axis direction of the semiconductor layer 106 is the thickest. It is formed such that the distance E in the minor axis direction between the (thick film portion) 402 and the center 401 in the minor axis direction of the channel region is less than or equal to a certain value.

In the thin film transistor element 1 configured as described above, even if the semiconductor layer 106 is misaligned by a degree equal to the channel length when the semiconductor layer 106 is formed, the thick film portion 402 of the semiconductor layer 106 overlaps the channel region. , high transistor characteristics can be obtained. In particular, when plotting the relationship between the film thickness of the semiconductor layer 106 and the ON current of the thin film transistor element 1 at a predetermined voltage, the ON current value tends to saturate at a predetermined film thickness d1. is thicker than its threshold value (film thickness d1), the uniformity of transistor characteristics in the thin film transistor array is improved. Further, when plotting the relationship between the film thickness of the semiconductor layer 106 and the off-current value, the off-current value tends to increase when the thickness exceeds a predetermined film thickness d2.

FIG. 9 is a cross-sectional view when the semiconductor layer 106 and the protective layer 107 are overlaid. In the minor axis direction of the stripe shape, the distance in the minor axis direction between the thickest portions (thickest portions) on both sides of the center of the protective layer 107 is the distance A, and the distance between both ends of the protective layer 107 in the minor axis direction is Distance B is the distance, distance C is the distance between both ends of the semiconductor layer 106 in the minor axis direction, and distance D is the distance between the centers of the protective layer 107 and the semiconductor layer 106 in the minor axis direction.

Regarding the positional relationship of each layer, it is preferable to pattern so that the central portion in the short axis direction of all the layers formed in stripes (patterns) as much as possible overlaps the center in the short axis direction of the channel region. For example, if the distance C corresponding to the width of the semiconductor layer 106 is made extremely larger than the distance M corresponding to the width of the channel region, the effect of the positional relationship is reduced. There is little need to use the present invention if large patterning is acceptable, as it is there for efficiency.

Under such circumstances, the relationship between the distance M corresponding to the width of the channel region and the distance C corresponding to the width of the semiconductor layer 106 is M≦C, and the stability and patterning accuracy of general flexographic printing are satisfied. In view of this, it is even better if a margin of about MC≦40 μm is ensured.
Note that when M=C, MC is 0.

As described above, the protective layer 107 is formed to protect the semiconductor layer 106 from the external environment. need to be However, if the width of the stripe shape of the protective layer 107 becomes extremely thick compared to the width of the stripe shape of the semiconductor layer 106, the part where the thickness of the protective layer 107, which is formed to be thicker than the thickness of the protective layer 107, is thicker becomes the short axis of the semiconductor layer 106. It protrudes greatly from both ends in the direction. On the other hand, if the margins of the widths of the protective layer 107 and the semiconductor layer 106 are formed too precisely, the semiconductor layer 106 may be suddenly separated from the protective layer 107 due to fluctuations in printing accuracy or width accuracy of printed matter. There is a high possibility that the image will be exposed and defective pixels will be created. Therefore, it is necessary that C<B, and it is desirable that B=C+20 μm from the viewpoint of stability.

A major feature of the present invention is that the formed protective layer 107 has a cross-sectional shape with a recessed center, so the cross-sectional shape also needs to be controlled to some extent. As mentioned above, in order to obtain a compact positional relationship and a film shape as much as possible, the distance A between the thickest portions of the protective layer 107, the distance B corresponding to the width of the protective layer 107, and the width of the semiconductor layer 106 The relationship of the corresponding distance C is preferably about |A−C|≦10 μm and BA≦20 μm. Under the thickest part of the protective layer 107, it is desirable that the end of the semiconductor layer 106, which is most vulnerable to external factors, be located in the minor axis direction. In addition, the distance A between the thickest portions of the protective layer 107 is extremely small (narrow) compared to the distance B corresponding to the width of the protective layer 107. If so, the distance C corresponding to the width of the semiconductor layer 106 that can be protected is reduced accordingly, and the utilization efficiency is extremely lowered, which is not preferable.

Also, when the distance E is large (that is, the distance between the center of the semiconductor layer 106 and the center of the channel region in the minor axis direction is large), the thickest part of the semiconductor layer 106 moves away from the center of the channel region. . As a result, the substantial thickness of the semiconductor layer 106 overlying the channel region is reduced, and the device characteristics of the thin film transistor device 1 are degraded. Such a tendency is more conspicuous in the source electrode 104 and the drain electrode 105 facing each other in a linear shape than in the comb-shaped source electrode 104 and the drain electrode 105 shown in FIG. Therefore, it is preferable that the distance E is as small as possible, and specifically, it is preferably 10 μm or less.

Also, when the distance D is large (that is, the distance between the center of the protective layer 107 and the center of the semiconductor layer 106 in the minor axis direction is large), the semiconductor layer 106 and the protective layer 107 are misaligned. As a result, a region that is not protected by the protective layer 107 is generated in a part of the semiconductor layer 106, and as a result, the device characteristics of the thin film transistor device 1 are degraded. Therefore, it is preferable that the distance D is as small as possible.

The distances D and E can be set independently by adjusting the position of the semiconductor layer 106 with respect to the channel region and the position of the protective layer 107 with respect to the semiconductor layer 106, respectively. For example, even if the distance E between the semiconductor layer 106 and the channel region is as large as 10 μm, the distance D can be reduced by forming the protective layer 107 in accordance with the position of the semiconductor layer 106. Deterioration of characteristics due to misalignment of the layer 107 can be suppressed. On the other hand, the distance E between the semiconductor layer 106 and the channel region is 10 μm, and the protective layer 107 is further −10 μm from the position of the channel region (in the direction opposite to the position of the semiconductor layer 106 with respect to the channel region). 10 μm), the value of the distance D becomes 20 μm, which is not preferable. It should be noted that the most preferable state is that both the distance D and the distance E are 0.

In reality, the required positional accuracy may change in various ways depending on the device accuracy, patterning accuracy, required film thickness, degree of external influence, etc. However, in general, such a positional accuracy relationship cannot be maintained. If so, the effect of the present invention can be obtained.

Although the bottom contact/bottom gate type thin film transistor element 1 has been described as an example, the form of the thin film transistor element is not limited to this, and the effect can be obtained even with a top contact or top gate type thin film transistor element. can be used if

A material used for the insulating substrate 101 is not particularly limited, but a glass substrate, a silicon wafer, or the like can be easily used. If it is desired to form a flexible transistor, it is necessary to use a flexible substrate. In that case, plastic materials such as polyethylene terephthalate (PET), polyimide, polyethersulfone (PES), polyethylene naphthalate (PEN), and polycarbonate are generally used. Since strength and heat resistance differ depending on the material, it is good to select a material suitable for each manufacturing process.

Materials used for electrode materials such as the gate electrode 103, the source electrode 104, the drain electrode 105, and the extraction electrode are not particularly limited. Examples include conductive polymers. The method of forming each electrode is not particularly limited, and dry processes such as vapor deposition and sputtering, and wet processes such as coating and printing can be used in consideration of the influence on other layers.

The material used for the gate insulating film 102 is not particularly limited, and can be freely selected as long as the material functions sufficiently as the gate insulating film 102 . In general, polyvinylphenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, epoxy resin, etc., PET, PEN, PES, etc. may be used.

The material used for the semiconductor layer 106 is not particularly limited, and generally used organic semiconductor materials include polymeric materials such as polyiophenes, polyallylamines, fluorene bithiophene copolymers, and derivatives thereof, pentacene, , tetracene, copper phthalocyanine, penylene, and derivatives thereof.

The material used for the protective layer 107 is not particularly limited, but since it is most important not to damage the semiconductor layer 106, a fluororesin or the like is generally likely to be used. Polyvinylphenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, epoxy resin, and the like may be used as long as they do not damage the semiconductor layer 106 .

The material used for the interlayer insulating film layer 108 is not particularly limited, but generally used materials include organic materials such as polyvinylphenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, and epoxy resin. For layer formation, known methods such as letterpress printing, reverse offset printing, inkjet printing, screen printing, spray coating and spin coating can be suitably used.

Examples are described below. In addition, in the present invention, it is preferable to have a carrier mobility of 0.1 cm ² /Vs or more as a guide, which is sufficiently applicable to electronic devices such as electronic paper.

(Example 1)
A thin film transistor array according to Example 1 was manufactured by the following procedure. In the manufactured thin film transistor array, the thin film transistor elements 1 are arranged in a matrix of 100 columns and 100 rows, and are arranged at equal intervals of 500 μm in length and width in a region of 5 cm in length and 5 cm in width.

First, silver ink was printed on a glass substrate 101 and dried on a hot plate at 180° C. for 1 hour to form a gate electrode 103 and a capacitor electrode with a film thickness of 100 nm.

Next, polyvinylphenol was applied by spin coating and dried on a hot plate at 180° C. for 1 hour to form a gate insulating film 102 .

Next, silver ink was printed on the gate insulating film 102 and dried on a hot plate at 180° C. for 1 hour to form a source electrode 104 and a drain electrode 105 with a film thickness of 100 nm to define a channel region. The defined channel regions are shown in FIG. The channel width (the width of the entire channel region in the major axis direction of FIG. 8) is 300 μm, the channel length (the distance between the source electrode 104 and the drain electrode 105 in the minor axis direction of FIG. 8) is 10 μm, and the channel region width (the width of the channel region The middle distance M) was designed to be 70 μm.

Next, a semiconductor ink prepared by mixing TIPS pentacene as a semiconductor material with tetralin to a concentration of 1.0% by weight was used, and printing was performed by flexographic printing to form a semiconductor layer 106 . The printing machine shown in FIG. 10 was used for flexographic printing. As the relief plate, 100 stripe-shaped photosensitive resin protrusions having a width of 50 μm and a length of 5.2 cm were formed at intervals of 500 μm. In the thin film transistor array, 100 thin film transistor elements 1 were straddled by one stripe pattern semiconductor layer, and printing was performed so that 100 rows of semiconductor layers were arranged. After printing, baking was performed in an oven at 150° C. for 1 hour under an environment of 5 hPa or less.

The cross-sectional shape of the semiconductor layer 106 after baking was a mountain-like shape in which the film thickness gradually decreased from the center toward the end. The film thickness was 45 nm at the central thickest portion. The distance C of the semiconductor layer 106 in the minor axis direction of the stripe was 85 μm. In addition, the distance E in the short axis direction between the center line of the stripe in the short axis direction of the semiconductor layer 106 and the center line of the width of the channel region was 5 μm or less.

Next, a protective layer 107 was formed by flexographic printing using a fluorine-containing resin, which is a fluorine-containing compound. The printing machine shown in FIG. 10 was used for flexographic printing. As a relief plate, a relief plate having photosensitive resin protrusions formed in stripes was used, and the protective layer 107 was printed so as to cover the entire surface of the semiconductor layer 106 . At the time of printing, nitrogen gas was always blown to the place where the photosensitive resin protrusion and the substrate were in contact to promote drying of the protective material ink. After printing, it was baked on a hot plate at 150° C. for 1 hour.

The cross-sectional shape of the protective layer 107 after firing is a concave shape having portions where the film thickness gradually increases from the center to the ends in the minor axis direction (having the thickest portions on both sides of the center in the minor axis direction). was in shape. The film thickness was 150 nm at the thinnest portion in the center and 220 nm at the thickest portion near both ends. The distance B between both ends of the protective layer 107 in the short axis direction of the stripe was 115 μm, and the distance A between the thickest portions (thickest portions) was 100 nm. Further, the distance D between the centers of the semiconductor layer 106 and the protective layer 107 in the minor axis direction was 5 μm or less.

Next, an inter-layer insulating film 108 having a thickness of 1 μm was formed by spin coating and photolithography using a paste of an epoxy resin material.

The upper pixel electrode was then formed by screen printing a silver paste.

(Comparative example 1)
A thin film transistor array was fabricated in the same manner as in Example 1, except that nitrogen gas was not sprayed during printing of the protective layer 107 .

<Evaluation>
In Example 1 and Comparative Example 1, the shape of the protective layer 107 was measured before forming the interlayer insulating film. The cross-sectional shape of the protective layer 107 in Example 1 in the minor axis direction of the stripe is a concave cross-sectional shape in which the film thickness increases from the center toward the ends. The thickness of the film was 220 nm at the thickest part near the edge, and the distance of the film in the minor axis direction of the stripe was 115 μm. The cross-sectional shape of the protective layer 107 in Comparative Example 1 was a mountain-like shape in which the film thickness decreases from the center toward both ends in the minor axis direction, and the film thickness was 200 nm at the thickest portion near the center. The distance B between both ends in the minor axis direction of the stripe was 95 μm.

After storing the prepared thin film transistor array in a high ozone concentration environment for 1 hour, the transistor characteristics of 10,000 thin film transistor elements 1 in the array were measured. The average value of the mobility of the measured devices was 0.17 cm ^{2 /Vs for the thin film transistor array of Example 1 and 0.07 cm 2 /} Vs for the thin film transistor array of Comparative Example 1.

From the above results, it was confirmed that the thin film transistor array according to the example was less susceptible to external influences and had high uniformity in transistor characteristics.

INDUSTRIAL APPLICABILITY The present invention is useful for thin film transistor arrays, electrophoretic displays, liquid crystal displays and the like using the same.

1 thin film transistor element 101 insulating substrate 102 gate insulating film (layer)
103 Gate electrode 104 Source electrode 105 Drain electrode 106 Semiconductor (layer)
107 protection (layer)
108 Interlayer insulating film (layer)
109 Film thickness required for protective layer for protection from external environment 201 Substrate to be printed 202 Ink 203 Flexographic plate 204 Semi-dry ink 205 Printed matter 301 Substrate surface plate 302 Substrate to be printed 303 Ink chamber 304 Doctor 305 Ink 306 Anilox roll 307 plate cylinder 308 letterpress 309 printed matter 310 raised portion 401 centerline of channel region 402 centerline of semiconductor layer

Claims (8)

At least an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, a semiconductor layer formed in a channel region between the source electrode and the drain electrode, and a semiconductor layer formed on the semiconductor layer. A thin film transistor array in which thin film transistor elements including a protective layer are arranged in a matrix on a substrate,
The protective layer is formed in a stripe shape so as to cover the channel region across the plurality of thin film transistor elements, and a cross section of the protective layer cut along a plane perpendicular to the long axis direction of the stripe shape corresponds to the short axis of the stripe shape. A shape having a thicker film thickness than the center on both sides of the center in the direction,
A thin-film transistor array in which the semiconductor layer has a shape in which a cross section of the semiconductor layer cut along a plane orthogonal to the long axis direction of the stripe shape has a shape in which the film thickness gradually decreases from the center toward both ends in the short axis direction. . Distance A in the minor axis direction between the thickest locations in the cross section of the protective layer where the film thickness is thicker than the center, and distance B between both ends of the protective layer in the minor axis direction relationship is
BA≦20 μm
2. The thin film transistor array of claim 1, wherein: The relationship between the distance B between both ends of the protective layer in the minor axis direction and the distance C between both ends of the semiconductor layer in the minor axis direction is
C<B
3. The thin film transistor array according to claim 1 or 2, wherein Distance A in the short axis direction between the thickest portions of each region thicker than the center in the cross section of the protective layer, and distance C between both ends of the semiconductor layer in the short axis direction relationship is
|AC|≦10 μm
4. The thin film transistor array according to any one of claims 1 to 3, wherein 5. The thin film transistor array according to claim 1, wherein a distance D between centers of said protective layer and said semiconductor layer in the minor axis direction is 10 [mu]m or less. The relationship between the distance M between both ends of the channel region in the short axis direction and the distance C between both ends of the semiconductor layer in the short axis direction is
0≦MC≦40 μm
6. The thin film transistor array according to any one of claims 1 to 5, wherein 7. The distance E in the minor axis direction between the thickest portion of the semiconductor layer cross section and the center of the channel region in the minor axis direction is 10 μm or less according to claim 1. Thin film transistor array. 8. The method of manufacturing a thin film transistor array according to any one of claims 1 to 7, comprising the step of forming the protective layer by letterpress printing.

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