JPWO2019203200A1 - Thin film transistor array, thin film transistor array multi-imposition substrate, and their manufacturing method - Google Patents

Abstract

Provided are a thin film transistor array capable of obtaining stable characteristics with a high degree of freedom in wiring design, a thin film transistor array multi-imposition substrate using the thin film transistor array, and a method for manufacturing these at low cost. The thin film transistor array is a thin film transistor element including at least an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor layer formed in a channel region between the source electrode and the drain electrode. The semiconductor layer includes a pixel pattern region arranged in a matrix and a plurality of extraction electrodes electrically connected to source electrodes of a plurality of thin film transistor elements linearly arranged in the pixel pattern region. It is formed by a part of a plurality of stripe patterns formed in a stripe shape parallel to the direction in which the plurality of thin film transistor elements arranged in a shape are arranged, and the stripe pattern and the extraction electrode are formed in different layers.

Description

The present invention relates to a thin film transistor array, a thin film transistor array multi-imposition substrate, and a method for manufacturing the same.

In recent years, research and development of printed electronics for producing functional elements by a printing method using functional materials inked regardless of whether they are organic or inorganic have been actively carried out.

Regarding printed electronics, organic functional elements such as organic EL (electroluminescence) elements, organic solar cells, and organic thin film transistors are being actively developed. In these organic functional elements, it is generally necessary to form an organic functional layer having a film thickness of about several nm to several μm on a substrate.

There are various printing methods used in the field of printed electronics, but typical ones are inkjet in addition to the methods used for a long time such as letterpress printing, intaglio printing, stencil printing, and stencil printing. There is a relatively new method typified by printing, and a wide variety of methods are selected depending on the ink and base material used. Letterpress printing, intaglio printing, lithographic printing, stencil printing, etc. are called plate printing because they produce and use plates for the target printing pattern. On the other hand, inkjet printing or the like is called plateless printing because the ink is directly transferred to a desired position and a plate is not used regardless of the pattern.

Further, each printing method is further subdivided according to the members used and the like. For example, in the letterpress printing method, a printing method using a printing plate called a flexographic plate made of resin, rubber, or the like is sometimes called flexographic printing to distinguish it from others.

In addition, there are relatively simple film forming methods such as a spin coating method, a bar coating method, a discharge coating method, and a dip coating method. However, these are generally good at forming a uniform film on the entire surface or almost the entire surface of the substrate, and on the other hand, they are suitable for high-precision patterning and material coating, which are often required for functional devices. Not suitable.

In this way, there are various types of printing methods, and each has its own advantages and disadvantages. Therefore, in printed electronics, a more suitable printing method is selected based on the target structure, material, functionality, and the like. It is necessary.

The advantages of the letterpress printing method, especially the flexographic printing method, in printed electronics are that continuous printing is stable, ink selectivity is wide, printing of relatively low-viscosity ink is possible, and flexibility. It is difficult to damage the base material, etc. because a new plate is used.

The application of the letterpress printing method to the field of printed electronics will be described by taking an organic semiconductor using an organic semiconductor ink, which has been attracting attention in recent years, as an example. For example, among the letterpress printing methods, a technique for forming an organic semiconductor layer using flexographic printing (see Patent Document 1) has already been developed.

An example of the letterpress printing apparatus will be described with reference to FIG. In the letterpress printing apparatus shown in FIG. 7, a rotary plate cylinder 107 on which a printing letterpress 108 is mounted, an anilox roll 106 for supplying ink 105 to the plate surface of the letterpress 108, and an ink 105 on the anilox roll 106 are applied. It has an ink chamber 103 to be supplied, a doctor 104 for scraping off excess ink on the anilox roll, and a substrate platen 101 on which the substrate 102 to be printed is placed. As the doctor 104, a blade made of a metal plate, a resin plate, or the like, a roll formed of resin, rubber, or the like on the outer periphery is often used.

In flexographic printing, when an independent pattern such as dots is formed, the printed matter is strongly affected by the flow and drying of the ink on the plate, so that the film thickness and shape tend to vary. Therefore, a technique for forming an organic semiconductor layer over a plurality of channels into a striped shape (see Patent Document 2) has been studied.

Even in printing using a striped plate (striped printing), it is difficult to completely avoid the influence of drying, and the ink state varies within the plate pattern area. In particular, drying tends to proceed in the vicinity of the edge of the plate pattern region, and printing shape defects are likely to occur. Therefore, a dummy area for printing a dummy plate pattern (dummy pattern) is formed outside the originally required pattern area (pixel pattern area), and only the portion where the ink state is relatively stable is used for printing the pixel pattern area. A method is used (Patent Document 4).

Japanese Unexamined Patent Publication No. 2006-633334 Japanese Unexamined Patent Publication No. 2008-235861 Japanese Unexamined Patent Publication No. 2005-21086 Japanese Unexamined Patent Publication No. 2013-21146

However, when the dummy pattern as described above is used, as shown in FIG. 8, a large area printing area 204 including the dummy area 202 provided on the outer edge of the minimum necessary pixel pattern area 201 is required. Further, it is necessary to design the dummy area 202 so as not to adversely affect the originally required pixel pattern area 201.

For example, in the thin film transistor array 400 in which a plurality of thin film transistor elements 302 are arranged on a substrate 304 as shown in FIG. 9, a plurality of thin film transistor elements 302 arranged in a linear shape are arranged in order to drive each of the thin film transistor elements 302. A take-out electrode 303 drawn from the gate electrode or the source electrode is required. The drawn-out electrode 303 may be aggregated in a predetermined region in order to facilitate wiring with the outside of the thin film transistor array 400. In such a case, at least a part of the extraction electrode 303 may be routed obliquely with respect to the arrangement direction of the thin film transistor element 302.

When the take-out electrode 303 is obliquely routed in the dummy region 202 as in the thin film transistor array 401 shown in FIG. 10, a stripe pattern 203 in which the semiconductor material is formed in a stripe shape is formed over the take-out electrode 303. If the material has conductivity (wiring-semiconductor contact region 403), a leak occurs between the extraction electrodes 303, which causes a problem. Therefore, in order to prevent leakage between the extraction electrodes 303, the extraction electrodes 303 may be formed parallel to the stripe pattern 203 to the outside of the dummy region 202 as in the thin film transistor array 402 shown in FIG. 11 (wiring-semiconductor contact buffer). Region 404).

However, in order to keep the size of the entire thin film transistor array small, it is desirable to make the dummy region 202, which is not functionally necessary, as narrow as possible. In particular, when printing a multi-imposition substrate in which a plurality of thin film transistor arrays are simultaneously formed on one substrate 501 as shown in FIGS. 12 and 13, there are cases where there is no dummy region 202 (FIG. 12) (FIG. 12). The imposition efficiency changes in FIG. 13), which reduces productivity and is disadvantageous in terms of cost.
In FIG. 13, it is shown as a print area 204 including a dummy area 202.

Such a phenomenon is not limited to stripe printing by flexographic printing, and a pattern is formed outside the pixel pattern area 201, for example, when patterning is performed on the pixel pattern area 201 as in one-stroke writing using nozzle printing. If it is, it will occur in the same way.

The present invention has been made in view of such a problem, and a thin film transistor array capable of obtaining stable transistor characteristics with a high degree of freedom in wiring design, a thin film transistor array multi-imposition substrate using the same, and these. It is intended to provide a method for manufacturing a transistor at a low cost.

One aspect of the invention for solving the above problems is formed in at least a channel region between an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a source electrode and a drain electrode. Includes a pixel pattern region in which the thin film transistor elements including the semiconductor layer are arranged in a matrix, and a plurality of extraction electrodes electrically connected to the source electrodes of the plurality of thin film transistor elements linearly arranged in the pixel pattern region. , The semiconductor layer is formed by a part of a plurality of stripe patterns formed in a stripe shape parallel to the direction in which a plurality of thin film transistor elements in which semiconductor materials are linearly arranged are arranged, and a part of the plurality of stripe patterns is at least one. The portion is formed in a dummy region outside the pixel pattern region, and the stripe pattern and the extraction electrode are formed in different layers, which is a thin film transistor array.

Further, at least one of the plurality of stripe patterns may intersect with at least one of the plurality of extraction electrodes in a plan view.

Further, the take-out electrode may be formed on an insulating substrate.

Further, at least an interlayer insulating film layer may be formed on the semiconductor layer, and the extraction electrode may be formed on the interlayer insulating film layer.

Further, the dummy region may be a region having a width of 1 mm or more from the outer edge of the pixel pattern region.

Further, another aspect of the present invention is a thin film transistor array multi-imposition substrate in which a plurality of the above-mentioned thin film transistor arrays are impositioned on the same substrate, and a stripe pattern is formed over at least two or more thin film transistor arrays. Thin film transistor array Multi-imposition substrate.

Another aspect of the present invention is a pixel pattern region in which thin film transistor elements including at least a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor layer are arranged in a matrix on an insulating substrate. A step of forming a plurality of extraction electrodes electrically connected to source electrodes of a plurality of thin film transistor elements linearly arranged in a pixel pattern region on a layer different from the semiconductor layer. In the step of forming the pattern region, the semiconductor layer is formed by a part of a plurality of stripe patterns formed in a stripe shape parallel to the direction in which the plurality of thin film transistor elements linearly arranged in the pixel pattern region are arranged. , A method for manufacturing a thin film transistor array.

Further, in the step of forming the pixel pattern region, a plurality of stripe patterns may be formed by printing.

Another aspect of the present invention is a method for manufacturing a thin-film transistor array multi-imposition substrate in which a plurality of thin-film transistor arrays are impositions on the same substrate by using the above-mentioned thin-film transistor array manufacturing method, and the number of semiconductor layers is at least two. This is a method for manufacturing a thin film transistor array multi-imposition substrate, which is formed in a striped shape over the above thin film transistor arrays.

According to the present invention, a thin film transistor array capable of obtaining stable transistor characteristics with a high degree of freedom in wiring design, a thin film transistor array multi-imposition substrate using the thin film transistor array, and a method for manufacturing these at low cost are provided. be able to.

FIG. 1 is a cross-sectional view of a thin film transistor element according to an embodiment of the present invention. FIG. 2 is a plan view of the thin film transistor array according to the embodiment of the present invention. FIG. 3 is a plan view of the thin film transistor array according to the embodiment of the present invention. FIG. 4 is a partial cross-sectional view of the thin film transistor array according to the embodiment of the present invention. FIG. 5 is a partial cross-sectional view of a thin film transistor array according to a modified example of the present invention. FIG. 6 is a plan view of the thin film transistor array multi-imposition substrate according to the embodiment of the present invention. FIG. 7 is a diagram showing a configuration example of a general letterpress printing apparatus. FIG. 8 is a diagram showing a striped semiconductor layer formed by using letterpress printing. FIG. 9 is a plan view showing a thin film transistor array according to the prior art. FIG. 10 is a plan view showing a thin film transistor array according to the prior art. FIG. 11 is a plan view showing a thin film transistor array according to the prior art. FIG. 12 is a plan view showing a thin film transistor array multi-imposition substrate according to the prior art. FIG. 13 is a plan view showing a thin film transistor array multi-imposition substrate according to the prior art.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, the same or corresponding components are designated by the same reference numerals, and duplicate description between the embodiments will be omitted.

FIG. 1 shows a cross-sectional view of a bottom contact-bottom gate type thin film transistor element 302 used in the thin film transistor array 301 according to the embodiment of the present invention.

In the thin film transistor element 302, a gate electrode 603 and a capacitor electrode (omitted in the drawing) are formed on an insulating substrate 601, and a gate insulating film 602 is laminated on the gate electrode 603 and a capacitor electrode (omitted in the drawing). A source electrode 604 and a drain electrode 605 are formed on the gate insulating film 602. The thin film transistor element 302 is formed on the gate insulating film 602 by overlapping with the gate electrode 603 in a plan view and forming a semiconductor layer 606 in a channel region sandwiched between the source electrode 604 and the drain electrode 605. If necessary, the thin film transistor element 302 may be appropriately formed with a protective material layer 607, an interlayer insulating film 608, an upper pixel electrode, and the like on the semiconductor layer 606 (partially omitted in the drawings).

2 and 3 show a plan view of the thin film transistor array 301 according to the embodiment of the invention, and FIG. 4 shows a partial cross-sectional view between A and A'of FIG. In FIG. 2, the interlayer insulating film 608 and the take-out electrode 303, which will be described later, are transmitted and shown.

As shown in FIGS. 2 and 3, the thin film transistor array 301 includes a pixel pattern region 201 formed by arranging a plurality of thin film transistor elements 302 in a matrix, and a plurality of extraction electrodes 303. The plurality of extraction electrodes 303 are electrically connected to the source electrodes 604 of the plurality of thin film transistor elements 302 that are linearly arranged with the source electrodes 604 electrically connected to each other.

Further, the thin film transistor array 301 includes a plurality of stripe patterns 203 in which the semiconductor material is formed in a stripe shape parallel to the direction in which the plurality of thin film transistor elements 302 in which the source electrodes 604 are electrically connected to each other are arranged. The semiconductor layer 606 is formed by forming the stripe pattern 203 on the channel region of the thin film transistor element 302. As shown in FIG. 4, the stripe pattern 203 and the take-out electrode 303 are formed in different layers.
In addition, in FIGS. 4 and 5, the description of the gate electrode 603 and the drain electrode 605 is omitted.

As shown in FIG. 2, a dummy region 202 is provided in a region having a predetermined width from the outer edge of the pixel pattern region 201, in which the stripe pattern 203 is formed but the thin film transistor element 302 is not formed. Specifically, as shown in FIG. 2, at least a part of the plurality of stripe patterns 203 is formed so that both ends in the length direction are located in the dummy area 202, and the remaining part is entirely formed in the dummy area 202. It is formed to be located in. By providing the dummy region 202, it is possible to suppress the influence of the printing defect near the end portion of the print region 204 on the semiconductor layer 606 when the stripe pattern 203 is formed by printing. Therefore, by providing the dummy region 202, the thin film transistor array 301 having stable transistor characteristics can be obtained. The width of the pixel pattern region 201 of the dummy region 202 from the outer edge is preferably 1 mm or more in order to sufficiently obtain the effect of the dummy region. On the other hand, even if it is 50 mm or more, the effect of the dummy region does not change, but rather the imposition position is strongly restricted in the multi-imposition substrate, so 50 mm or less is the appropriate range.

As shown in FIGS. 2 to 4, at the end of the pixel pattern region 201, a plurality of electrically connected source electrodes 604 are formed on the interlayer insulating film 608 via the source electrode-take-out electrode connection portion 702. It is connected to the take-out electrode 303.

The take-out electrode 303 is formed so as to be integrated in a predetermined region after extending from the source electrode-take-out electrode connection portion 702 in order to facilitate the connection between the thin film transistor array 301 and an external device such as an operation jig. Will be done. As shown in FIG. 4, in the thin film transistor array 301, the source electrode-take-out electrode connection portion 702 is provided in the via hole formed in the interlayer insulating film 608 as an example.

In the thin film transistor array 301, as shown in FIG. 3, at least a part of the plurality of stripe patterns 203 intersects with at least a part of the plurality of extraction electrodes 303 in a plan view, but the stripe pattern 203 Since the take-out electrode 303 is formed in a separate layer, leakage between the take-out electrodes 303 as described above does not occur. The forming layer of the extraction electrode 303 does not have to be on the interlayer insulating film 608, and any layer as long as it is formed on a layer different from the stripe pattern 203, for example, on the insulating substrate 601 as shown in FIG. Is also good. In this case, the source electrode-take-out electrode connection portion 702 is provided in the via hole formed in the gate insulating film 602.

No matter how the dummy region 202 is designed, the thin film transistor array 301 can suppress leakage between the extraction electrodes 303 (that is, the degree of freedom in wiring design is high), so that the printing pattern of the dummy region 202 is optimized. be able to. For example, when manufacturing a multi-imposition substrate in which a plurality of thin film transistor arrays 301 are impositioned on the same substrate as shown in FIG. 6, the thin film transistor array 301 can be manufactured without providing a dummy region 202 between the plurality of thin film transistor arrays 301. In the thin film transistor array multi-imposition substrate thus formed, the stripe pattern 203 can be formed over at least two or more thin film transistor arrays 301 by printing so as to connect the ends of the adjacent thin film transistor arrays 301. Therefore, it is possible to suppress the occurrence of drying at the edge of the print area 204, which is a problem due to printing, only at the edge of the entire substrate. As a result, the thin film transistor array 301 having stable transistor characteristics can be manufactured. Further, since it is not necessary to design the dummy region 202 for each thin film transistor array 301, more impositions can be performed efficiently. As a result, the thin film transistor array 301 can be manufactured at low cost.

In the above, the thin film transistor array 301 using the bottom contact-bottom gate type thin film transistor element 302 has been described as an example, but the form of the thin film transistor element used is not limited to this, and a top cotton tact or a top gate type thin film transistor is used. Even an element can be used as long as the effect can be obtained.

The material used for the insulating substrate 601 is not particularly limited, but a glass substrate, a silicon wafer, or the like can be easily used. When it is desired to form a flexible transistor, it is necessary to use a flexible substrate. In that case, in general, plastic materials such as polyethylene terephthalate (PET), polyimide, polyether sulfone (PES), polyethylene naphthalate (PEN), and polycarbonate are likely to be used. Since the strength and heat resistance differ depending on the material, it is advisable to select a material suitable for each manufacturing process.

The materials used for the electrode materials such as the gate electrode 603, the source electrode 604, the drain electrode 605, and the take-out electrode 303 are not particularly limited, but are generally metals and oxides such as gold, platinum, silver, and nickel. There are films, conductive polymers, etc. The method for forming each electrode is not particularly limited, and a dry process such as vapor deposition or sputtering, a wet process such as coating, or printing can be used in consideration of the influence on other layers.

The material used for the gate insulating film 602 is not particularly limited, and can be freely selected as long as it functions sufficiently as the gate insulating film 602. In general, polyvinylphenol, polymethylmethacrylate, polyimide, polyvinyl alcohol, epoxy resin and the like, PET, PEN, PES and the like may be used.

The material used for the semiconductor layer 606 is not particularly limited, and as a material generally used as an organic semiconductor material, a polymer-based material such as polyiophen, polyallylamine, fluorevithiophene copolymer, and derivatives thereof, Low molecular weight materials such as pentacene, tetracene, copper phthalocyanine, penylene, and derivatives thereof can be used.

The material used for the protective material layer 607 is not particularly limited, but since it is most important not to damage the semiconductor layer 606, a fluororesin or the like is generally easily used. Polyvinylphenol, polymethylmethacrylate, polyimide, polyvinyl alcohol, epoxy resin, or the like may be used as long as it does not damage the semiconductor layer 606. In forming the protective material layer 607, known methods such as a letterpress printing method, an inverted offset printing method, a screen printing method, a spray coating method, and a spin coating method can be preferably used.

The material used for the interlayer insulating film layer 608 is not particularly limited, but generally used materials include organic materials such as polyvinylphenol, polymethylmethacrylate, polyimide, polyvinyl alcohol, and epoxy resin. For layer formation, known methods such as letterpress printing method, reverse offset printing method, screen printing method, spray coating method, and spin coating method can be preferably used.

The material used for the source electrode-take-out electrode connection portion 702 can be the same material as the electrodes such as the gate electrode 603, the source electrode 604, the drain electrode 605, and the take-out electrode 303, but is not particularly limited. .. Further, the method of forming the source electrode-take-out electrode connection portion 702 is not particularly limited as long as an electrical connection between the source electrode 604 and the take-out electrode 303 can be sufficiently obtained, and the influence on other layers is taken into consideration. Dry processes such as vapor deposition and sputtering, and wet processes such as coating and printing can be used.

As described above, according to the present invention, in the thin film transistor array 301, the extraction electrode 303 electrically connected to the source electrodes 604 of the plurality of thin film transistor elements 302 is formed in a layer different from the stripe pattern 203. Thereby, the stripe pattern 203 can be formed without intersecting with the plurality of extraction electrodes 303. Therefore, the degree of freedom in wiring design of the take-out electrode 303 is increased. Further, a sufficient dummy region 202 can be secured without increasing the size of the thin film transistor array 301, and stable transistor characteristics can be obtained. Further, when the thin film transistor array 301 is manufactured on the multi-imposition substrate, the dummy region 202 can be reduced to the minimum necessary, so that the thin film transistor array 301 can be manufactured at low cost as a more multi-imposition design. it can.

(Example 1)
The thin film transistor array 301 according to Example 1 was manufactured by the following procedure. In the manufactured thin film transistor array 301, 50 thin film transistor elements and 200 thin film transistor elements 302 are arranged in a region of 2.5 cm in length and 10 cm in width at equal intervals of 500 μm in length and width. The dummy region 202 is a strip-shaped region having a width of 1.0 mm from the outer edge of the pixel pattern region 201.

First, a 0.7 mm thick non-alkali glass was used as an insulating substrate 601 and silver ink was printed by an inkjet method, and then fired on a hot plate at 180 ° C. for 1 hour to obtain a gate electrode 603 having a film thickness of 100 nm and a gate electrode 603. A capacitor electrode was formed.

Next, a photosensitive acrylic resin is applied by a spin coating method, mask exposure and development with an alkaline developer are performed to form a pattern (photolithography method), and firing is performed at 180 ° C. for 1 hour to insulate a gate having a film thickness of 1 μm. A film 602 was formed. A via hole was formed at the source electrode-take-out electrode connection portion 702 provided in the gate insulating film 602.

Next, silver ink is printed on the gate insulating film 602 by an inkjet method and fired on a hot plate at 180 ° C. for 1 hour to form a source electrode 604 and a drain electrode 605 having a film thickness of 100 nm to form a channel region. Defined.

Next, as the semiconductor material, using a semiconductor ink prepared by adjusting TIPS pentacene with tetralin to 1.0% by weight, printing was performed by flexographic printing to form a stripe pattern 203 made of the semiconductor material. The printing machine used for flexographic printing was the one shown in FIG. 7. As the letterpress, a photosensitive resin convex portion having a striped shape having a width of 50 μm and a length of 10.2 cm, in which 54 pieces were formed side by side at intervals of 500 μm was used. In the thin film transistor array 301, printing was performed so that 200 rows of stripe patterns 203 capable of straddling a maximum of 50 thin film transistor elements 302 were arranged. After printing, it was dried in an oven at 150 ° C. for 1 hour under reduced pressure (about 1 hPa).

Next, a protective material layer 607 was formed by flexographic printing using a fluorine-based resin which is a fluorine-containing compound. The printing machine used for flexographic printing was the one shown in FIG. 7. As the letterpress, a striped plate having a photosensitive resin convex portion formed therein was used, and printing was performed so that the protective material layer 607 covered the entire surface of the stripe pattern 203. After printing, it was dried on a hot plate at 150 ° C. for 1 hour.

Next, the photosensitive acrylic resin was applied by a spin coating method and patterned by a photolithography method in the same manner as the gate insulating film 602 to form an interlayer insulating film 608.

Next, silver ink was printed on the interlayer insulating film 608 by an inkjet method, and dried on a hot plate at 150 ° C. for 1 hour to form a take-out electrode 303 having a film thickness of 100 nm.

Next, the silver paste was printed by a screen printing method to form a source electrode-take-out electrode connection portion 702 and an upper pixel electrode.

An electrophoresis-type electronic paper display device using the thin film transistor array 301 manufactured by the above procedure as a driving element was manufactured.

(Example 2)
At the same time as the formation of the gate electrode 603, the take-out electrode 303 was formed on the insulating substrate 601 to form a gate insulating film and via holes in the same manner as in Example 1. Further, after forming the source electrode 604 and the drain electrode 605, the thin film transistor array according to the second embodiment is manufactured by the same method as in the first embodiment except that the silver paste is screen-printed to form the source electrode-take-out electrode connection portion 702. did. In addition, an electrophoresis-type electronic paper display device using this was manufactured.

(Comparative Example 1)
The same as in Example 1 except that the take-out electrode 303 was formed by stretching the source electrode 604 on the gate insulating film 602 to form the thin film transistor array 401. That is, in Comparative Example 1, the stripe pattern 203 and the take-out electrode were formed in the same layer. In addition, an electrophoresis-type electronic paper display device using this was manufactured.

(Comparative Example 2)
This was carried out except that the photosensitive resin convex portions were striped with a width of 50 μm and a length of 10 cm and 50 strips were formed side by side at intervals of 500 μm, that is, the stripe pattern 203 was not formed in the dummy region 202. It was the same as in Example 1. In addition, an electrophoresis-type electronic paper display device using this was manufactured.

<Evaluation>
With respect to the electronic paper display devices produced by the thin film transistor arrays 301 and 401 according to Examples 1 and 2 and Comparative Examples 1 and 2 thus produced, white and black squares are alternately displayed in a 1 mm square size to display white. Black and black were rewritten multiple times so that they became white, and the results were compared.

There was no particular problem in the display of Examples 1 and 2, and good images were obtained. In Comparative Example 1, some pixels showing poor contrast in black-and-white rewriting were observed. In Comparative Example 2, a defect was found at the end of the display unit.

In Comparative Example 1, it is considered that the on / off ratio is deteriorated due to leakage in a plurality of pixels. Further, in Comparative Example 2, a printing defect of the semiconductor layer was observed in the thin film transistor element corresponding to the end portion of the display unit.

From the above results, it was confirmed that a thin film transistor array having stable transistor characteristics can be obtained by the structure of the thin film transistor array 301 according to the present invention.

The present invention is useful when it is desired to manufacture a thin film transistor array having a high degree of freedom in wiring design and capable of obtaining stable transistor characteristics at low cost.

101 Substrate platen 102 Printed substrate 103 Ink chamber 104 Doctor 105 Ink 106 Anilox roll 107 Plate cylinder 108 Convex plate 109 Printed matter 110 Convex part 201 Pixel pattern area 202 Dummy area 203 Stripe pattern 204 Printing area 301 Thin film transistor array 302 Thin film transistor element 303 Extraction electrode 304 Thin film transistor array 400 to 402 Conventional technology Thin film transistor array 403 Wiring-semiconductor contact area 404 Wiring-semiconductor contact buffering area 501 Thin film transistor array Multi-imposition board 601 Insulating board 602 Gate insulating film (layer)
603 Gate electrode 604 Source electrode 605 Drain electrode 606 Semiconductor (layer)
607 Protective material (layer)
608 Interlayer insulating film (layer)
701 Thin film transistor array 702 Source electrode-takeout electrode connection

Claims (9)

A matrix of thin film transistor elements including at least an insulating substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor layer formed in a channel region between the source electrode and the drain electrode. The pixel pattern area arranged in a shape and
A plurality of extraction electrodes electrically connected to the source electrodes of the plurality of thin film transistor elements linearly arranged in the pixel pattern region are included.
The semiconductor layer is formed by a part of a plurality of stripe patterns formed in a stripe shape parallel to the direction in which the plurality of thin film transistor elements in which the semiconductor materials are linearly arranged are arranged.
A part of the plurality of stripe patterns is formed in a dummy area outside the pixel pattern area, at least in part.
The stripe pattern and the take-out electrode are formed in different layers.
Thin film transistor array. At least one of the plurality of stripe patterns intersects with at least one of the plurality of extraction electrodes in a plan view.
The thin film transistor array according to claim 1. The take-out electrode is formed on the insulating substrate.
The thin film transistor array according to claim 1 or 2. At least an interlayer insulating film layer is formed on the semiconductor layer,
The take-out electrode is formed on the interlayer insulating film layer.
The thin film transistor array according to claim 1 or 2. The dummy region is a region having a width of 1 mm or more from the outer edge of the pixel pattern region.
The thin film transistor array according to any one of claims 1 to 4. A thin film transistor array multi-imposition substrate in which a plurality of thin film transistor arrays according to any one of claims 1 to 5 are impositioned on the same substrate.
The stripe pattern is formed over at least two or more thin film transistor arrays.
Thin film transistor array multi-imposition substrate. A step of forming a pixel pattern region in which thin film transistor elements including at least a gate electrode, a gate insulating film, a source electrode, a drain electrode, and a semiconductor layer are arranged in a matrix on an insulating substrate.
A step of forming a plurality of extraction electrodes electrically connected to the source electrodes of the plurality of thin film transistor elements linearly arranged in the pixel pattern region on a layer different from the semiconductor layer is included.
In the step of forming the pixel pattern region, the semiconductor layer is one of a plurality of stripe patterns in which the semiconductor material is formed in a stripe shape parallel to the direction in which the plurality of thin film transistor elements linearly arranged in the pixel pattern region are arranged. Formed by the part,
A method for manufacturing a thin film transistor array. In the step of forming the pixel pattern region, the plurality of stripe patterns are formed by printing.
The method for manufacturing a thin film transistor array according to claim 7. A method for manufacturing a thin film transistor array multi-imposition substrate, wherein a plurality of thin film transistor arrays are impositioned on the same substrate by using the method for manufacturing the thin film transistor array according to any one of claims 7 or 8.
The semiconductor layer is formed in a striped shape over at least two or more of the thin film transistor arrays.
A method for manufacturing a thin-film transistor array multi-imposition substrate.

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