JP7152543B2 - Semiconductor package structure - Google Patents
Semiconductor package structure Download PDFInfo
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- JP7152543B2 JP7152543B2 JP2021026628A JP2021026628A JP7152543B2 JP 7152543 B2 JP7152543 B2 JP 7152543B2 JP 2021026628 A JP2021026628 A JP 2021026628A JP 2021026628 A JP2021026628 A JP 2021026628A JP 7152543 B2 JP7152543 B2 JP 7152543B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
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- General Physics & Mathematics (AREA)
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- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Description
本発明は、巻き取り可能であり、放熱シートを貼り付けている可撓性の半導体パッケージ構造に関するものである。 The present invention relates to a flexible semiconductor package structure that can be rolled up and attached with a heat dissipation sheet.
薄膜フリップチップパッケージ(COF)は薄膜トランジスタ液晶ディスプレイ(Thin film transistor liquid crystal display、TFT LCD)のドライバICのパッケージ方式の1つであり、高解像度及び高性能が求められる。この種の薄膜フリップチップパッケージは、高熱が発生することによりドライバICが損壊することがあった。 A thin film flip-chip package (COF) is one of package methods for a driver IC of a thin film transistor liquid crystal display (TFT LCD), and requires high resolution and high performance. This type of thin film flip chip package may damage the driver IC due to high heat generation.
薄膜フリップチップパッケージ構造として、例えば、特許文献1に記載されたものが知られている。第一放熱部材の接着層によりチップ及び薄膜基板に貼り付け、チップに対する放熱を行っている。特許文献1には接着層の端部が基材、熱伝導層、第一金属層、及び第二金属層の端部に平たく揃えていると記載されているため、薄膜フリップチップパッケージ構造が押圧された場合、外力(例えば、巻き取る際の圧力等)により基材、熱伝導層、第一金属層、及び第二金属層の端部に接着層が溢れ出すか突出し、薄膜フリップチップパッケージ構造が汚染された。また、薄膜フリップチップパッケージ構造が巻き取られた場合、基材、熱伝導層、第一金属層、及び第二金属層の端部に溢れ出すか突出する接着層により薄膜フリップチップパッケージ構造が相互に接着してしまい、薄膜フリップチップパッケージ構造の品質及び歩留まりに影響を与えた。 As a thin film flip chip package structure, for example, the one described in Patent Document 1 is known. The adhesive layer of the first heat dissipation member is attached to the chip and the thin film substrate to dissipate heat to the chip. Patent Document 1 describes that the edges of the adhesive layer are flush with the edges of the base material, the thermally conductive layer, the first metal layer, and the second metal layer, so that the thin film flip chip package structure is pressed. When the adhesive layer overflows or protrudes at the edges of the base material, the thermally conductive layer, the first metal layer, and the second metal layer due to external force (such as pressure during winding), the thin film flip chip package structure is formed. was contaminated. In addition, when the thin film flip chip package structure is rolled up, the adhesive layer that overflows or protrudes at the edges of the substrate, the thermally conductive layer, the first metal layer, and the second metal layer keeps the thin film flip chip package structure together. , thus affecting the quality and yield of the thin film flip chip package structure.
本発明は、上述に鑑みてなされたものであり、その目的は、チップに貼り付けた放熱シートの接着層が放熱シートに溢れ出すか突出し汚染される事象を回避する半導体パッケージ構造を提供することにある。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor package structure that avoids the phenomenon that the adhesive layer of a heat dissipation sheet attached to a chip overflows or protrudes into the heat dissipation sheet and is contaminated. It is in.
本発明の半導体パッケージ構造は、回路層を有している可撓性基板と、前記可撓性基板に設置し、前記回路層に電気的に接続し、露出面を露出しているチップと、前記チップの前記露出面に設置し、キャリアと、放熱層と、接着層とを含み、前記放熱層は前記キャリアと前記接着層との間に位置し、前記接着層は第一接着面により前記チップの前記露出面に貼り付け、前記放熱層と前記チップとの間に前記接着層を包囲している空間を形成している放熱シートと、を備え、前記接着層は前記チップの前記露出面に投影し、前記露出面に第一投影領域を形成し、前記チップの前記露出面は第一端部を有し、前記放熱層の表面は第二端部を有し、前記第一投影領域は第三端部を有し、前記第一端部、前記第二端部、及び前記第三端部により前記空間を定義し、前記キャリアは前記チップの前記露出面に投影し、前記露出面に第三投影領域を形成し、前記第三投影領域は第五端部を有し、前記第五端部は前記露出面の前記第一端部と前記第一投影領域の前記第三端部との間に位置している。
A semiconductor package structure of the present invention comprises: a flexible substrate having a circuit layer; a chip mounted on the flexible substrate, electrically connected to the circuit layer, and having an exposed surface exposed; A carrier, a heat dissipation layer and an adhesive layer are disposed on the exposed surface of the chip, wherein the heat dissipation layer is positioned between the carrier and the adhesive layer, and the adhesive layer is disposed on the exposed surface of the chip by a first adhesive surface. a heat dissipation sheet attached to the exposed surface of the chip and forming a space surrounding the adhesive layer between the heat dissipation layer and the chip, wherein the adhesive layer is attached to the exposed surface of the chip. to form a first projection area on the exposed surface, the exposed surface of the chip having a first edge, the surface of the heat dissipation layer having a second edge, the first projection area has a third end and defines the space with the first end, the second end and the third end, the carrier projecting onto the exposed surface of the chip and the exposed surface forming a third projection area in the third projection area, the third projection area having a fifth end, the fifth end being the first end of the exposed surface and the third end of the first projection area is located between
本発明は、接着層が押圧された場合、絞り出された接着層を空間に収容することで接着層が放熱シートに溢れ出す或いは突出する事象を回避する。また、複数の可撓性の半導体パッケージ構造を巻き取る際に、これら可撓性の半導体パッケージ構造が相互に接着する事象も回避する。 According to the present invention, when the adhesive layer is pressed, the squeezed-out adhesive layer is accommodated in the space, thereby avoiding the phenomenon that the adhesive layer overflows or protrudes into the heat dissipation sheet. It also avoids the phenomenon of the flexible semiconductor packaging structures sticking together when winding the flexible semiconductor packaging structures.
以下、本発明による実施形態を図面に基づいて説明する。 BEST MODE FOR CARRYING OUT THE INVENTION An embodiment according to the present invention will be described below with reference to the drawings.
(第一実施形態)
本発明の第一実施形態について図1から図2に基づいて説明する。
(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.
本発明に係る半導体パッケージ構造100(例えば、薄膜フリップチップパッケージ、COF等)は、可撓性基板110と、チップ120と、放熱シート130と、を備えている。可撓性基板110は回路層111及び保護層112を有している。
図1及び図2に示すように、本実施形態では、回路層111は可撓性基板110の表面に設置し、保護層112は回路層111を被覆し、保護層112は回路層111の複数のインナーリード111aを露出している。
A semiconductor package structure 100 (eg, thin film flip chip package, COF, etc.) according to the present invention comprises a
As shown in FIGS. 1 and 2 , in this embodiment, the
図1及び図2に示すように、チップ120は可撓性基板110に設置し、チップ120は複数のバンプ121により回路層111のこれらインナーリード111aに電気的に接続し、チップ120は露出面120aを露出している。
本実施形態では、可撓性基板110とチップ120との間にアンダーフィル140を充填し、アンダーフィル140はこれらバンプ121を被覆している。
As shown in FIGS. 1 and 2, the
In this embodiment, an
放熱シート130はチップ120の露出面120aに設置し、放熱シート130はキャリア131と、放熱層132と、接着層133と、を備えている。放熱層132はキャリア131と接着層133との間に位置し、接着層133は第一接着面133a及び第二接着面133bを有している。接着層133は第一接着面133aによりチップ120の露出面120aに貼り付け、接着層133は第二接着面133bにより放熱層132の表面132aに貼り付け、放熱層132とチップ120との間に接着層133を包囲する空間Rを形成している。
A
接着層133はチップ120の露出面120aに投影し、露出面120aに第一投影領域A1を形成している。接着層133は放熱層132の表面132aに投影し、表面132aに第二投影領域A2を形成している。キャリア131はチップ120の露出面120aに投影し、露出面120aに第三投影領域A3を形成している。
The
また、第一投影領域A1は露出面120a中に位置し、第一投影領域A1の領域面積は露出面120aの表面積未満である。第二投影領域A2は表面132a中に位置し、第二投影領域A2の領域面積は表面132aの表面積未満である。
本実施形態では、チップ120の露出面120aは第一端部120bを有し、放熱層132の表面132aは第二端部132bを有し、第一投影領域A1は第三端部A11を有し、第二投影領域A2は第四端部A21を有し、第三投影領域A3は第五端部A31を有している。第五端部A31は露出面120aの第一端部120bと第一投影領域A1の第三端部A11との間に位置し、第五端部A31と露出面120aの第一端部120bとが重畳している。
Also, the first projection area A1 is located in the exposed
In this embodiment, the exposed
図1及び図2に示すように、本実施形態では、第一端部120bと第三端部A11との間に20μm以上である間隔を有し、第二端部132bと第四端部A21との間に20μm以上である間隔を有し、第一端部120b、第二端部132b、及び第三端部A11により空間Rを定義している。
本実施形態では、第一端部120b、第二端部132b、第三端部A11、及び第四端部A21により空間Rを定義している。空間Rは保留空間であり、接着層133が押圧された場合、保留された空間Rに押圧された接着層133を収容することにより、接着層133が放熱シート130に溢れ出す或いは突出する事象を回避し、半導体パッケージ構造100が汚染されないようにしている。また、複数の半導体パッケージ構造100を巻き取る際に、これら半導体パッケージ構造100が相互に接着する事象も回避している。
As shown in FIGS. 1 and 2, in this embodiment, there is a gap of 20 μm or more between the
In this embodiment, the space R is defined by the
(その他の実施形態)
その他の実施形態では、第一端部、第二端部、及び第三端部ではなく、第二端部、第三端部、及び第四端部により空間Rを定義している。
(Other embodiments)
In other embodiments, the space R is defined by the second, third and fourth ends rather than the first, second and third ends.
その実施形態の他の基本的構成は、第一実施形態と同様である。 Other basic configurations of this embodiment are the same as those of the first embodiment.
以上、本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々の形態で実施可能である。 As described above, the present invention is not limited to the above-described embodiments, and can be implemented in various forms without departing from the gist of the present invention.
100 半導体パッケージ構造、
110 可撓性基板、
111 回路層、
111a インナーリード、
112 保護層、
120 チップ、
120a 露出面、
120b 第一端部、
121 バンプ、
130 放熱シート、
131 キャリア、
132 放熱層、
132a 表面、
132b 第二端部、
133 接着層、
133a 第一接着面、
133b 第二接着面、
140 アンダーフィル、
A1 第一投影領域、
A11 第三端部、
A2 第二投影領域、
A21 第四端部、
A3 第三投影領域、
A31 第五端部、
R 空間。
100 semiconductor package structure,
110 flexible substrate;
111 circuit layer,
111a inner lead,
112 protective layer,
120 chips,
120a exposed surface,
120b first end,
121 Bump,
130 heat dissipation sheet,
131 Carrier,
132 heat dissipation layer,
132a surface,
132b second end,
133 adhesive layer,
133a first adhesive surface,
133b second adhesive surface,
140 underfill,
A1 first projection area,
A11 third end,
A2 second projection area,
A21 fourth end,
A3 third projection area,
A31 fifth end,
R space.
Claims (6)
前記可撓性基板に設置し、前記回路層に電気的に接続し、露出面を露出しているチップと、
前記チップの前記露出面に設置し、キャリアと、放熱層と、接着層とを含み、前記放熱層は前記キャリアと前記接着層との間に位置し、前記接着層は第一接着面により前記チップの前記露出面に貼り付け、前記放熱層と前記チップとの間に前記接着層を包囲している空間を形成している放熱シートと、を備え、
前記接着層は前記チップの前記露出面に投影し、前記露出面に第一投影領域を形成し、
前記チップの前記露出面は第一端部を有し、前記放熱層の表面は第二端部を有し、前記第一投影領域は第三端部を有し、前記第一端部、前記第二端部、及び前記第三端部により前記空間を定義し、
前記キャリアは前記チップの前記露出面に投影し、前記露出面に第三投影領域を形成し、前記第三投影領域は第五端部を有し、前記第五端部は前記露出面の前記第一端部と前記第一投影領域の前記第三端部との間に位置していることを特徴とする半導体パッケージ構造。 a flexible substrate having a circuit layer;
a chip mounted on the flexible substrate and electrically connected to the circuit layer with an exposed surface exposed;
A carrier, a heat dissipation layer and an adhesive layer are disposed on the exposed surface of the chip, wherein the heat dissipation layer is positioned between the carrier and the adhesive layer, and the adhesive layer is disposed on the exposed surface of the chip by a first adhesive surface. a heat dissipation sheet attached to the exposed surface of the chip and forming a space surrounding the adhesive layer between the heat dissipation layer and the chip ;
the adhesive layer projects onto the exposed surface of the chip to form a first projected area on the exposed surface;
The exposed surface of the chip has a first end, the surface of the heat dissipation layer has a second end, the first projected area has a third end, the first end, the defining the space by a second end and the third end;
The carrier projects onto the exposed surface of the chip and forms a third projected area on the exposed surface, the third projected area having a fifth end, the fifth end being the exposed surface of the exposed surface. A semiconductor package structure located between a first end and the third end of the first projection area .
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TW109145666 | 2020-12-23 | ||
TW109145666A TWI738596B (en) | 2020-12-23 | 2020-12-23 | Flexible semiconductor package |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001007262A (en) | 1999-06-17 | 2001-01-12 | Nec Corp | Semiconductor device and manufacture thereof |
JP2001244362A (en) | 2000-02-28 | 2001-09-07 | Nec Corp | Semiconductor device |
US20050168952A1 (en) | 2004-02-04 | 2005-08-04 | Siliconware Precision Industries Co., Ltd. | Semiconductor package |
US20070262444A1 (en) | 2006-05-10 | 2007-11-15 | Siliconware Precision Industries Co., Ltd. | Semiconductor device and chip structure thereof |
US20100019379A1 (en) | 2008-07-24 | 2010-01-28 | Broadcom Corporation | External heat sink for bare-die flip chip packages |
CN114520197A (en) | 2020-11-19 | 2022-05-20 | 颀邦科技股份有限公司 | Flexible semiconductor package structure |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW258829B (en) * | 1994-01-28 | 1995-10-01 | Ibm | |
KR100760770B1 (en) * | 2006-03-29 | 2007-09-21 | 삼성에스디아이 주식회사 | Plasma display device |
US20090091021A1 (en) * | 2007-10-03 | 2009-04-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2012164846A (en) * | 2011-02-08 | 2012-08-30 | Renesas Electronics Corp | Semiconductor device, semiconductor device manufacturing method and display device |
US10770368B2 (en) * | 2015-12-02 | 2020-09-08 | Novatek Microelectronics Corp. | Chip on film package and heat-dissipation structure for a chip package |
TWM610924U (en) * | 2020-12-23 | 2021-04-21 | 頎邦科技股份有限公司 | Flexible semiconductor package |
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2020
- 2020-12-23 TW TW109145666A patent/TWI738596B/en active
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- 2021-02-22 JP JP2021026628A patent/JP7152543B2/en active Active
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001007262A (en) | 1999-06-17 | 2001-01-12 | Nec Corp | Semiconductor device and manufacture thereof |
JP2001244362A (en) | 2000-02-28 | 2001-09-07 | Nec Corp | Semiconductor device |
US20050168952A1 (en) | 2004-02-04 | 2005-08-04 | Siliconware Precision Industries Co., Ltd. | Semiconductor package |
US20070262444A1 (en) | 2006-05-10 | 2007-11-15 | Siliconware Precision Industries Co., Ltd. | Semiconductor device and chip structure thereof |
US20100019379A1 (en) | 2008-07-24 | 2010-01-28 | Broadcom Corporation | External heat sink for bare-die flip chip packages |
CN114520197A (en) | 2020-11-19 | 2022-05-20 | 颀邦科技股份有限公司 | Flexible semiconductor package structure |
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JP2022100191A (en) | 2022-07-05 |
KR20220091317A (en) | 2022-06-30 |
TW202226474A (en) | 2022-07-01 |
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