TWI738596B - Flexible semiconductor package - Google Patents

Flexible semiconductor package Download PDF

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Publication number
TWI738596B
TWI738596B TW109145666A TW109145666A TWI738596B TW I738596 B TWI738596 B TW I738596B TW 109145666 A TW109145666 A TW 109145666A TW 109145666 A TW109145666 A TW 109145666A TW I738596 B TWI738596 B TW I738596B
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Taiwan
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edge
projection area
chip
heat dissipation
layer
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TW109145666A
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Chinese (zh)
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TW202226474A (en
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李東昇
龐規浩
魏兆璟
郭晉村
李佩螢
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頎邦科技股份有限公司
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Priority to TW109145666A priority Critical patent/TWI738596B/en
Priority to CN202120060945.8U priority patent/CN214254395U/en
Priority to CN202110031745.4A priority patent/CN114520197A/en
Priority to CN202120299508.1U priority patent/CN215008198U/en
Priority to CN202110144595.8A priority patent/CN114520201A/en
Priority to JP2021026628A priority patent/JP7152543B2/en
Priority to KR1020210023227A priority patent/KR20220091317A/en
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Publication of TWI738596B publication Critical patent/TWI738596B/en
Publication of TW202226474A publication Critical patent/TW202226474A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A flexible semiconductor package includes a flexible substrate, a chip and a thermal pad. The chip is mounted on the flexible substrate. The thermal pad is attached on an exposed surface of the chip by an adhesive, and a space exists between the thermal pad and the chip and surrounds the adhesive. The space is provided to accommodate the adhesive so as to prevent the adhesive from overflowing or being squeezed out from the thermal pad when being compressed.

Description

撓性半導體封裝構造Flexible semiconductor package structure

本發明關於一種撓性半導體封裝構造，尤其是一種可撓、可捲收，且貼附有一散熱貼片的撓性半導體封裝構造。 The present invention relates to a flexible semiconductor packaging structure, in particular to a flexible semiconductor packaging structure that is flexible and rollable and attached with a heat dissipation patch.

薄膜覆晶封裝(COF)為目前薄膜電晶體液晶顯示器(Thin film transistor liquid crystal display，TFT LCD)的一驅動積體電路(IC)的封裝方式之一，在高解析度及高性能的需求下，會使得薄膜覆晶封裝產生高熱，而高熱將使該驅動積體電路(IC)損壞。 Chip-on-film packaging (COF) is currently one of the packaging methods of a driving integrated circuit (IC) of thin film transistor liquid crystal display (TFT LCD), under the requirements of high resolution and high performance , Will make the thin film flip chip package generate high heat, and high heat will damage the drive integrated circuit (IC).

台灣申請第109209860號專利揭露一種「薄膜覆晶封裝結構」，其以一第一散熱件13的一黏著層貼附於晶片12及薄膜基板11上，以對晶片12進行散熱，請參閱台灣申請第109209860號專利的圖1C，其揭露該黏著層的邊緣與基材131、導熱層133、第一金屬層134、第二金屬層136的邊緣平齊，因此，當該薄膜覆晶封裝結構被擠壓時，該黏著層將會因外力(如捲收時的壓力等)而溢流或凸出於該基材131、該導熱層133、該第一金屬層134、該第二金屬層136的邊緣，而污染該薄膜覆晶封裝結構，且當該薄膜覆晶封裝結構被捲收時，溢流或凸出於該基材131、該導熱層133、該第一金屬層134、該第二金屬層136的各該邊緣的該黏著層，會造成薄膜覆晶封裝結構互相黏著，其影響了該薄膜覆晶封裝結構的品質 及良率。 Taiwan Application No. 109209860 discloses a "thin film-on-chip package structure" in which an adhesive layer of a first heat sink 13 is attached to the chip 12 and the film substrate 11 to dissipate the heat of the chip 12. Please refer to the Taiwan application FIG. 1C of Patent No. 109209860 discloses that the edge of the adhesive layer is flush with the edges of the substrate 131, the thermal conductive layer 133, the first metal layer 134, and the second metal layer 136. Therefore, when the film-on-chip package structure is When squeezed, the adhesive layer will overflow or protrude from the substrate 131, the thermally conductive layer 133, the first metal layer 134, and the second metal layer 136 due to external forces (such as pressure during rolling). The edge of the film-on-chip package structure is contaminated, and when the film-on-chip package structure is rolled up, it overflows or protrudes from the substrate 131, the thermally conductive layer 133, the first metal layer 134, and the second The adhesion layer on each edge of the two metal layers 136 will cause the film-on-chip package structure to adhere to each other, which affects the quality of the film-on-chip package structure And yield.

本發明的主要目的是避免貼附於一晶片的一散熱貼片的一黏著層溢流或凸出於該散熱貼片，而造成一撓性半導體封裝構造受污染。 The main purpose of the present invention is to prevent an adhesive layer of a heat dissipation patch attached to a chip from overflowing or protruding from the heat dissipation patch, thereby causing a flexible semiconductor package structure to be contaminated.

本發明之一種撓性半導體封裝構造包含一撓性基板、一晶片及一散熱貼片，該撓性基板具有一電路層，該晶片設置於該撓性基板，且該晶片與該電路層電性連接，該晶片並顯露出一顯露表面，該散熱貼片設置於該晶片的該顯露表面，該散熱貼片包含一載體、一散熱層及一黏著層，該散熱層位於該載體與該黏著層之間，該黏著層以一第一黏著面貼附於該晶片的該顯露表面，使該散熱層及該晶片之間形成一容膠空間，該容膠空間並環繞該黏著層。 A flexible semiconductor package structure of the present invention includes a flexible substrate, a chip and a heat dissipation patch. The flexible substrate has a circuit layer, the chip is disposed on the flexible substrate, and the chip and the circuit layer are electrically connected. Connected, the chip is exposed to an exposed surface, the heat dissipation patch is disposed on the exposed surface of the chip, the heat dissipation patch includes a carrier, a heat dissipation layer, and an adhesive layer, and the heat dissipation layer is located between the carrier and the adhesive layer In between, the adhesive layer is attached to the exposed surface of the chip with a first adhesive surface, so that a glue-tolerant space is formed between the heat dissipation layer and the chip, and the glue-tolerant space surrounds the adhesive layer.

本發明藉由該容膠空間，使得該黏著層受壓時，能容納被壓力擠出的該黏著層，以避免該黏著層溢流出或凸出於該散熱貼片，並可避免捲收複數個撓性半導體封裝構造時，造成該些撓性半導體封裝構造互相黏著。 The present invention uses the glue-containing space so that when the adhesive layer is pressed, the adhesive layer can be squeezed out by the pressure, so as to prevent the adhesive layer from overflowing or protruding from the heat dissipation patch, and avoiding multiple windings. When there are two flexible semiconductor packaging structures, the flexible semiconductor packaging structures are caused to adhere to each other.

請參閱第1及2圖，本發明的一種撓性半導體封裝構造100(如薄膜覆晶封裝，COF等)包含一撓性基板110、一晶片120及一散熱貼片130，該撓性基板110具有一電路層111及一保護層112，在本實施例中，該電路層111設置於該撓性基板110的一表面，且該保護層112覆蓋該電路層111，該保護層112並顯露出該電路層111的複數個內引腳111a。Please refer to FIGS. 1 and 2. A flexible semiconductor package structure 100 (such as a chip-on-film package, COF, etc.) of the present invention includes a flexible substrate 110, a chip 120, and a heat sink 130. The flexible substrate 110 It has a circuit layer 111 and a protective layer 112. In this embodiment, the circuit layer 111 is disposed on a surface of the flexible substrate 110, and the protective layer 112 covers the circuit layer 111, and the protective layer 112 is exposed A plurality of inner leads 111a of the circuit layer 111.

請參閱第1及2圖，該晶片120設置於該撓性基板110，且該晶片120以複數個凸塊121與該電路層111的該些內引腳111a電性連接，該晶片120並顯露出一顯露表面120a，在本實施例中，一填充膠140填充於該撓性基板110與該晶片120之間，且該填充膠140包覆該些凸塊121。Please refer to FIGS. 1 and 2. The chip 120 is disposed on the flexible substrate 110, and the chip 120 is electrically connected to the inner pins 111a of the circuit layer 111 by a plurality of bumps 121, and the chip 120 is exposed An exposed surface 120a is exposed. In this embodiment, a filler 140 is filled between the flexible substrate 110 and the chip 120, and the filler 140 covers the bumps 121.

請參閱第1及2圖，該散熱貼片130設置於該晶片120的該顯露表面120a，該散熱貼片130包含一載體131、一散熱層132及一黏著層133，該散熱層132位於該載體131與該黏著層133之間，該黏著層133具有一第一黏著面133a及一第二黏著面133b，該黏著層133以該第一黏著面133a貼附於該晶片120的該顯露表面120a，該黏著層133以該第二黏著面133b貼附於該散熱層132的一表面132a，並使該散熱層132及該晶片120之間形成一容膠空間R，該容膠空間R並環繞該黏著層133。Please refer to Figures 1 and 2. The heat dissipation patch 130 is disposed on the exposed surface 120a of the chip 120. The heat dissipation patch 130 includes a carrier 131, a heat dissipation layer 132 and an adhesive layer 133. The heat dissipation layer 132 is located on the exposed surface 120a of the chip 120. Between the carrier 131 and the adhesive layer 133, the adhesive layer 133 has a first adhesive surface 133a and a second adhesive surface 133b, and the adhesive layer 133 is attached to the exposed surface of the chip 120 by the first adhesive surface 133a 120a, the adhesive layer 133 is attached to a surface 132a of the heat dissipation layer 132 with the second adhesive surface 133b, and a glue containing space R is formed between the heat dissipation layer 132 and the chip 120, and the glue containing space R is parallel to Surround the adhesive layer 133.

請參閱第1及2圖，該黏著層133投影至該顯露表面120a，並於該晶片120的該顯露表面120a形成一第一投影區域A1，該黏著層133投影至該散熱層132的該表面132a，並於該表面132a形成一第二投影區域A2，該載體131投影至該晶片120的該顯露表面120a，並於該顯露表面120a形成一第三投影區域A3。Referring to FIGS. 1 and 2, the adhesive layer 133 is projected onto the exposed surface 120a, and a first projection area A1 is formed on the exposed surface 120a of the chip 120, and the adhesive layer 133 is projected onto the surface of the heat dissipation layer 132 132a, a second projection area A2 is formed on the surface 132a, the carrier 131 is projected onto the exposed surface 120a of the wafer 120, and a third projection area A3 is formed on the exposed surface 120a.

請參閱第1及2圖，該第一投影區域A1位於該顯露表面120a中，且該第一投影區域A1的一區域面積小於該顯露表面120a的一表面積，該第二投影區域A2位於該表面132a中，且該第二投影區域A2的一區域面積小於該表面132a的一表面積，在本實施例中，該晶片120的該顯露表面120a具有一第一邊緣120b，該散熱層132的該表面132a具有一第二邊緣132b，該第一投影區域A1具有一第三邊緣A11，該第二投影區域A2具有一第四邊緣A21，該第三投影區域A3具有一第五邊緣A31，該第五邊緣A31位於該顯露表面120a的該第一邊緣120b與該第一投影區域A1的該第三邊緣A11之間，較佳地，該第五邊緣A31與該顯露表面120a的該第一邊緣120b重疊。Please refer to Figures 1 and 2, the first projection area A1 is located in the exposed surface 120a, and an area of the first projection area A1 is smaller than a surface area of the exposed surface 120a, and the second projection area A2 is located on the surface 132a, and an area of the second projection area A2 is smaller than a surface area of the surface 132a. In this embodiment, the exposed surface 120a of the wafer 120 has a first edge 120b, and the surface of the heat dissipation layer 132 132a has a second edge 132b, the first projection area A1 has a third edge A11, the second projection area A2 has a fourth edge A21, the third projection area A3 has a fifth edge A31, the fifth The edge A31 is located between the first edge 120b of the exposed surface 120a and the third edge A11 of the first projection area A1. Preferably, the fifth edge A31 overlaps with the first edge 120b of the exposed surface 120a .

請參閱第1及2圖，在本實施例中，該第一邊緣120b與該第三邊緣A11之間具有一間距，該間距不小於20微米，該第二邊緣132b與該第四邊緣A21之間具有一間距，該間距不小於20微米，且該第一邊緣120b、該第二邊緣132b、該第三邊緣A11定義出該容膠空間R，或者，在不同的實施例中，該第二邊緣132b、該第三邊緣A11、該第四邊緣A21定義出該容膠空間R，在本實施例中，是以該第一邊緣120b、該第二邊緣132b、該第三邊緣A11、該第四邊緣A21定義該容膠空間R，該容膠空間R為一預留空間，當該黏著層133受壓時，藉由預留的該容膠空間R容納受壓的該黏著層133，以避免該黏著層133溢流出或凸出於該散熱貼片130，而污染該撓性半導體封裝構造100，且可避免捲收複數個撓性半導體封裝構造100時，造成該些撓性半導體封裝構造100互相黏著。Please refer to Figures 1 and 2. In this embodiment, there is a distance between the first edge 120b and the third edge A11, and the distance is not less than 20 microns. The second edge 132b and the fourth edge A21 are There is a gap between them, the gap is not less than 20 microns, and the first edge 120b, the second edge 132b, and the third edge A11 define the glue-tolerant space R, or, in different embodiments, the second The edge 132b, the third edge A11, and the fourth edge A21 define the glue-tolerant space R. In this embodiment, the first edge 120b, the second edge 132b, the third edge A11, and the The four edges A21 define the glue containing space R. The glue containing space R is a reserved space. When the adhesive layer 133 is compressed, the glue containing space R is reserved to accommodate the compressed adhesive layer 133. It prevents the adhesive layer 133 from overflowing or protruding from the heat dissipation patch 130, thereby contaminating the flexible semiconductor packaging structure 100, and avoiding the flexible semiconductor packaging structures 100 when multiple flexible semiconductor packaging structures 100 are rolled up. 100 stuck to each other.

本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。The scope of protection of the present invention shall be determined by the scope of the attached patent application. Anyone who is familiar with the art and makes any changes and modifications without departing from the spirit and scope of the present invention shall fall within the scope of protection of the present invention. .

100:撓性半導體封裝構造 110:撓性基板 111:電路層 111a:內引腳 112:保護層 120:晶片 120a:顯露表面 120b:第一邊緣 121:凸塊 130:散熱貼片 131:載體 132:散熱層 132a:表面 132b:第二邊緣 133:黏著層 133a:第一黏著面 133b:第二黏著面 140:填充膠 A1:第一投影區域 A11:第三邊緣 A2:第二投影區域 A21:第四邊緣 A3:第三投影區域 A31:第五邊緣 R:容膠空間100: Flexible semiconductor package structure 110: Flexible substrate 111: circuit layer 111a: inner pin 112: protective layer 120: chip 120a: exposed surface 120b: first edge 121: bump 130: heat sink 131: Carrier 132: heat dissipation layer 132a: Surface 132b: second edge 133: Adhesive layer 133a: The first adhesive surface 133b: second adhesive surface 140: Filling glue A1: The first projection area A11: The third edge A2: The second projection area A21: Fourth edge A3: The third projection area A31: Fifth edge R: Glue capacity

第1圖：本發明的電路板的俯視圖。 Figure 1: A top view of the circuit board of the present invention.

第2圖：本發明的電路板的剖視圖。 Figure 2: A cross-sectional view of the circuit board of the present invention.

100:撓性半導體封裝構造 100: Flexible semiconductor package structure

110:撓性基板 110: Flexible substrate

111:電路層 111: circuit layer

111a:內引腳 111a: inner pin

112:保護層 112: protective layer

120:晶片 120: chip

120a:顯露表面 120a: exposed surface

120b:第一邊緣 120b: first edge

121:凸塊 121: bump

130:散熱貼片 130: heat sink

131:載體 131: Carrier

132:散熱層 132: heat dissipation layer

132a:表面 132a: Surface

132b:第二邊緣 132b: second edge

133:黏著層 133: Adhesive layer

133a:第一黏著面 133a: The first adhesive surface

133b:第二黏著面 133b: second adhesive surface

140:填充膠 140: Filling glue

A1:第一投影區域 A1: The first projection area

A11:第三邊緣 A11: The third edge

A2:第二投影區域 A2: The second projection area

A21:第四邊緣 A21: Fourth edge

A3:第三投影區域 A3: The third projection area

A31:第五邊緣 A31: Fifth edge

R:容膠空間 R: Glue capacity

Claims (9)

一種撓性半導體封裝構造，包含：一撓性基板，具有一電路層；一晶片，設置於該撓性基板，且該晶片與該電路層電性連接，該晶片並顯露出一顯露表面；以及一散熱貼片，設置於該晶片的該顯露表面，該散熱貼片包含一載體、一散熱層及一黏著層，該散熱層位於該載體與該黏著層之間，該黏著層以一第一黏著面貼附於該晶片的該顯露表面，使該散熱層及該晶片之間形成一容膠空間，該容膠空間並環繞該黏著層。 A flexible semiconductor packaging structure, comprising: a flexible substrate with a circuit layer; a chip arranged on the flexible substrate, and the chip is electrically connected to the circuit layer, the chip reveals an exposed surface; and A heat dissipation patch is disposed on the exposed surface of the chip. The heat dissipation patch includes a carrier, a heat dissipation layer, and an adhesive layer. The heat dissipation layer is located between the carrier and the adhesive layer. The adhesive layer has a first The adhesive surface is attached to the exposed surface of the chip, so that a glue containing space is formed between the heat dissipation layer and the chip, and the glue containing space surrounds the adhesive layer. 如請求項1之撓性半導體封裝構造，其中該黏著層投影至該顯露表面，並於該顯露表面形成一第一投影區域，該第一投影區域的一區域面積小於該顯露表面的一表面積，且該第一投影區域位於該顯露表面中，該黏著層以一第二黏著面貼附於該散熱層的一表面，該黏著層投影至該散熱層的該表面，並於該表面形成一第二投影區域，該第二投影區域的一區域面積小於該表面的一表面積，且該第二投影區域位於該表面中。 The flexible semiconductor package structure of claim 1, wherein the adhesive layer is projected onto the exposed surface, and a first projection area is formed on the exposed surface, and an area of the first projection area is smaller than a surface area of the exposed surface, And the first projection area is located in the exposed surface, the adhesive layer is attached to a surface of the heat dissipation layer with a second adhesive surface, the adhesive layer is projected onto the surface of the heat dissipation layer, and a first surface is formed on the surface Two projection areas, an area of the second projection area is smaller than a surface area of the surface, and the second projection area is located in the surface. 如請求項2之撓性半導體封裝構造，其中該晶片的該顯露表面具有一第一邊緣，該散熱層的該表面具有一第二邊緣，該第一投影區域具有一第三邊緣，該第一邊緣、該第二邊緣、該第三邊緣定義出該容膠空間。 According to the flexible semiconductor package structure of claim 2, wherein the exposed surface of the chip has a first edge, the surface of the heat dissipation layer has a second edge, the first projection area has a third edge, and the first The edge, the second edge, and the third edge define the glue-tolerant space. 如請求項2之撓性半導體封裝構造，其中該散熱層的該表面具有一第二邊緣，該第一投影區域具有一第三邊緣，該第二投影區域具有一第四邊緣，該第二邊緣、該第三邊緣、該第四邊緣定義出該容膠空間。 The flexible semiconductor package structure of claim 2, wherein the surface of the heat dissipation layer has a second edge, the first projection area has a third edge, the second projection area has a fourth edge, and the second edge , The third edge and the fourth edge define the glue-tolerant space. 如請求項2之撓性半導體封裝構造，其中該顯露表面具有一第一 邊緣，該散熱層的該表面具有一第二邊緣，該第一投影區域具有一第三邊緣，該第二投影區域具有一第四邊緣，該第一邊緣、該第二邊緣、該第三邊緣、該第四邊緣定義出該容膠空間。 The flexible semiconductor package structure of claim 2, wherein the exposed surface has a first Edge, the surface of the heat dissipation layer has a second edge, the first projection area has a third edge, the second projection area has a fourth edge, the first edge, the second edge, and the third edge , The fourth edge defines the glue holding space. 如請求項3之撓性半導體封裝構造，其中該第二投影區域具有一第四邊緣，該第二邊緣與該第四邊緣之間具有一間距，該間距不小於20微米。 According to claim 3, the flexible semiconductor package structure, wherein the second projection area has a fourth edge, and there is a distance between the second edge and the fourth edge, and the distance is not less than 20 microns. 如請求項3之撓性半導體封裝構造，其中該第一邊緣與該第三邊緣之間具有一間距，該間距不小於20微米。 According to the flexible semiconductor package structure of claim 3, there is a distance between the first edge and the third edge, and the distance is not less than 20 microns. 如請求項3至7中任一項之撓性半導體封裝構造，其中該載體投影至該顯露表面，並於該顯露表面形成一第三投影區域，該第三投影區域具有一第五邊緣，該第五邊緣位於該顯露表面的該第一邊緣與該第一投影區域的該第三邊緣之間。 The flexible semiconductor package structure of any one of claims 3 to 7, wherein the carrier is projected onto the exposed surface, and a third projection area is formed on the exposed surface, the third projection area has a fifth edge, the The fifth edge is located between the first edge of the exposed surface and the third edge of the first projection area. 如請求項8之撓性半導體封裝構造，其中該第五邊緣與該顯露表面的該第一邊緣重疊。 The flexible semiconductor package structure of claim 8, wherein the fifth edge overlaps the first edge of the exposed surface.
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