JP7138506B2 - Digital signal processing circuit - Google Patents

Description

The present invention relates to digital signal processing circuits.

When a signal coming from a signal source such as a switch or sensor is input to a control device such as a programmable logic controller (PLC), the signal is generally input to the control device via an input interface circuit.

However, when the control device is installed in a poor noise environment such as in a factory, the control device often malfunctions due to the noise.

In order to prevent the control device from malfunctioning due to noise, it is effective to remove the noise from the input voltage input to the control device using a filter. Filters include hardware filters, including capacitors, line filters, etc., and software filters.

However, when the noise is removed by the filter, the response speed of the control device to the input voltage also decreases. This decrease in response speed becomes a bottleneck in shortening the tact time of the control device.

In the technique described in Patent Document 1, a digital signal is input to the input port (paragraph 0016). An interrupt is detected from a change in the level of the digital signal input to the input port, an interrupt request is notified, and interrupt processing is started when the interrupt request is notified (paragraph 0016). In addition, the presence or absence of noise in the digital signal input to the input port is determined, and the data generated by the interrupt processing when the result of the determination of the presence or absence of noise performed from the start to the end of the interrupt processing is no noise. is output (paragraph 0017).

JP 2006-18331 A

As described above, in order to suppress malfunction of the control device due to noise, it is effective to remove noise from the input voltage input to the control device using a filter. However, when the noise is removed by the filter, the response speed of the control device to the input voltage also decreases.

Moreover, the technique described in Patent Document 1 has a problem that the type of signal is limited to an interrupt request.

The present invention has been made in view of these problems. The problems to be solved by the present invention are digital signal processing that can improve the response speed of a processor, can suppress malfunctions due to noise, and has few restrictions on the types of signals that can exhibit these effects. to provide the circuit.

The digital signal processing circuit includes a determination section, a first execution section, a holding section, a second execution section and a management section. The first execution unit, the holding unit and the second execution unit are built into the processor.

The determination unit determines whether the input voltage is a signal.

A task comprises a first part and a second part. The first part is before the hold point or before the hold point. The second part is after the hold point. The hold point is before the point at which malfunction occurs if the input voltage is erroneous.

The first execution unit starts executing the first part in conjunction with the input of the edge of the input voltage.

The holding unit holds the execution result of the first part when the first execution part finishes executing the first part.

The second execution unit takes over the execution result of the first part and starts execution of the second part after the determination part determines that the input voltage is a signal.

The management unit instructs the first execution unit to stop execution of the first part when the determination unit determines that the input voltage is not a signal and the input voltage satisfies the condition. and/or instructing the holding unit to reset the result of execution of the first part. The determination unit determines that the input voltage is the signal when the input voltage continues to be equal to or higher than a threshold value until a first period of time has elapsed since the edge of the input voltage was input. The condition is that the input voltage becomes lower than the threshold during a period from when the edge of the input voltage is input until a second time elapses, and the second time is equal to the first time. It is the same time as the time or a time longer than the first time.

In the present invention, task execution is started in conjunction with the input of an edge of the input voltage before it is determined whether or not the input voltage is a signal. Therefore, the response speed of the processor can be improved.

Also, in the present invention, if the input voltage is not determined to be a signal, execution of the second part of the task containing the point at which the malfunction occurs is not initiated and, if necessary, the first part of the task is aborted, or the result of the execution of the first part of the task is reset. Therefore, malfunction due to noise can be suppressed.

Moreover, in the present invention, restrictions on the types of signals that can exhibit these effects can be reduced.

Objects, features, aspects and advantages of the present invention will become more apparent with the following detailed description and accompanying drawings.

2 is a block diagram illustrating the digital signal processing circuit of Embodiment 1; FIG. 3 is a block diagram illustrating a digital signal processing circuit according to a second embodiment; FIG. FIG. 11 is a block diagram illustrating a digital signal processing circuit according to a third embodiment; FIG. FIG. 12 is a block diagram illustrating a digital signal processing circuit according to a fourth embodiment; FIG.

1 Embodiment 1
FIG. 1 is a block diagram illustrating a digital signal processing circuit of Embodiment 1. FIG.

A digital signal processing circuit 100a illustrated in FIG. The input voltage determination unit 110 is externally attached to the processor 112 . The input voltage determination unit 110 may be built into the processor 112 . The digital signal processing circuit 100a may have elements different from these elements.

The input voltage determination unit 110 operates as a determination unit that determines whether the input voltage 120 is a signal.

The input voltage determination unit 110 has ports 140 and 142 .

Input voltage 120 is input to port 140 . The input voltage 120 that is input may be a signal coming from a signal source such as a sensor attached to a production device, equipment, or the like, or may be noise coming from a noise source. A signal determination flag 122 is output from the port 142 .

Input voltage determination unit 110 detects that edge 124 of input voltage 120 is input to port 140 . The detected edge 124 may be either a rising edge or a falling edge.

The input voltage determination unit 110 determines that the input voltage 120 is a signal when the state in which the input voltage 120 is equal to or higher than the threshold continues until the first time elapses after the edge 124 of the input voltage 120 is input. do. Also, the input voltage determination unit 110 generates a signal determination flag 122 when determining that the input voltage 120 is a signal.

Either a hardware filter or a software filter is used to determine whether the state in which the input voltage 120 is equal to or greater than the threshold continues until the first time elapses after the edge 124 of the input voltage 120 is input. may be broken. A hardware filter is a circuit that includes elements such as capacitors and resistors and has a time constant. If the decision is made using a software filter, an integrated circuit is used. The integrated circuit used monitors the input voltage 120, measures the time that the input voltage 120 remains above the threshold after detecting the edge 124 of the input voltage 120, and the measured time is a first time. is reached, the signal determination flag 122 is generated.

The generated signal definite flag 122 is output from port 142 .

The first time may be a time that can be variably set by the user.

Processor 112 may be a central processing unit (CPU), processing unit, arithmetic unit, microprocessor, microcomputer, digital signal processor (DSP), system large scale integrated circuit (LSI), application specific integrated circuit (ASIC), or the like. processing circuit.

The processor 112 includes a task execution section 170 and a task management section 172 . A task execution unit 170 and a task management unit 172 are built into the processor 112 . A task manager 172 may be externally attached to the processor 112 .

Task execution unit 170 operates as an execution unit that executes task 180 . Task 180 to be performed comprises a first portion 190 and a second portion 192 . A first portion 190 is before hold point 200 . A second portion 192 is after hold point 200 . Hold point 200 is the final point of first portion 190 of task 180 . Thus, when the already executed portion of task 180 reaches holdpoint 200, execution of first portion 190 of task 180 ends.

The hold point 200 is before the point at which a malfunction occurs when the input voltage 120 is an erroneous input such as noise, preferably just before that point. The point is a point at which information is output to the outside of the task execution unit 170. For example, a point at which a signal output command is issued inside the task execution unit 170; It is a point etc. which issues an execution command. Hold point 200 may be a point that can be variably set by the user.

When a command is issued to the task execution unit 170, the task execution unit 170 executes the command.

Processor 112 includes ports 144 and 146 . Input voltage 120 is input to port 144 . The signal determination flag 122 is input to the port 146 . Processor 112 detects that edge 124 of input voltage 120 is input to port 144 and signal clear flag 122 is input to port 146 .

The processor 112 immediately issues a task execution command 126 to the task execution unit 170 when the edge 124 of the input voltage 120 is input. Processor 112 instructs task executor 170 to begin execution of first portion 190 of task 180 by issuing task execution instruction 126 to task executor 170 . Also, when the edge 124 of the input voltage 120 is input, the processor 112 immediately inputs the edge 124 of the input voltage 120 to the task management unit 172 .

The processor 112 issues a task processing continuation command 128 to the task execution unit 170 when the signal determination flag 122 is input. By issuing a task processing continuation command 128 to the task execution unit 170, the processor 112 executes the second portion 192 of the task 180 after completing the execution of the first portion 190 of the task 180, thereby executing the task 180. command the task execution unit 170 to continue the execution of Moreover, the processor 112 inputs the signal determination flag 122 to the task management unit 172 when the signal determination flag 122 is input.

The task execution unit 170 functions as a first execution unit, a holding unit and a second execution unit.

The first execution part starts executing the first part 190 of the task 180 as soon as the task execution command 126 is issued. This causes the first execution unit to start executing the first part 190 of the task 180 in conjunction with the input of the edge 124 of the input voltage 120 to the processor 112 .

The holding unit holds the result of the execution of the first part 190 of the task 180 when the execution of the first part 190 of the task 180 is completed.

If the task processing continuation command 128 has already been issued when the execution of the first portion 190 of the task 180 ends, the second execution unit takes over the execution result of the first portion 190 of the task 180. performs a second portion 192 of task 180 at . Further, the first execution unit stops execution of the task 180 at the hold point 200 if the task processing continuation command 128 has not yet been issued when the execution of the first part 190 of the task 180 is completed. Further, when the task processing continuation command 128 is issued after the execution of the first part 190 of the task 180 is completed, the second execution unit executes the task 180 from the time when the task processing continuation command 128 is issued. and execute a second portion 192 of task 180 taking over the results of the execution of the first portion 190 of task 180 . As a result, the second execution unit takes over the execution result of the first part 190 of the task 180 after the input voltage determination part 110 determines that the input voltage 120 is a signal, and executes the second part of the task 180. 192 begins execution.

A task may be divided into three or more parts, and a hold point may be provided between a first part and a second part included in the three or more parts. In this case, the first portion 190 of task 180 is before the hold point.

The task manager 172 has ports 148 , 150 , 152 and 154 . Edge 124 of input voltage 120 is input to port 148 . A signal determination flag 122 is input to the port 150 . A task processing stop command 130 is output from the port 152 . A reset command 132 is output from the port 154 . The task management unit 172 detects that the edge 124 of the input voltage 120 is input to the port 148 and that the signal determination flag 122 is input to the port 150 .

The task management unit 172 operates as a management unit that issues commands to the task execution unit 170 . Issuance of the command is performed based on the edge 124 of the input voltage 120 and the signal determination flag 122 . The type of command issued changes according to the execution state of the task 180 by the task execution unit 170 .

The task management unit 172 has a timer 210 .

The task management unit 172 causes the timer 210 to start measuring time when the edge 124 of the input voltage 120 is input.

The task management unit 172 resets the time measurement by the timer 210 when the input voltage 120 becomes lower than the threshold during the period from when the timer 210 starts measuring time until the second time elapses, A command is issued to the task execution unit 170 .

Further, task management unit 172 issues a command to task execution unit 170 when signal confirmation flag 122 is not input even though the second time has elapsed since timer 210 started measuring time. to be issued.

The command issued is a task abort command 130 if the first executor is executing the first part 190 of the task 180 and the first executor is executing the first part 190 of the task 180 is completed, it is a reset command 132 . The task management unit 172 instructs the first execution unit to stop executing the first part 190 of the task 180 by issuing a task processing stop command 130 to the first execution unit. The task manager 172 also issues a reset command 132 to the holder to instruct the holder to reset the execution result of the first part 190 of the task 180 .

The second time is the same time as the first time or longer than the first time. The second time is, for example, the first time plus the maximum delay time required for the signal determination flag 122 to be transmitted from the port 142 to the port 146 . The second time may be a time that can be variably set by the user within a range that does not cause inconsistency in operation.

The first execution unit suspends the execution of the first part 190 of the task 180 when the task processing stop command 130 is issued without the task processing continuation command 128 being issued. Further, the holding unit resets the execution result of the first part 190 of the task 180 when the reset command 132 is issued while the task processing continuation command 128 is not issued.

Based on these, the task management unit 172 determines whether or not the input voltage 120 satisfies the conditions described below. When it is determined that the conditions described below are satisfied, the first execution unit or the holding unit is instructed to do the following. The conditions to be satisfied are that the input voltage 120 falls below the threshold within the second time after the edge 124 of the input voltage 120 is applied, and that the edge 124 of the input voltage 120 is applied at least one of the conditions that the input voltage determination unit 110 has not determined that the input voltage 120 is a signal even though the second time has elapsed since . These conditions may be replaced by conditions different from these conditions. What is directed is at least one of aborting execution of the first portion 190 of task 180 and resetting the results of execution of the first portion 190 of task 180 . What is instructed is that if the first execution part is executing the first part 190 of the task 180, it is to stop executing the first part 190 of the task 180, and the first execution part is finished executing the first portion 190 of task 180, resetting the results of the execution of the first portion 190 of task 180;

The time from when the edge 124 of the input voltage 120 is input until the already executed part of the task 180 reaches the hold point 200 depends on the size of the control program, etc., and the signal input to the PLC passes through. The delay time may be about the same as the delay time of the noise filter mounted on the input interface circuit, or may be longer than the delay time. The delay time is approximately 1 μs to 70 ms. However, if the time is made approximately equal to the delay time, it becomes possible to incorporate the digital signal processing circuit 100a into a device relating to functional safety. However, the digital signal processing circuit 100a may be incorporated in a device different from the device related to functional safety.

In digital signal processing circuit 100a, execution of task 180 is started in conjunction with input of edge 124 of input voltage 120 before it is determined whether or not input voltage 120 is a signal. Therefore, the response speed of the processor 112 can be improved.

Further, in the digital signal processing circuit 100a, when the input voltage 120 is not determined to be a signal, execution of the second portion 192 of the task 180 including the point where the malfunction occurs does not start, and the first portion of the task 180 does not start. , or the results of the execution of the first portion 190 of task 180 are reset. Therefore, malfunction due to noise can be suppressed.

Moreover, in the digital signal processing circuit 100a, restrictions on the types of signals that can exhibit these effects can be reduced.

2 Embodiment 2
FIG. 2 is a block diagram illustrating a digital signal processing circuit of Embodiment 2. FIG.

The digital signal processing circuit 100b of the second embodiment shown in FIG. 2 differs from the digital signal processing circuit 100a of the first embodiment shown in FIG. 1 in the following points.

First, in the digital signal processing circuit 100a, the processor 112 issues a task processing continuation command 128 to the task execution unit 170 when the signal determination flag 122 is input. On the other hand, in the digital signal processing circuit 100b, the processor 112 inputs the signal determination flag 122 to the task management section 172 when the signal determination flag 122 is input. Also, the task execution unit 170 inputs the hold point arrival signal 134 to the task management unit 172 when the execution of the first part 190 of the task 180 is completed. Also, the task management unit 172 issues a task processing continuation command 128 to the task execution unit 170 when both the signal determination flag 122 and the hold point arrival signal 134 are input. As a result, the task management unit 172 performs the task 180 when the input voltage determination unit 110 determines that the input voltage 120 is a signal and the task execution unit 170 finishes executing the first part 190 of the task 180. It instructs the task execution unit 170 to start executing the second part 192 .

Second, in the digital signal processing circuit 100a, a task processing stop command 130 is issued to the task execution section 170. FIG. On the other hand, in the digital signal processing circuit 100 b , the task processing stop command 130 is not issued to the task execution section 170 .

The configuration of the digital signal processing circuit 100b related to the above differences will be described below. As for the configuration not described, the configuration adopted in the digital signal processing circuit 100a is also adopted in the digital signal processing circuit 100b.

The task manager 172 has ports 150 , 158 and 160 . A signal determination flag 122 is input to the port 150 . A hold point arrival signal 134 is input to port 158 . A task processing continuation command 128 is output from the port 160 . The task management unit 172 detects that the signal determination flag 122 has been input to the port 150 and that the hold point arrival signal 134 has been input to the port 158 .

The task execution unit 170 functions as a first execution unit, a holding unit and a second execution unit.

When the input voltage 120 becomes lower than the threshold value after the timer 210 starts measuring the time and before the second time elapses, the task management unit 172 causes the first execution unit to execute the first execution of the task 180 . When the execution of part 190 of 1 is completed, a reset command 132 is issued to the holding unit. Further, the task management unit 172 determines that the first execution unit performs the task 180 when the signal confirmation flag 122 is not input even though the second time has elapsed since the timer 210 started measuring the time. When the execution of the first part 190 of is finished, a reset command 132 is issued to the holding unit. Therefore, the task management unit 172 determines whether or not the input voltage 120 satisfies the conditions described below. When it is determined that the conditions described below are satisfied, the holding unit is instructed to do the following. The conditions to be satisfied are that the input voltage 120 falls below the threshold within the second time after the edge 124 of the input voltage 120 is applied, and that the edge 124 of the input voltage 120 is applied at least one of the conditions that the input voltage determination unit 110 has not determined that the input voltage 120 is a signal even though the second time has elapsed since . What is directed is to reset the results of the execution of the first portion 190 of task 180 .

In the digital signal processing circuit 100b, similarly to the digital signal processing circuit 100a, the response speed of the processor 112 can be improved, malfunctions due to noise can be suppressed, and these effects can be exhibited. Restrictions on types can be reduced.

Moreover, in the digital signal processing circuit 100b, the task management unit 172 does not need to monitor the execution state of the task 180, and does not need to issue the task processing stop command 130. FIG. Thereby, the task management unit 172 can be simplified.

3 Embodiment 3
FIG. 3 is a block diagram illustrating a digital signal processing circuit according to a third embodiment;

The digital signal processing circuit 100c of the third embodiment shown in FIG. 3 differs from the digital signal processing circuit 100a of the first embodiment shown in FIG. 1 in the following points.

First, in the digital signal processing circuit 100a, an input voltage determination unit 110 and a task management unit 172 are provided which are separated from each other. built into the On the other hand, in the digital signal processing circuit 100c, an input voltage determination/task management unit 174 in which the input voltage determination unit 110 and the task management unit 172 are integrated is provided. 112. Input voltage determination/task management unit 174 may be externally attached to processor 112 .

Second, in the digital signal processing circuit 100a, when the input voltage 120 becomes lower than the threshold during the period from when the timer 210 starts measuring time until the second time elapses, and when the timer 210 A command is issued to the task execution unit 170 in at least one of cases where the signal determination flag 122 has not been input even though the second time has elapsed since the measurement of . On the other hand, in the digital signal processing circuit 100c, when the input voltage 120 becomes lower than the threshold during the period from when the timer 210 starts measuring the time until the second time elapses, the command is issued to the task. Issued to the execution unit 170 .

The configuration of the digital signal processing circuit 100c related to the above difference will be described below. As for the configuration not described, the configuration adopted in the digital signal processing circuit 100a is also adopted in the digital signal processing circuit 100c.

Input voltage determination/task management unit 174 includes ports 140 , 142 , 152 and 154 . Edge 124 of input voltage 120 is input to port 140 . A task processing continuation command 128 is output from the port 142 . A task processing stop command 130 is output from the port 152 . A reset command 132 is output from the port 154 . Input voltage determination/task management unit 174 detects that edge 124 of input voltage 120 is input to port 140 .

The task execution unit 170 functions as a first execution unit, a holding unit and a second execution unit.

The input voltage determination/task management unit 174 detects that the input voltage 120 is a signal when the input voltage 120 continues to be equal to or higher than the threshold until the first time elapses after the edge 124 of the input voltage 120 is input. Determine that there is. Also, the input voltage determination/task management unit 174 generates the signal determination flag 122 when determining that the input voltage 120 is a signal. The generated signal determination flag 122 is output from the port 142 and becomes a task processing continuation command 128 issued to the second execution unit. As a result, after the input voltage determination/task management unit 174 determines that the input voltage 120 is a signal, the second execution unit takes over the execution result of the first part 190 of the task 180 and executes the task 180. Execution of the second portion 192 begins.

The input voltage determination/task management unit 174 causes the timer 210 to start measuring time when the input voltage 120 becomes lower than the threshold value during the period from when the timer 210 starts measuring time to when the second time elapses. is reset, and the noise determination flag 136 is generated. The generated noise determination flag 136 is output from the port 152 when the first execution unit is executing the first part 190 of the task 180, and the task processing signal issued to the first execution unit. A stop command 130 is issued. The generated noise determination flag 136 is the reset command 132 output from the port 154 and issued to the holding unit when the first execution unit has finished executing the first part 190 of the task 180 . becomes.

Accordingly, the input voltage determination/task management unit 174 determines whether or not the input voltage 120 satisfies the conditions described below. When it is determined that the input voltage 120 satisfies the conditions described below, the first execution section or holding section is instructed to do the following. The condition to be satisfied is that the input voltage 120 falls below the threshold within a second period of time after the edge 124 of the input voltage 120 is input. What is directed is at least one of aborting execution of the first portion 190 of task 180 and resetting the results of execution of the first portion 190 of task 180 . What is instructed is that if the first execution part is executing the first part 190 of the task 180, it is to stop executing the first part 190 of the task 180, and the first execution part is finished executing the first portion 190 of task 180, resetting the results of the execution of the first portion 190 of task 180;

In the digital signal processing circuit 100c, similarly to the digital signal processing circuit 100a, the response speed of the processor 112 can be improved, malfunctions due to noise can be suppressed, and these effects can be exhibited. Restrictions on types can be reduced.

4 Embodiment 4
FIG. 4 is a block diagram illustrating a digital signal processing circuit according to a fourth embodiment.

A digital signal processing circuit 100d according to the fourth embodiment shown in FIG. 4 differs from the digital signal processing circuit 100a according to the first embodiment shown in FIG. 1 in the following points.

In the digital signal processing circuit 100a, the task management unit 172 determines that the input voltage 120 becomes lower than the threshold during the period from when the timer 210 starts measuring time until the second time elapses, and when the timer 210 A command is issued to the task execution unit 170 in at least one of the cases where the signal determination flag 122 is not input even though the second time has elapsed since the start of time measurement. On the other hand, in the digital signal processing circuit 100d, the input voltage determination unit 110 determines that the input voltage 120 becomes lower than the threshold during the period from when the timer 210 starts measuring the time until the second time elapses. If so, the noise determination flag 136 is generated. Also, the task management unit 172 issues a command to the task execution unit 170 when the noise determination flag 136 is generated.

The configuration of the digital signal processing circuit 100d related to the above differences will be described below. As for the configuration not described, the configuration adopted in the digital signal processing circuit 100a is also adopted in the digital signal processing circuit 100d.

The input voltage determination unit 110 has a port 162 . A noise determination flag 136 is output from the port 162 .

The task manager 172 has ports 164 , 152 and 154 . The noise determination flag 136 is input to the port 164 . A task processing stop command 130 is output from the port 152 . A reset command 132 is output from the port 154 . The task management unit 172 detects that the noise confirmation flag 136 has been input to the port 164 .

The task execution unit 170 functions as a first execution unit, a holding unit and a second execution unit.

When the noise determination flag 136 is input, the task management unit 172 sends the task processing stop command 130 to the first execution unit when the first execution unit is executing the first part 190 of the task 180. and when the first execution unit has finished executing the first part 190 of the task 180, it issues a reset command 132 to the holding unit. Accordingly, the input voltage determination unit 110 determines whether or not the input voltage 120 satisfies the below-described condition, and the task management unit 172 causes the input voltage determination unit 110 to determine if the input voltage 120 satisfies the below-described condition. If so, instruct the first executor or holder to do the following. The condition to be satisfied is that the input voltage 120 falls below the threshold within a second period of time after the edge 124 of the input voltage 120 is input. What is directed is at least one of aborting execution of the first portion 190 of task 180 and resetting the results of execution of the first portion 190 of task 180 . is instructed to cease execution of the first portion 190 of the task 180 if the first execution portion of the task executor 170 is executing the first portion 190 of the task 180; If the first execution part has finished executing the first part 190 of the task 180 , reset the result of the execution of the first part 190 of the task 180 .

In the digital signal processing circuit 100d, as in the digital signal processing circuit 100a, the response speed of the processor 112 can be improved, malfunctions due to noise can be suppressed, and these effects can be exhibited. Restrictions on types can be reduced.

Further, in the digital signal processing circuit 100d, the task management unit 172 does not need to detect that the edge 124 of the input voltage 120 is input, and the time elapsed after the edge 124 of the input voltage 120 is input can be set by the timer. 210 does not need to be measured, and there is no need to issue the task processing continuation command 128 . Thereby, the task management unit 172 can be simplified.

5 Modifications In the description of the digital signal processing circuits 100a, 100b, 100c, and 100d of Embodiments 1 to 4, one input voltage 120 is input to the processor 112 for the sake of simplicity. However, multiple input voltages 120 may be input to processor 112 .

In the first modification, a plurality of input voltages 120 are input to a processor 112 , a plurality of input voltage determination units 110 corresponding to the plurality of input voltages 120 are provided, and a plurality of voltage detectors 110 corresponding to the plurality of input voltages 120 are provided. task management unit 172 is provided.

In the second modification, a plurality of input voltages 120 are input to the processor 112, one input voltage determination unit 110 corresponding to the plurality of input voltages 120 is provided, and one task corresponding to the plurality of input voltages 120 is provided. A management unit 172 is provided. However, one input voltage determination unit 110 and one task management unit 172 handle the plurality of input voltages 120 independently of each other.

The first modified example and the second modified example may be mixed.

A plurality of input voltages 120 are input to the processor 112, and the first processing of task 180, which is started in conjunction with the input of the edge 124 of the input voltage 120, stores the time when the edge 124 of the input voltage 120 is detected. , it is possible to precisely measure the time deviation between a plurality of signals that are input substantially at the same time.

When noise is removed by a hardware filter, errors may occur in the measured time deviation due to variations in the constants of the elements provided in the hardware filter. decline may occur. Further, when noise is removed by a software filter, a delay in signal transmission due to the software filter causes deterioration in real-time performance. However, in the first modified example and the second modified example described above, these hardware filters and software filters can be omitted, and these problems can be resolved.

In addition, within the scope of the invention, the embodiments can be appropriately modified or omitted.

Although the present invention has been described in detail, the above description is, in all aspects, illustrative and not intended to limit the present invention. It is understood that numerous variations not illustrated can be envisioned without departing from the scope of the invention.

100a, 100b, 100c, 100d digital signal processing circuit 110 input voltage determination unit 112 processor 170 task execution unit 172 task management unit 174 input voltage determination/task management unit 180 task 190 first part 192 Second part, 200 hold points.

Claims (7)

a determination unit that determines whether the input voltage is a signal;
Execution of a first part of a task before or before a hold point built in a processor and before a point at which a malfunction occurs if said input voltage is a false input. a first execution unit that starts in conjunction with an input of an edge;
a holding unit built in the processor and holding a result of execution of the first part when the first execution unit finishes executing the first part;
a second portion of the task built in the processor and after the hold point taking over the result of execution of the first portion after the determining unit determines that the input voltage is the signal; a second execution unit that initiates execution;
In the first execution, when it is determined that the input voltage satisfies a condition in a state where the input voltage is not determined to be the signal by the determination unit, the execution of the first part is stopped. a management unit that at least one of instructs a unit and instructs the holding unit to reset results of execution of the first portion;
with
The determination unit determines that the input voltage is the signal when a state in which the input voltage is equal to or higher than a threshold continues until a first time elapses after an edge of the input voltage is input,
the condition is that the input voltage becomes lower than the threshold within a period of time from when the edge of the input voltage is input until a second time elapses;
The second time is the same time as the first time or longer than the first time
Digital signal processing circuit. a determination unit that determines whether the input voltage is a signal;
Execution of a first part of a task before or before a hold point built in a processor and before a point at which a malfunction occurs if said input voltage is a false input. a first execution unit that starts in conjunction with an input of an edge;
a holding unit built in the processor and holding a result of execution of the first part when the first execution unit finishes executing the first part;
a second portion of the task built in the processor and after the hold point taking over the result of execution of the first portion after the determining unit determines that the input voltage is the signal; a second execution unit that initiates execution;
In the first execution, when it is determined that the input voltage satisfies a condition in a state where the input voltage is not determined to be the signal by the determination unit, the execution of the first part is stopped. a management unit that at least one of instructs a unit and instructs the holding unit to reset results of execution of the first portion;
with
The determination unit determines that the input voltage is the signal when a state in which the input voltage is equal to or higher than a threshold continues until a first time elapses after an edge of the input voltage is input,
the condition is that the determination unit has not determined that the input voltage is the signal even though a second time has passed since the edge of the input voltage was input ;
The second time is the same time as the first time or longer than the first time
Digital signal processing circuit. The management department
determining whether the input voltage satisfies the condition;
The first execution unit executes the first part when it is determined that the input voltage satisfies the condition in a state where the determination unit has not determined that the input voltage is the signal. when the execution of the first part is stopped, and when the first execution part has finished executing the first part, the first execution part is executed. 3. A digital signal processing circuit according to claim 1 or 2, commanding said holding unit to reset the result of execution of the part of . The management department
When the determination unit determines that the input voltage is the signal and the first execution unit ends execution of the first part, the second execution part starts execution of the second part. command the execution part of
determining whether the input voltage satisfies the condition;
When it is determined that the input voltage satisfies the condition without being determined by the determination unit that the input voltage is the signal, the first execution unit ends execution of the first part. 3. A digital signal processing circuit according to claim 1 or 2, wherein the holding unit is commanded to reset the result of execution of the first part when the first part is executed. 2. A digital signal processing circuit according to claim 1, wherein said determination section and said management section are integrated. The determination unit further determines whether the input voltage satisfies the condition,
The management unit controls the execution of the first portion when the determination unit determines that the input voltage satisfies the condition and the first execution unit is executing the first portion. instructing the first execution unit to stop execution, and resetting the result of execution of the first part when the first execution unit has finished executing the first part; 2. A digital signal processing circuit according to claim 1, wherein said holding unit is instructed to 7. A digital signal processing circuit according to any one of claims 1 to 6 , wherein said hold point is a point that can be variably set by a user.

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