JPS58158715A - Programmable controller - Google Patents

Abstract

PURPOSE:To attain processing in response to the state of a failure with the user's program, by displaying the number of a failed flag to be detected automatically and repetitively in order with a prescribed interval. CONSTITUTION:When the user's instruction read out from a user's program memory 1 is a failure diagnostic instruction, the number of a failure display flag FR(N) is addressed at an address counter sequentially, and the number of failed flags being FR(N)=1 is counted by an error counter. In detecting the failure flag being FR(N)=1 with the error counter, the failure display flag is set, a failure display lamp of an operating section 6 is lighted and the count value of the error counter is displayed on the number display section. The number of the failed flags being FR(N)=1 is stored in a display objective register from the ascending order, and this is displayed on the number display section sequentially with a prescribed interval repetitively and automatically. As a result, the user grasps the all failure states in advance and a suitable processing is taken with the user's program.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable controller, and more particularly to abnormality display control when a plurality of logical abnormalities occur in a sequence.

In conventional programmable controllers, when a sequence control abnormality occurs due to a defect in an input/output device, the user program detects the logical abnormality and displays the number of the abnormal input/output device as abnormal information. That's what I was doing.

However, such conventional programmable controllers display abnormality information related to the first abnormality detected during a cycle of the user program, and the display cannot be reset until the cause of the abnormality is resolved. Because of this configuration, when an abnormality occurs, the device must be completely stopped, which is often not always appropriate from the user's perspective.

In other words, it is necessary to understand in advance all the abnormal conditions that occur during one round of execution of the user program, and to take decisions and actions in accordance with the type of abnormality and the situation of the controlled object in which the abnormality has occurred in the user program. was difficult.

As a countermeasure, for example, it is possible to display the abnormality for each controlled object and leave it to the user's discretion when an abnormality occurs, but this would increase the size of the display unit and is not practical.

This invention has been made in view of the above conventional problems, and its purpose is to easily display the numbers of each control object in which an abnormality has occurred on a single display, and to detect the abnormality using a user program. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which provide a programmable controller that can take measures depending on the situation.

FIG. 1 is a block diagram showing a schematic configuration of a programmable controller according to the present invention.

This programmable controller has a user program memory 1 in which user programs are stored, an input circuit 2 to which external input signals are applied, an output circuit 3 to send out external output signals, and corresponds to the input circuit 2 and output circuit 3 described above. The input/output memory 4 serves as a buffer memory for input/output data, and each instruction in the user program memory 1 is executed in sequence at high speed, arithmetic processing is performed based on the data in the input/output memory 4, and the processing results are used to execute the above input/output data. an instruction execution means for rewriting output data of the output memory 4; and the input circuit 2.
The input/output memory 4 basically has an input updating means for writing input data into a predetermined area of the input/output memory 4, and an output updating means for setting output data of the predetermined area of the input/output memory 4 into the output circuit 3. There is. The above-mentioned instruction execution means, input updating means and output updating means are realized by a CPLI (Central Processing Unit) 5 constituted by a so-called microprocessor. In addition to controlling operations as an instruction execution means and an input/output updating means, the CPU 5 executes various O8 processes (operating system) to be described later, including a failure display routine according to the present invention, on the operation unit 6 in response to a scheduled interrupt. At this time, the memory 7, which is a RAM, is used as a working memory.

Further, the fault diagnosis instruction according to the present invention, which is arbitrarily set in the user program memory 1 as a part of the user program, is specified by the 21monique FAL in the operation code section, and an abnormality flag (described later) is specified in the operand section. The number @N (N-0 to M) of FR(N) is specified. Hereinafter, the fault diagnosis command will be referred to as a FAL command.

FIG. 2 is a diagram showing a portion of the operating section 6 according to the present invention. This operation section 6 includes a failure indicator lamp 8 for reporting the occurrence of an abnormality, a number display section 9 for displaying the number of abnormalities that have occurred during one round of execution of the user program, and a number display section 9 for displaying the number of abnormalities that have occurred during the execution of one cycle of the user program. A number display section 10 that automatically and repeatedly displays numbers in order at regular intervals, a hold switch H8W that stops the repeated display on the number display section 10 and continues to display a specific number, and each of the above displays. Part 8.9
．． A reset switch R8W is provided for resetting the display of 10 and initializing the device.

FIG. 3 shows flags and the like provided in the working memory 7 in order for the CPU 5 to execute the failure display routine according to the present invention.

During the operation of the instruction execution means, the working memory 7 is individually set or reset with the result of any logical operation between any input/output data by executing the FAL instruction, and is stored in the user program. Can be used arbitrarily as a logical operation target in the special number N
(N-0 to M) are provided with M abnormality flags FR(
N), and an abnormality flag F every time the instruction execution means executes one round.
Dress R(N) 7 times from N-1 to N-M,
The number of the abnormality flag FR(N) which is FR(N)-1 is detected every time the CPU 5 receives a scheduled interrupt. an address counter ADC for storing N in a display target register DCR in descending order and automatically repeatedly displaying it on the number display section 10 at regular intervals;
As a result of the above-mentioned addressing, when the abnormality flag FR(N) which is FR(N)-1 is detected, it is set and the above-mentioned fault indicator lamp 8 is turned on, and the fault display is reset by operating the above-mentioned reset switch R8W. Flag F and
An error counter E that detects the total number of abnormality flags FR(N) that are FR(N)-1 detected as a result of the addressing and displays the number on the number display section 9.
RC and each time the hold switch H8W is operated, the number is automatically and repeatedly displayed on the number display section 10 at regular intervals, or the display is stopped repeatedly and a specific number is continued. A bold flag HF is provided for controlling whether to display or not.

FIG. 4 shows an example of a fault detection program, which is part of a user program, expressed in the form of a relay ladder diagram. Part A in the diagram is LDXI, ANDX
2. After sequentially executing each logical operation of LDX3.0RLD and ANDX4, FALol is executed, and the abnormal flag FR (01) is set or reset depending on the contents of the calculation register.
The execution result of OL is the input condition of 0LJTIO, which indicates that, for example, a buzzer is driven. In this way, the user program according to the present invention is optionally provided with the FAL instruction.

5A and 5B are flowcharts showing mainly the parts related to the present invention of the system program executed by the CPU 5, and FIG. FIG. 8 shows the display side control operation of automatically updating the number N of each abnormality flag FR (N>) on the number display section 10 by a scheduled interruption and repeatedly displaying this. The control operation of the CPU 5 will be explained according to A and B.

In FIG. 1A, in the first step 10o, various well-known initial processes are performed upon power-on, and each display on the operation unit 6 and each flag, counter, etc. in the working memory 7 are reset.

In step 101, an input update operation is performed in which the external input signal applied to the input circuit 2 is taken into a predetermined area of the input/output memory 4. The subsequent step 102 and subsequent steps are the user program execution routine.

First, in step 102, one instruction is read from the starting address of the user program memory 1. If the read user command is neither a FAL command nor an END command, the process proceeds to step 103 → 104 → 1°5, and this step 10
Step 5 executes the instruction, steps 109 increments the program counter, and returns to step 102 to read the next user instruction from user program memory 1. The above operations are repeatedly executed at high speed, and the operation results of each user instruction remain in the operation register.

Then, the user command read in step 102 is
If it is an L instruction, this is detected in step 103 and the process proceeds to step 106. Step 106 is a routine for determining whether or not there is an abnormality in the controlled object related to the FAL instruction, which is determined based on the contents of the operation register. That is, if the calculation result is 1, the process proceeds to step 107 and the abnormality display flag FR(N> is set. If the calculation result is not 1, the abnormality display flag FR(N) is reset in step 108.Next, The program counter is incremented in step 109 and the process returns to step 102 to read the next user command from the user program memory 1.

In other words, the EN inserted at the end of the user program
Step 1 until the D instruction is detected in step 104.
02 to step 109 are repeatedly executed at high speed,
A predetermined logical operation is performed, and a logical abnormality is detected by an appropriately executed FAL instruction. The above is the operation of the instruction execution means.

Then, when an END command is detected in step 104,
In step 110, the output data of the input/output memory 4 is rewritten according to the execution result of each instruction executed by the operation of the instruction execution means (operation of the output update means), and in step 111, the program counter is reset, thereby making the user program known. Execution completes.

In the next step 112, it is determined whether the failure display flag F has already been set, and if the result is No, each routine from steps 113 to 117 is executed. In this routine, the address counter ADC addresses the number N of the abnormal flag FR(N>) up to O-M, and the abnormal flag FR(N), which is FR(N)-1, is addressed by the address counter ADC.
) is counted by the error counter ERC.

As a result, if the error counter ERC does not count anything at step 118, the process returns to step 101 and preparations are made to execute the user program. If the error counter ERC detects an abnormality flag of FR(N)-1, the process proceeds to step 119→120, sets the failure display flag F, and lights up the failure indicator lamp 8 of the operation unit 6. , an error counter ER is displayed on the number display section 9.
Display the count value of C. Next, in step 121, the address counter ADC and the hold flag HF are reset,
Prepare for switch operation by the operator in step 122. Note that if the determination result in step 112 is YES, the process similarly proceeds to step 122.

Step 122 is a routine for detecting whether or not the hold switch H8W has been operated.
is operated, the hold flag HF is set in step 123.
is checked, and if the hold flag HF is reset, it is set in step 124, and if the hold flag HF is set, it is set in step 124.
This is reset in step 5.6 In other words, each time the operation of the hold switch H8W is detected in step 122, the hold flag HF is inverted. The operation of this hold switch H8W causes the operator to decide whether to stop the automatic update display of the number of the abnormality flag FR (N>, which is displayed in the scheduled interrupt processing described later), and to continue displaying the same number. This is what we do.

The next step 126 is a routine to determine whether the reset switch R8W has been operated, and the next step 127
Then, the various flags mentioned above are reset.
Return to step 101.

Next, in Figure B, CPL15 is one of the scheduled interrupts.
When one interrupt is received, first in step 130 it is determined whether or not a failure display flag F is set. If the determination result is NO, the control target of the device is normal, and the CPU 5 returns to the program before accepting the interrupt. Moreover, if the judgment result is YES, step 13
1 (hold flag) Check the IF status. As a result, if the hold flag HF is reset, the execution of each routine of steps 132 → 133 → 134 → 131 → 132 will cause the hold flag HF to be A smaller number is detected.Next, in step 135, that number N is displayed in the register DC.
It is set to R and displayed on the number display section 10 in step 136. Then, in step 137, the address counter ADC is incremented to prepare for the next interrupt reception.

Next, when the CPU 5 accepts the next interrupt, step 13
0 to step 131. As a result, if the hold flag HF is set, the CPU 5 returns to the program before accepting the interrupt without updating the previous number displayed on the number display section 10.

If the hold flag HF is reset, steps 132→133→134→131 are performed as described above.
→By executing each routine of 132, the number display section 10
The abnormality flag number FR(N)-1 to be displayed next is detected, and this is displayed on the number display section 10 by each routine of steps 135 and 136. and,
When all the abnormality flags that are FR(N)-1 are detected in step 134, the address counter ADC is reset in step 138, and the process returns to step 131.

As described above, each time the CPU 5 receives a scheduled interrupt, the numbers are displayed on the number display section 10, and the numbers are automatically updated in descending order of number and displayed at regular intervals, and this is repeated. Further, by operating the hold switch H8W, automatic updating of the number displayed on the number display section 10 is stopped, and the same number is continuously displayed.

As described above in detail, according to the present invention, by executing instructions arbitrarily set in the user program as part of the user 70gram, arbitrary input/output data and the result of arbitrary logical operation can be obtained. a plurality of abnormality flags that are individually set or reset, can be arbitrarily used as logical operation targets in a user program, and are assigned special numbers; and a detection means for detecting a set flag among the abnormality flags; Since the programmable controller is equipped with a display means that automatically and repeatedly displays the number of the abnormality flag detected by the detection means in order at regular intervals, the number of each controlled object in which an abnormality has occurred is displayed as 1. The number can be easily and automatically updated and displayed on one display section, and the same number can be displayed continuously as desired. As a result, the user can grasp all abnormal situations in advance, and can take appropriate judgments and measures depending on the control target where the abnormality has occurred, using the user program or the user's judgment at the time. A programmable controller that is much easier to use than conventional ones can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a programmable controller according to the present invention, FIG. 2 is a schematic diagram showing a portion of an operation unit according to the present invention, and FIG. 3 is a flag according to the present invention provided in a working memory. 4 is a schematic diagram representing an example of a fault detection program which is a part of the user program in the form of a relay ladder diagram, and FIG. 5 is a schematic diagram showing the control operation of the above programmable controller A flowchart mainly showing the parts related to the invention,
Figure A shows an abnormality detection operation in the process of one round of user program execution, and Figure B shows a display control operation in which each abnormality flag number is automatically updated by a scheduled interrupt and repeatedly displayed. There is. 1......User program memory 2...Input circuit 3...
・・・・・・・・・・・・Output circuit 4・・・・・・・
・・・・・・・・・Input/output memory 5・・・・・・・・・・・・
・・・・・・CPU6・・・・・・・・・・・・・Operation unit 7・・・・・・・・・・・・・・・Working memory 8・・・・・・・・・・・・・・・・・・Fault indicator lamp 1
0...Number display section FR(N)...
・Abnormal flag ADC・・・・・・Address counter ERC・・
・・・・・・Error counter DCR・・・・・・・・・
・Display target register F・・・・・・・・・・・・・・・
Trouble display flag diagram 1

Claims (1)

[Claims] (1) Serves as a user program memory in which user programs are stored, an input circuit to which external input signals are applied, an output circuit to send out external output signals, and a buffer memory for output data corresponding to the input circuits and output circuits. an input/output memory and an instruction execution means for sequentially executing each instruction in the user program memory at high speed, performing arithmetic processing based on the data in the input/output memory, and switching output data in the input/output memory based on the result; A programmable controller comprising input updating means for writing input data of an input circuit to a predetermined area of the input/output memory, and output updating means for setting output data of the predetermined area of the input/output memory to the output circuit. By executing instructions arbitrarily set in the user program as part of the program, any input/output data can be individually set or reset as a result of any logical operation, and as a logical operation target in the user program. A plurality of abnormality flags that can be used arbitrarily and are assigned special numbers, a detection means for detecting a set flag among the above abnormality flags, and a number of abnormality flags detected by the above detection means are automatically determined. A programmable
controller.