JPH0411881B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable controller, and particularly to abnormality display control when a logical abnormality occurs in a sequence.

When an abnormality occurs in sequence control due to a defect in input/output equipment, a programmable controller capable of displaying the abnormality is conventionally known, as disclosed in, for example, Japanese Patent Application Laid-Open No. 57-45611.

However, in order to display the faulty element location and element name, conventional displays such as those described above require condition matching traces to be performed in a maintenance display connected to the programmable control, which requires a condition matching trace circuit. Since a memory circuit, ie, ROM, is required to store the processing procedure of the condition matching trace, high cost and weight are unavoidable, and a large installation space is required.

Further, according to the display device as described above, when changing the processing procedure for detecting an abnormality, there is a problem that the circuit needs to be modified and cannot be easily changed.

This invention was made in view of the above-mentioned conventional problems, and its purpose is to allow the user program to freely set abnormality flags, and to set control targets in correspondence with each abnormality flag number. By making it possible to set arbitrary messages such as the type of error and the action to be taken in response, even non-experts can easily respond to failures, etc., and can easily identify the control object where an abnormality has occurred without performing condition matching tracing. The type of abnormality and the action to be taken in response to it are displayed in the form of a message, thereby reducing cost, weight, and space, as well as allowing changes to be made in the event of a change in the processing procedure for detecting an abnormality. By providing an easy-to-use programmable controller that makes it easy to
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of a programmable controller according to the present invention. This programmable controller includes a user program memory 1 in which a UDA program including a failure diagnosis program according to the present invention is stored, an input circuit 2 to which an external input signal is applied, an output circuit 3 to send an external output signal, and the above-mentioned The input/output memory 4 serves as a buffer memory for input/output data corresponding to the input circuit 2 and the output circuit 3, and each instruction in the user program memory 1 is sequentially executed at high speed, and arithmetic processing is performed based on the data in the input/output memory 4. and an instruction execution means for rewriting the output data of the input/output memory 4 with the processing result, and the input circuit 2.
basically comprises an input updating means for writing the input data of the input/output memory 4 into a predetermined area of the input/output memory 4, and an output updating means for setting the output data of the predetermined area of the input/output memory 4 in the output circuit 3, A message memory 6 for storing messages related to respective failure diagnosis programs that are preset in association with each number (N=O to M) of abnormality flags FR (N) according to the present invention, which will be described later by the user, and the message memory 6; 6, an operation display section 9 having a keyboard 7 for setting a predetermined message, and a display section 8 for displaying various displays according to the present invention. The above-mentioned instruction execution means, input updating means and output updating means are realized by a CPU (central processing unit) 5 constituted by a so-called microprocessor. In addition to control operations as an instruction execution means and input/output updating means, the CPU 5 performs various OS processing (operating and system), and at that time the memory 10, which is RAM, is used as working memory. Note that the message memory 6 is provided with a power source 11 for compensating for power outages.

The output command of the fault diagnosis program arbitrarily set as part of the user program in the user program memory 1 is specified by the mnemonic FAL in its operation code section, and the number of the abnormality flag FR (N) in its operand section. (N=O
~M).

FIG. 2 is a diagram schematically showing the key arrangement of the keyboard 7. As shown in FIG. This keyboard 7 includes a numeric keypad for creating a message to be set in the message memory 6 in the form of a katakana code, a message key MSG used to set a predetermined message in the message memory 6, and a message key MSG for creating a message to be set in the message memory 6 in the form of a katakana code. A hold switch key HLD is used to stop the repeated display described later and continue to display a specific abnormality flag number and its corresponding message, and a hold switch key HLD is used to reset each display on the display section 8 and initialize the device. Reset switch key RST and
It also has other key groups.

FIG. 3 is a diagram showing the display mode on the display section 8. This display section 8 is divided into an upper stage and a lower stage.
The upper row shows a failure display section 8A that displays the message "Koshiyouari" indicating that a failure has occurred, a number display section 8B that displays the total number of failures that occurred during one round of execution of the user program, and a control object that has exhibited an abnormal situation. The number display part 8C displays a number, and the number display part 8C has a symbol indicating an abnormality flag.
FR and its number N are displayed, and this number N is automatically and repeatedly displayed in order at regular intervals.
Further, the lower part is a message display section 8D that displays the message corresponding to the number N in katakana, and this message display section 8D is in this embodiment.
16 katakana characters can be displayed, and these 16 katakana characters are arbitrarily set in the message memory 6 in the form of a code by the user using the numeric keypad described above, and in the example shown, they correspond to the abnormal flag FR01. Indicates that the message is "conveyor motor transfer". The display modes of the failure display section 8A and the number display section 8b remain unchanged until they are reset using the reset switch key RST, and the display modes of the number display section 8C and the message display section 8D are automatically set at a fixed interval. will be updated and displayed.

FIG. 4 shows a working memory 10 in which the CPU 5 executes various display controls according to the present invention.
This shows the flags etc. set in the . During the operation of the instruction execution means, the results of arbitrary logical operations between arbitrary input and output data are individually set or reset in the working memory 10 by executing the instructions of the fault diagnosis program. M abnormality flags FR(N) to which different numbers N (N=0 to M) are assigned, and abnormality flags FR(N) are sent to the above-mentioned instruction execution means every round of execution.
Addressing from =1 to N=M and FR(N)
In addition to detecting the abnormality flag that is set to =1, the FR
An address counter ADC for storing the numbers N of abnormality flags with (N) = 1 in the display target register DCR in descending order and automatically repeatedly displaying them in the number display section 8C in order; As a result, when the abnormality flag FR(N) with FR(N) = 1 is detected, it is set to display the message "Failure" on the fault display section 8 and press the reset switch key.
Failure display flag F reset by RST operation
and the FR detected as a result of the above addressing
The error counter ERC detects the total number of abnormality flags with (N) = 1 and displays the number on the number display section 8B, and the CPU 5 performs a reversal operation every time the hold switch key HLD is operated. When an interrupt is accepted, the hold flag HF controls whether or not to update the display on the number display section 8C and the message display section 8D, and the number of the abnormality flag displayed on the number display section 8C. A message storage unit WDM (in this embodiment, a 16-word memory area is prepared) stores a message to be displayed on the message display unit 8D corresponding to the message display unit 8D, and each time the CPU 5 receives a scheduled interrupt,
Corresponding to the number of the abnormality flag displayed on the number display section 8C, the address of the message memory 6 storing the message to be displayed on the message display section 8D is designated and addressed, and the message storage is performed. Transfer word counter for transferring 16 words of katakana code to part WDM
TWC and TWC are provided respectively.

FIG. 5 shows an example of a fault diagnosis program that is part of the user program, expressed in the form of a relay ladder.

Part A in the diagram is LDX1, ANDX2, LDX
After sequentially executing each logical operation of 3, ORLD, ANDX4, FAL01 is executed, indicating that the abnormality flag FR (01) is set or reset depending on the contents of the operation register.
The execution result of FAL01 is the input condition for OUT10, which indicates that, for example, a buzzer will be driven. In this way, the user program according to the present invention is optionally provided with the FAL instruction.

6A and 6B are flowcharts showing an overview of the system program executed by the CPU 5, focusing on the display control operation according to the present invention, and FIG. The operation is also shown in FIG. 2B, which automatically updates the number N of each abnormal flag FR(N) in the number display section 8C and the message corresponding to the number N in the message display section 8D by a scheduled interrupt. and display control operations for repeatedly displaying this.

In FIG. 1A, in the first step 100, various well-known initial processes are performed upon power-on, and each display on the display section 8 and each flag, counter, etc. in the working memory 10 are reset.

In step 101, an input update operation is performed to input the external input signal applied to the input circuit 2 into a predetermined area of the input/output memory 4. Next step 102
The following is the user program execution routine.

First, in step 102, one instruction is read from the starting address of the user program memory 1. If the read user instruction is neither a FAL instruction nor an END instruction, the process proceeds to steps 103→104→105, executes the instruction in step 105, and then proceeds to step 109.
Then, the program counter is incremented and the process returns to step 102, where the next user command is read from the user program memory 1. The above operations are repeatedly executed at high speed, and the operation results of each user instruction remain in the operation register.

If the user command read in step 102 is a FAL command, this is detected in step 103 and the process advances to step 106. Step 106 is FAL
This is a routine that determines whether or not there is an abnormality in the control target related to the instruction, and this is determined based on the contents of the operation register. That is, if the calculation result is 1, proceed to step 107 and set the abnormality display flag FR(N), and if the calculation result is not 1, proceed to step 108.
Reset the abnormality display flag FR(N) with . Then, in step 109, the program counter is incremented and the process returns to step 102, where the next user command is read from the user program memory 1.

In other words, until the END instruction inserted at the end of the user program is detected in step 104,
Steps 102 to 109 are repeatedly executed at high speed, predetermined logical operations are performed, and logical abnormalities are detected by the FAL instruction executed as appropriate. The above is the operation of the instruction execution means.

Next, when the END command is detected in step 104, the output data of the input/output memory 4 is rewritten according to the execution results of each instruction executed by the operation of the instruction execution means (operation of the output update means) in step 110. ), the program counter is reset in step 111, completing the well-known round execution of the user program.

In the next step 112, it is determined whether the failure display flag F has already been set, and if the result is NO, each routine from steps 113 to 117 is executed. In this routine, the address counter ADC addresses the number N of the abnormality flag FR(N) from 0 to M, and the number of abnormality flags FR(N) with FR(N) = 1 is counted using the error counter ERC. .

As a result, in step 118 the error counter ERC
However, if it is not counted, return to step 101.
Preparations are made to execute the user program.
Then, if the error counter ERC detects an abnormality flag with FR(N)=1, step 119→
120, sets the failure indication flag F, and lights up the failure indication lamp 8A of the display section 8.
The counted value of the error counter ERC is displayed on the number display section 8B. Next, in step 121, the address counter ADC and the hold flag HF are reset in preparation for the operator's switch operation in step 122. Note that if the determination result in step 112 is YES, the process similarly proceeds to step 122.

Step 122 is a routine to detect whether or not the hold switch HSW has been operated. When the hold switch HSW is operated, the state of the hold flag HF is checked in step 123, and if the hold flag HF has been reset, the routine returns to step 124. If the hold flag HF is set, it is reset in step 125. In other words, in step 122 the hold switch is
Hold flag every time HSW operation is detected
HF is made to operate in reverse. The operation of this hold switch HSW stops the automatic update display of the abnormality flag FR (N) number displayed in the scheduled interrupt processing described later, and the operator decides whether or not to continue displaying the same number. This is what we do.

The next step 126 is a routine for determining whether or not the reset switch RSW has been operated, and the process advances to the next step 127, where the various flags and the like are reset, and the process returns to step 101.

Next, in FIG. 5B, when the CPU 5 receives one of the scheduled interrupts, it first determines in step 130 whether or not the failure display flag F is set. If the determination result is NO, the control target of the device is normal, and the CPU 5 returns to the program before accepting the interrupt. Further, if the judgment result is YES, the state of the hold flag HF is checked in step 131. As a result, if the hold flag HF is HF=0, step 132→
The routines 133 → 134 → 131 → 132 are executed, and the address counter ADC addresses
The lowest number among the abnormality flags with FR(N)=1 is detected, and in step 135 that number N is set in the display target register DCR.
In step 136, the number is displayed on the number display section 8C, and in step 137, the address counter ADC is incremented. Next, in step 138, the address of the message memory (MGM) 6 where the message corresponding to that number is stored is specified, and in step 139, the transfer word counter TWC is reset, and the routines of steps 140→141→142 are executed. While updating the transfer word counter TWC, each word of the message consisting of katakana codes is transferred to the message storage unit WDM up to 16 words. Then, in step 143, the predetermined message transferred to the message storage section WDM is displayed on the message display section 8D, and the CPU 5 returns to the program before accepting the interrupt.

When CPU5 accepts the next interrupt, step 130
Proceed to step 131 via . As a result, if the hold flag HF is HF=1, number display section 8C
The CPU 5 returns to the program before accepting the interrupt without updating the numbers displayed on the message display section 8D and the corresponding messages. And hold flag HF is HF=
If it is 0, step 132 → 133 → 134 → 131 → 132
By executing each routine, the number next to the last displayed abnormality flag is detected among the abnormality flags with FR(N)=1, and that number is displayed on the number display section 8C in steps 135 and 136. At the same time, a predetermined message is displayed on the message display section 8D by each routine from steps 138 to 143.

When all the abnormality flags with FR(N)=1 are detected in step 134, the address counter ADC is reset in step 144.
Return to step 131.

As described above, each time the CPU 5 accepts a scheduled interrupt, the numbers of the abnormality flags FR(N) that have been set are automatically updated and displayed on the number display section 8C in ascending order of the number, and this is repeated. , the message corresponding to the number of the abnormality flag FR(N) is similarly automatically updated and repeatedly displayed on the message display section 8D. In addition, by operating the hold switch key HLD, automatic updating of the number displayed on the number display section 8C and the message displayed on the message display section 8D is stopped, and the same message corresponding to the same number continues. will be displayed.

As described in detail above, according to the present invention, by executing a fault diagnosis program arbitrarily set in the user program memory as part of the user program, any logical operation between any input and output data can be performed. As a result, there is a working memory that has a plurality of abnormality flags that are individually set or reset and each assigned a different number, and a user associates each of the abnormality flag numbers with the type of control target and the actions to be taken against it. a message setting means for setting an arbitrary message such as what action should be taken in the message memory; a failure diagnosis means for detecting an abnormality and setting an abnormality flag by a failure diagnosis program in the user program; a detection means for detecting an abnormality flag that is set in the message memory; Since the system is equipped with a display means for reading out and displaying messages to be displayed, abnormality flags can be set freely by a user program set on the user side, and any message can be set in association with each abnormality flag number. Therefore, when a failure occurs, for example, the failure location can be immediately recognized using information suitable for the user side, and the actions to be taken in response to the failure location can be confirmed on the display means. By looking at the message displayed on the display means, even non-experts can easily deal with failures, etc., thereby improving usability on the user side.

In addition, the type of control target in which an abnormality has occurred and the measures to be taken in response to it are displayed in the form of a message, without performing condition matching tracing as in the past, so you can easily understand the condition matching trace circuit and the processing procedure of condition matching tracing. A memory circuit (ROM) for storing data is not required, and therefore cost reduction, weight reduction, and space saving can be achieved.

In addition, as part of the user program, abnormalities are detected by a fault diagnosis program set by the user program, so even if input/output is changed, the processing procedure for detecting abnormalities can be easily changed by changing the user program memory. Therefore, it is possible to provide a programmable controller that is easy to use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the schematic configuration of a programmable controller according to the present invention, FIG. 2 is a schematic diagram showing the key arrangement of the keyboard, FIG. 3 is a schematic diagram showing the display mode of the display section, and FIG. A schematic diagram showing flags etc. according to the present invention provided in the working memory, FIG. 5 is a schematic diagram showing a fault diagnosis program according to the present invention in the form of a relay ladder diagram,
FIGS. 6A and 6B are flowcharts showing an overview of the display control operation of the programmable controller according to the present invention, in which FIG. 6A shows the abnormality detection operation during one round of user program execution, and FIG. Therefore, each number of the abnormality flag and each message corresponding to the number are automatically updated and the display control operation for repeatedly displaying the same is shown. 1... User program memory, 2... Input circuit, 3... Output circuit, 4... Input/output memory, 5...
...CPU, 6...Message memory, 7...Keyboard, 8...Display section, 8D...Message display section, FR(N)...Error flag, ADC...Address counter, ERC...Error counter, DCR...
...Display target register, F...Failure display flag,
HF...Hold flag, TWC...Transfer word counter, WDM...Message storage unit.

Claims (1)

[Scope of Claims] 1. A user program memory in which a user program is stored, an input circuit to which an external input signal is applied, an output circuit to send out an external output signal, and input/output data corresponding to the input circuit and output circuit. The input/output memory serves as a buffer memory, and each instruction of the above user program is executed in sequence at high speed, arithmetic processing is performed based on the data of the above input/output memory, and the output data of the above input/output memory is rewritten with the processing result. A programmable device having an instruction execution means, an input updating means for writing input data of the input circuit to a predetermined area of the input/output memory, and an output updating means for setting output data of the predetermined area of the input/output memory to the output circuit. - In the controller, by executing a fault diagnosis program arbitrarily set in the user program memory as part of the user program, the results of any logical operation between any input/output data can be individually set or reset. , a working memory which has a plurality of abnormality flags to which different numbers are assigned, and a message memory in which the user can store arbitrary messages such as the type of control object and the action to be taken on it in association with each number of the abnormality flags. a message setting means for setting an abnormality flag by a fault diagnosis program in the user program; a detection means for detecting an abnormality flag set by the fault diagnosis means; a display means for reading out and displaying a message corresponding to the set abnormal flag from among the messages set in advance in the message memory by the message setting means when the detecting means detects that the abnormal flag is set; A programmable controller characterized by being equipped with the following.