JP7122061B2 - エアギャップ形成プロセス - Google Patents
エアギャップ形成プロセス Download PDFInfo
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- JP7122061B2 JP7122061B2 JP2020543022A JP2020543022A JP7122061B2 JP 7122061 B2 JP7122061 B2 JP 7122061B2 JP 2020543022 A JP2020543022 A JP 2020543022A JP 2020543022 A JP2020543022 A JP 2020543022A JP 7122061 B2 JP7122061 B2 JP 7122061B2
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
[0001] 本出願は、2018年2月15日に出願された米国仮出願第62/631,179号の利益を主張し、あらゆる目的のために、その全体が参照により本明細書に組み込まれる。
Claims (12)
- 半導体構造内にエアギャップを形成する方法であって、
第1の材料および前記第1の材料とは異なる第2の材料を含むスペーサ構造を形成することと、
少なくとも1つの他の材料によって前記スペーサ構造の前記第2の材料からオフセットされたソース/ドレイン構造を形成することと、
前記スペーサ構造から前記第2の材料をエッチングして、前記エアギャップを形成することと、
を含み、前記ソース/ドレイン構造が、前記エッチング中にエッチャント材料に曝されず、
前記スペーサ構造を形成することが、
ゲート構造に隣接し、前記第1の材料を含む第1のスペーサ層を形成することであって、前記ゲート構造と交差するフィンを少なくとも部分的に覆う第1のスペーサ層を形成することと、
前記第1のスペーサ層に隣接し、前記第2の材料を含む第2のスペーサ層を形成することと、
前記第2のスペーサ層に隣接する第3のスペーサ層を形成することと、
を含む、方法。 - 前記スペーサ構造が、半導体基板上の前記ゲート構造に近接して形成され、前記ソース/ドレイン構造が、前記ゲート構造に垂直に形成される、請求項1に記載の半導体構造内にエアギャップを形成する方法。
- 前記ソース/ドレイン構造が、シリコンまたはシリコンゲルマニウムを含む、請求項1に記載の半導体構造内にエアギャップを形成する方法。
- 前記第1の材料および前記第2の材料が、酸素または窒素を含む、請求項1に記載の半導体構造内にエアギャップを形成する方法。
- 前記第1の材料および前記第2の材料が、窒化シリコン、炭窒化シリコン、酸炭化シリコン、酸炭窒化シリコン、酸化シリコン、金属酸化物、および金属窒化物のうちの1つ以上を含む、請求項4に記載の半導体構造内にエアギャップを形成する方法。
- 前記第3のスペーサ層が、前記第1のスペーサ層と同じ材料である、請求項1に記載の半導体構造内にエアギャップを形成する方法。
- 前記第3のスペーサ層を形成する前に、前記第1のスペーサ層および前記第2のスペーサ層をエッチングして、前記ゲート構造と交差する前記フィンを露出させることと、
前記第3のスペーサ層をエッチングして、前記ゲート構造と交差する前記フィンを部分的に露出させることと、
をさらに含む、請求項6に記載の半導体構造内にエアギャップを形成する方法。 - 基板と、
前記基板の上にあり、前記基板を横切る第1の方向に形成されたゲート構造と、
前記基板の上にあり、前記基板を横切る第2の方向に形成されたフィンであって、前記第2の方向が前記第1の方向に垂直であり、前記フィンが前記ゲート構造と交差する、フィンと、
前記ゲート構造に隣接し、エアギャップを含む少なくとも3つの層を含むスペーサ構造であって、前記ゲート構造から横方向に延在するスペーサ構造と、
前記スペーサ構造の外部で前記フィンの周囲に形成され、前記スペーサ構造から横方向にオフセットされたソース/ドレイン材料であって、前記スペーサ構造の少なくとも1つの介在層が、前記ソース/ドレイン材料と前記エアギャップとの間に含まれる、ソース/ドレイン材料と、
を備える半導体構造。 - 前記スペーサ構造が、前記ゲート構造に隣接する第1の層であって、前記フィンおよび前記基板上で前記ゲート構造から横方向外側に第1の距離を延在する第1の層を備える、請求項8に記載の半導体構造。
- 前記スペーサ構造が、前記第1の層から横方向外側の第2の層であって、前記第1の距離で前記第1の層に接触する第2の層を、さらに含み、前記エアギャップが、前記ゲート構造に隣接する前記第1の層の部分と、前記基板の上にある前記第1の層の部分と、前記第2の層との間に少なくとも部分的に画定され、前記第1の層および前記第2の層が、窒化シリコン、炭窒化シリコン、酸炭化シリコン、酸炭窒化シリコン、酸化シリコン、金属酸化物、および金属窒化物からなる群から選択される1つ以上の材料を含む、請求項9に記載の半導体構造。
- 前記ゲート構造からの方向において前記スペーサ構造の横方向外側に配置されたコンタクトエッチストップ層を、さらに備える、請求項8に記載の半導体構造。
- 半導体構造を形成する方法であって、
半導体基板上のゲート構造に近接する第1のスペーサ層であって、前記半導体基板上に形成されたフィンを少なくとも部分的に覆う第1のスペーサ層を形成することと、
前記第1のスペーサ層に隣接する第2のスペーサ層を形成することと、
前記フィンの側部領域を完全に垂直に露出させるように、前記第1のスペーサ層および前記第2のスペーサ層を後退させることと、
前記第1のスペーサ層に隣接する第3のスペーサ層であって、前記半導体基板上に形成された前記フィンを少なくとも部分的に覆う第3のスペーサ層を形成することと、
前記フィンの前記側部領域を部分的に垂直に露出させるように、前記第3のスペーサ層を後退させることと、
前記フィンの部分的に垂直に露出された前記側部領域上にソース/ドレイン材料をエピタキシャル成長させることと、
前記第1のスペーサ層および前記第3のスペーサ層に対して選択的な前記第2のスペーサ層をエッチングして、前記第1のスペーサ層と前記第3のスペーサ層との間にエアギャップを形成することと、
を含み、
前記ソース/ドレイン材料が、前記エッチング中にエッチャント材料に曝されない、方法。
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