JP7114291B2 - 光電変換素子の作製方法 - Google Patents
光電変換素子の作製方法 Download PDFInfo
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- JP7114291B2 JP7114291B2 JP2018054214A JP2018054214A JP7114291B2 JP 7114291 B2 JP7114291 B2 JP 7114291B2 JP 2018054214 A JP2018054214 A JP 2018054214A JP 2018054214 A JP2018054214 A JP 2018054214A JP 7114291 B2 JP7114291 B2 JP 7114291B2
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- photoelectric conversion
- hole injection
- selenium
- injection blocking
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Description
本実施の形態では、本発明の一態様である光電変換素子について、図面を参照して説明する。
本発明の一態様に係る光電変換素子10Aの断面構造の模式図を図1(A)に示す。光電変換素子10Aは、第1の電極11と、第1の電極11上の光電変換層13と、光電変換層13上の正孔注入阻止層17と、正孔注入阻止層17上の第2の電極15と、を有する。
以下に、本発明の一態様に係る光電変換素子の各要素について説明する。
光電変換層13について説明する。光電変換層13にセレン系材料を用いることができる。セレン系材料を用いた光電変換素子は、可視光に対する内部量子効率が高い特性を有する。当該光電変換素子では、アバランシェ現象による電荷増幅効果を用いて、入射光により生成されたキャリアの増幅を行うことにより光電変換効率を高めることができる。アバランシェ増倍効果を利用したフォトダイオードを、アバランシェフォトダイオード(APD:Avalanche Photodiode)と呼ぶ場合がある。
本発明の一態様に係る光電変換素子は、図1(A)乃至図1(C)に示すように、光電変換層13と第2の電極15との間に、正孔注入阻止層17を有する。正孔注入阻止層17は、第2の電極15から光電変換層13への正孔の注入を抑制する機能を有する。正孔注入阻止層17は、光電変換層13への電荷の注入を抑制する機能を有することから、電荷注入阻止層と呼ばれる場合がある。
本発明の一態様に係る光電変換素子は、図1(C)に示すように、第1の電極11と光電変換層13との間に、さらに電子注入阻止層19を有していてもよい。電子注入阻止層19は、第1の電極11から光電変換層13への電子の注入を抑制する機能を有する。電子注入阻止層19は、光電変換層13への電荷の注入を抑制する機能を有することから、電荷注入阻止層と呼ばれる場合がある。
第1の電極11について説明する。第1の電極11は、例えば、金、窒化チタン、モリブデン、タングステン、アルミニウム、チタンなどを用いることができる。また、例えば、アルミニウムをチタンで挟むような積層を用いることができる。第1の電極11は、スパッタ法やプラズマCVD法により形成することができる。なお、第1の電極11は、基板上に形成されてもよく、基板に形成された、または、基板上に形成された駆動用のトランジスタの上に形成されてもよい。
第2の電極15について説明する。第2の電極15は、例えば、インジウム錫酸化物(ITO)、シリコンを含むインジウム錫酸化物、亜鉛を含む酸化インジウム、酸化亜鉛、ガリウムを含む酸化亜鉛、アルミニウムを含む酸化亜鉛、酸化錫、フッ素を含む酸化錫、アンチモンを含む酸化錫、またはグラフェン等を用いることができるが、インジウム錫酸化物、シリコンを含むインジウム錫酸化物が特に好ましい。第2の電極15は単層に限らず、異なる膜の積層であっても良い。なお、インジウム錫酸化物は、InとSnとOとを有する。
本発明の一態様に係る光電変換素子10Bの作製方法について説明する。
本発明の一態様に係る光電変換素子10Bの別の作製方法について、図を用いて説明する。前述の光電変換素子の作製方法1とは、ステップS402の工程が異なる。
本実施の形態では、本発明の一態様を適用することのできる撮像装置の一例について、図面を参照して説明する。
本発明の一態様に係る撮像装置を用いることができる電子機器として、表示機器、パーソナルコンピュータ、記録媒体を備えた画像記憶装置または画像再生装置、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図16に示す。
各試料の構成、作製方法について、図17(A)及び図17(B)を用いて説明する。図17(A)及び図17(B)は、試料の作製方法を示す断面図である。
次に、試料A1乃至試料A6のSEM観察を行い、セレン層の膜剥がれ領域の有無を評価した。SEM観察には、日立ハイテクノロジーズ社製走査電子顕微鏡装置SU8030を用い、加速電圧は1.0kVとした。
各試料の構成、作製方法について、図5(A)乃至図5(E)に示す光電変換素子10Bに付記した符号を用いて説明する。
次に、試料B1乃至試料B5の電流-電圧特性を測定した。試料B1の電流-電圧特性を図27(A)、試料B2を図27(B)、試料B3を図28(A)、試料B4を図28(B)、試料B5を図29に示す。図27(A)、図27(B)、図28(A)、図28(B)及び図29において、横軸は対向電極間の電圧(Voltage)[V]を示し、縦軸は電流値(Current)[A]を示す。
次に、試料B3を集束イオンビーム(FIB:Focused Ion Beam)により薄片化し、試料B3の断面をSTEMで観察した。FIB加工には、SIIナノテクノロジー社製FIB-SEMダブルビーム装置XVision210DBを用い、加速電圧は30kV、照射イオンとしてガリウム(Ga)を用いた。STEM観察には、日立ハイテクノロジーズ社製走査透過電子顕微鏡HD-2700を用い、加速電圧は200kVとした。
試料C1の構成、作製方法について、図5(A)乃至図5(E)に示す光電変換素子10Bに付記した符号を用いて説明する。
試料C2の構成、作製方法について説明する。試料C2は、先に示す試料C1と光電変換層13の構成が異なる。それ以外の工程については、試料C1と同様とした。
次に、試料C1及び試料C2の電流-電圧特性を測定した。試料C1の電流-電圧特性を図35(A)、試料C2を図35(B)に示す。図35(A)及び図35(B)において、横軸は対向電極間の電圧(Voltage)[V]を示し、縦軸は電流値(Current)[A]を示す。
次に、試料B3及び試料C2の電流-電圧特性の測定温度依存を評価した。試料B3は、光電変換層に結晶セレンを用いた光電変換素子である。試料C2は、光電変換層に結晶セレンと、結晶セレン上の非晶質セレンとの積層構造を用いた光電変換素子である。
試料D1は、基板上に下地層として膜厚2nmの銀の膜を形成し、その後、膜厚500nmの非晶質セレン層を形成した。下地層と非晶質セレン層は、真空中で連続して成膜した。
試料D2は、基板上に膜厚500nmの非晶質セレン層を形成した。
次に、試料D1及び試料D2のX線光電子分光(XPS:X-ray Photoelectron Spectroscopy)測定を行った。
試料E1は、シリコンウェハとしてp型、面方位(100)のものを用いた。試料E2乃至試料E4は、ガラス基板として旭硝子社製ガラス基板AN100を用いた。
次に、試料E1のX線光電子分光(XPS:X-ray Photoelectron Spectroscopy)測定を行った。
次に、試料E1の紫外光電子分光法(UPS:Ultraviolet Photoelectron Spectroscopy)測定を行った。
次に、試料E2乃至試料E4の透過率及び反射率測定を行い、バンドギャップ(Eg)を算出した。試料E2の透過率及び反射率を図42(A)、試料E3を図42(B)、試料E4を図42(C)に示す。図42(A)、図42(B)及び図42(C)において、横軸は光の波長(Wavelength)[nm]を示し、縦軸は透過率(Transmittance)[%]及び反射率(Reflectance)[%]を示す。また、透過率を実線、反射率を破線で示す。
試料F1乃至試料F4の構成、作製方法について説明する。試料F1乃至試料F4は、先に示す試料B3と正孔注入阻止層17の構成が異なる。それ以外の工程については、試料B3と同様とした。
次に、試料F1乃至試料F4の電流-電圧特性を測定した。試料F1の電流-電圧特性を図44(A)、試料F2を図44(B)、試料F3を図45(A)、試料F4を図45(B)に示す。図44(A)、図44(B)、図45(A)及び図45(B)において、横軸は対向電極間の電圧(Voltage)[V]を示し、縦軸は電流値(Current)[A]を示す。
試料G1は、下地層43として銀の膜を2nm形成し、その後、非晶質セレン層45を300nm形成した。下地層43と非晶質セレン層45は、真空中で連続して成膜した。下地層43及び非晶質セレン層45の形成は、実施例1の記載を参照できるため、詳細を省略する。
次に、試料G1乃至試料G3および試料B3の電流-電圧特性を測定した。試料G1の電流-電界強度特性を図47(A)、試料G2を図47(B)、試料G3を図48(A)、試料B3を図48(B)に示す。図47(A)、図47(B)、図48(A)及び図48(B)において、横軸は電界強度[MV/cm]を示し、縦軸は電流値(Current)[A]を示す。なお、試料G1乃至試料G3、試料B3は、それぞれ光電変換層の膜厚が異なるため、図47(A)、図47(B)、図48(A)及び図48(B)は対向電極間の電圧を光電変換層膜厚で除した値(電界強度)を示している。
10B 光電変換素子
10C 光電変換素子
11 第1の電極
13 光電変換層
15 第2の電極
17 正孔注入阻止層
17a 正孔注入阻止層
17b 正孔注入阻止層
19 電子注入阻止層
41 層
43 下地層
43a 下地層
43b 下地層
45 非晶質セレン層
50 光電変換素子
51 トランジスタ
52 トランジスタ
53 トランジスタ
54 トランジスタ
56 電源
61 層
62 層
63 層
65 電極
66 光電変換部
66a 光電変換層
66b 正孔注入阻止層
67 電極
71 配線
72 配線
73 配線
75 配線
76 配線
77 配線
78 配線
79 配線
80 画素
81 画素アレイ
82 回路
83 回路
84 回路
85 回路
91 バックゲート
92 隔壁
93 絶縁層
200 シリコン基板
201 シリコン基板
202 シリコン基板
210 半導体層
220 絶縁層
300 絶縁層
310 遮光層
320 有機樹脂層
330 カラーフィルタ
330a カラーフィルタ
330b カラーフィルタ
330c カラーフィルタ
340 マイクロレンズアレイ
350 光学変換層
360 絶縁層
410 パッケージ基板
411 パッケージ基板
420 カバーガラス
421 レンズカバー
430 接着剤
435 レンズ
440 バンプ
441 ランド
450 イメージセンサチップ
451 イメージセンサチップ
460 電極パッド
461 電極パッド
470 ワイヤ
471 ワイヤ
490 ICチップ
911 筐体
912 表示部
919 カメラ
931 筐体
932 表示部
933 リストバンド
935 ボタン
936 竜頭
939 カメラ
951 筐体
952 レンズ
953 支持部
961 筐体
962 シャッターボタン
963 マイク
965 レンズ
967 発光部
971 筐体
972 筐体
973 表示部
974 操作キー
975 レンズ
976 接続部
981 筐体
982 表示部
983 操作ボタン
984 外部接続ポート
985 スピーカ
986 マイク
987 カメラ
1001 非晶質セレン層
1003 セレン化合物
1005 結晶粒
1005a 結晶粒
1007 結晶セレン層
1009 結晶粒
1011 結晶粒径
1061 基板
1063 下地層
1065 結晶セレン層
1067 非晶質セレン層
Claims (1)
- 第1の電極上に、元素Xを有する下地層を設ける工程と、
前記下地層上に、セレンを有する層を設ける工程と、
加熱処理を行う工程と、
前記セレンを有する層上に、スズ、ガリウム及び酸素を有する正孔注入阻止層を形成する工程と、
前記正孔注入阻止層上に、第2の電極を設ける工程と、を有し、
前記元素Xは、銀、ビスマス、インジウム、スズ又はテルルから選ばれる一以上であり、
前記加熱処理は、第1の工程乃至第6の工程に分けて処理され、
前記第1の工程は、室温から50℃以上90℃以下の第1の温度に昇温し、
前記第2の工程は、前記第1の温度を保持し、
前記第3の工程は、前記第1の温度より高く、かつ70℃以上170℃以下の第2の温度に昇温し、
前記第4の工程は、前記第2の温度を保持し、
前記第5の工程は、前記第2の温度より高く、かつ110℃以上220℃以下の第3の温度に昇温し、
前記第6の工程は、前記第3の温度を保持する、光電変換素子の作製方法。
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