JP7078272B2 - Transmitter, receiver, communication system, transmit method and receive method - Google Patents

Description

The present invention relates to a transmitting device, a receiving device, a communication system, a transmitting method and a receiving method, and more particularly to a technique for multiplexing and transmitting a signal.

The communication device uses a synchronization clock when performing time division multiplexing (TDM) communication or asynchronous transfer mode (ATM) communication. The synchronization clock is, for example, a DCS (Digital Clock Supply) clock. The synchronization clock is transmitted and received via the synchronization clock network.

On the other hand, Patent Document 1 discloses a technique of frequency-modulating a clock signal and transmitting control information. The receiving side can extract the control signal from the frequency of the modulated clock signal.

Japanese Unexamined Patent Publication No. 2010-68428

As described above, the synchronization clock network is a network for transmitting and receiving synchronization clocks. Therefore, the communication device could not send and receive control signals for control communication via the synchronization clock network.
When the method of Patent Document 1 is applied to the synchronization clock, the clock signal is frequency-modulated, so that the frequency is not the original frequency of the synchronization clock, and the receiving device connected to the synchronization clock network can extract the synchronization clock. There was a problem that it disappeared.

The present disclosure is for solving the above-mentioned problems, and is a transmitting device, a receiving device, and a transmitting device and a receiving device capable of superimposing a clock signal used for synchronization of data communication and a control signal for control communication. It is an object of the present invention to provide a communication system, a transmission method, and a reception method.

The transmission device according to the present disclosure is a clock generation means that generates a transmission side synchronization clock from a clock signal used for synchronization of data communication, and a control signal from control information for control communication based on the timing of the transmission side synchronization clock. It is provided with a signal generating means for generating the clock signal and a signal synthesizing means for synthesizing the signal levels of the clock signal and the control signal and transmitting the signal as a transmission signal.

The receiving device according to the present disclosure includes a signal separating means for separating the received signal into a clock signal used for synchronization of data communication and a control signal for control communication based on the signal level of the received signal, and the clock signal. It is provided with a clock generating means for generating a receiving side synchronous clock from the above, and a signal receiving means for acquiring control information from the control signal based on the timing of the receiving side synchronous clock.

The communication system according to the present disclosure is a clock generation means for generating a transmission side synchronization clock from a clock signal used for synchronization of data communication, and a control signal from control information for control communication based on the timing of the transmission side synchronization clock. A transmission device including a signal generation means for generating the clock signal and a signal synthesis means for synthesizing the signal levels of the clock signal and the control signal and transmitting the signal as a transmission signal, and the reception signal based on the signal level of the reception signal. The control from the control signal based on the signal separation means for separating the clock signal and the control signal, the clock generation means for generating the receiving side synchronous clock from the clock signal, and the timing of the receiving side synchronous clock. It includes a receiving device including a signal receiving means for acquiring information.

The transmission method according to the present disclosure generates a transmission side synchronization clock from a clock signal used for synchronization of data communication, and generates a control signal from control information for control communication based on the timing of the transmission side synchronization clock. The signal levels of the clock signal and the control signal are combined and transmitted.

The receiving method according to the present disclosure separates the received signal into a clock signal used for synchronization of data communication and a control signal for control communication based on the signal level of the received signal, and synchronizes the received signal with the receiving side. A clock is generated, and control information is acquired from the control signal based on the timing of the receiving side synchronization clock.

The present disclosure provides a transmission device, a reception device, a communication system, a transmission method, and a reception method capable of superimposing and transmitting / receiving a clock signal used for synchronization of data communication and a control signal for control communication. be able to.

It is a block diagram which shows the structure of the communication system which concerns on Embodiment 1. FIG. It is a block diagram which shows the structure of the transmission device which concerns on Embodiment 1. FIG. It is a block diagram which shows the structure of the receiving apparatus which concerns on Embodiment 1. FIG. It is a schematic diagram which shows the outline of the communication system which concerns on Embodiment 2. FIG. It is a block diagram which shows the structure of the transmission device which concerns on Embodiment 2. FIG. It is a timing chart at the time of transmitting the clock signal which concerns on Embodiment 2. It is a block diagram which shows the structure of the receiving apparatus which concerns on Embodiment 2. FIG. It is a timing chart at the time of receiving the clock signal which concerns on Embodiment 2.

<Examination of embodiments>
When controlling and monitoring communication devices, a monitoring network is provided separately from the synchronization clock network.
The surveillance network may be redundant in case of a failure. Under normal conditions, communication equipment is monitored and controlled by a normal monitoring network. In the event of a failure, communication equipment is monitored and controlled by a redundant monitoring network.

However, even if the monitoring network is redundant, both systems may be in a failed state. In such a case, the monitoring network cannot access the communication device, and the control of the communication device may be isolated. Further, if a failure occurs in the communication system of the main signal, the communication device falls into a state where it cannot be recovered remotely. In order to solve this situation, it was necessary to remotely control the communication device using some kind of physical wiring other than the monitoring network.

A method is conceivable in which a DCS clock wiring is used as wiring other than the monitoring network, and a pulse signal for a control signal is superimposed on a trivalent signal of the DCS clock. However, when this method is used, there is a problem that the timing of the essential DCS clock is disrupted and the DCS clock wiring cannot be used for transmitting the synchronization clock.

<Embodiment 1>
FIG. 1 is a configuration diagram showing a configuration of a communication system 300 according to the present embodiment. The transmission device 100 transmits a clock signal used for synchronization of data communication and a control signal for control communication to the reception device 200 via the network 400. The network 400 is, for example, a synchronization clock network.

FIG. 2 is a configuration diagram showing the configuration of the transmission device 100 of the present embodiment.
The transmission device 100 includes a clock generation unit 101, a signal generation unit 102, and a signal synthesis unit 103.
The clock generation unit 101 generates a transmission side synchronization clock from a clock signal used for synchronization of data communication. The clock signal is, for example, a DCS clock.
The signal generation unit 102 generates a control signal from the control information for control communication based on the timing of the transmission side synchronization clock.
The signal synthesis unit 103 synthesizes the signal levels of the control signal and the clock signal to generate a composite signal, and transmits the combined signal to the receiving device.

FIG. 3 is a configuration diagram showing the configuration of the receiving device 200 according to the present embodiment.
The receiving device 200 includes a signal separating unit 201, a clock generating unit 202, and a signal receiving unit 203.
The signal separation unit 201 separates the received signal into a control signal and a clock signal. The signal separation unit 201 generates a clock signal and a control signal by classifying the signal levels of the received signals.

The clock generation unit 202 generates a receiving side synchronous clock from the clock signal generated by the signal separation unit 201.
The signal receiving unit 203 acquires control information by reading the control signal based on the timing of the receiving side synchronization clock.

According to the present embodiment, the transmission device 100 synthesizes and transmits the signal levels of the clock signal and the control signal based on the timing of the clock. Therefore, the transmission device 100 can superimpose and transmit the clock signal used for synchronization of data communication and the control signal for control communication.
Further, the receiving device 200 separates the clock signal and the control signal based on the signal level. Then, the receiving device 200 generates a synchronous clock and acquires control information from the control signal based on the timing of the synchronous clock. Therefore, the receiving device 200 can generate a synchronization clock from the received signal and acquire control information.

According to the present embodiment, the communication system 300 synthesizes and transmits the signal levels of the clock signal and the control signal based on the timing of the clock, and separates the clock signal and the control signal based on the signal level of the received signal. , Acquires control information from the control signal based on the timing of the synchronous clock. Therefore, the communication system 300 can transmit and receive the clock signal used for synchronization of data communication and the control signal for control communication in an superimposed manner.

<Embodiment 2>
In the present embodiment, in the DCS clock used as a synchronization clock for performing TDM communication or ATM communication, any pulse within the threshold level for recognizing the positive / medium / negative logic of the ternary signal of the DCS clock pulse. A signal is input and transmitted. The DCS clock can not only transmit timing information as a synchronization clock, but also transmit an arbitrary signal.

FIG. 4 is a schematic diagram showing an outline of the communication system according to the present embodiment.
The transmitting device 100 and the receiving device 200 are connected to each other via the network 400. The monitoring server 501 controls and monitors the receiving device 200 via the monitoring network 502.
The transmitting device 100 includes a signal output unit 16 that outputs a signal to the receiving device 200.
The receiving device 200 includes a signal input unit 19 and a monitoring network port 503. The signal input unit 19 receives the signal transmitted by the transmission device 100. The monitoring network port 503 receives a control signal from the monitoring server.

Normally, the transmitting device 100 transmits a clock signal to the receiving device 200. The monitoring server 501 performs monitoring control of the receiving device 200 via the monitoring network 502.
When a failure occurs in the monitoring network 502, the transmission device 100 continues the monitoring control by transmitting the control signal using the network 400 which is the wiring for transmitting the clock signal.
The receiving device 200 operates according to the received control signal. The operation content is arbitrary, and may be, for example, an operation such as shutting down, restarting, or communicating with another device.

FIG. 5 is a configuration diagram showing the configuration of the transmission device 100 of the present embodiment. The arrows simply indicate the direction of the flow of a signal and do not exclude interactivity. The transmitting device 100 outputs a signal to the receiving device 200.
The DCS clock source 1 is a clock signal. The DCS clock source 1 is input to the clock delay unit 5 and the clock generation unit 7.
The clock delay unit 5 delays the DCS clock source 1.
The clock generation unit 7 extracts the timing of the 8k clock of the DCS clock source 1 and generates the 8kHz clock 8.

The 8 kHz clock 8 is distributed to the signal generation unit 6 and the N multiplication unit 9. The N multiplication unit 9 multiplies the 8 kHz clock 8 by N. The multiplication factor N is arbitrary, but in the present embodiment, the case where the multiplication factor is 16 will be described.
The N multiplication unit 9 multiplies the 8 kHz clock 8 by 16 to generate a 128 kHz clock 10, and outputs the 128 kHz clock 10 to the signal generation unit 6.

The control signal conversion unit 3 converts an arbitrary control signal 2 for controlling the opposite device (reception device 200) into signal pulse information 4 and transmits it to the signal generation unit 6.
The signal generation unit 6 receives the signal pulse information 4 which is an arbitrary control signal, generates a signal pulse 13 using the clock timings of the 8 kHz clock 8 and the 128 kHz clock 10, and outputs the signal pulse information 14 to the signal synthesis unit 14.
The DCS clock 12 generated by the clock delay unit 5 is input to the signal synthesis unit 14. The signal synthesis unit 14 generates the DCS clock control signal 15 and outputs it to the signal output unit 16.
The signal output unit 16 outputs the DCS clock control signal 17 to the external device (reception device 200).

The operation of the transmission device will be described with reference to FIGS. 5 and 6.
FIG. 6 is a timing chart showing a series of operations when a control signal is input to the DCS clock on the transmitting side. In the timing chart, signal and clock processing and transmission delay are omitted. The timing chart shows a state in which the transmission delay and the like are optimized by the clock delay unit 5.

From the DCS clock source 1 shown in FIG. 5, an 8k clock synchronized with the DCS clock source 1 can be generated. This is a known technique and will be omitted here. The clock generation unit 7 is a mechanism for generating an 8 kHz clock 8.
The waveform of the DCS clock source 1 and the waveform of the 8 kHz clock 8 are shown in FIG.
The DCS clock source 1 is a ternary signal and has a frequency of 64 kHz.

In FIG. 5, the 8 kHz clock 8 generated from the clock generation unit 7 is sent to the N multiplication unit 9. The N multiplication unit 9 simply multiplies the 8 kHz clock 8 by 16 to generate the 128 kHz clock 10. The N multiplication unit 9 is multiplied by 16 in this paper, but the multiplication number is arbitrary and can be changed depending on the number of pulses of the control signal to be exchanged.
A control signal can be sent within a time of 1/8 kHz = 125 us from the rising timing of the 8 kHz clock 8 to the next rising timing. When the multiplication factor is 16, the number of pulses of the control signal that can be transmitted is the number of pulses of the 128 kHz clock 10 generated by the N multiplication unit 9. Therefore, since the pulse width of the 128 kHz clock 10 is 1/128 kHz = 7.8125 us, the control signal for 16 pulses can be sent from 125 us / 7.8125 us = 16. It is possible to send and receive a larger number of pulses by increasing the multiplication factor.
The waveform of the 128 kHz clock 10 is shown in FIG. The 128 kHz clock is an 8 kHz clock 8 multiplied by 16.

In FIG. 5, an arbitrary control signal 2 that controls the opposite device (reception device) is sent to the control signal conversion unit 3 and converted into 16-bit signal pulse information 4. Further, the signal pulse information 4 is transmitted to the signal generation unit 6. Since the interface differs depending on the architect of the device, the control signal conversion unit 3 arbitrarily generates signal pulse information 4 from the control signal 2 according to the device architect. In this description, the control interface in the device is not specified. The signal pulse information 4 is information for 16 pulses and is input to the signal generation unit 6.
An example of signal pulse information 4 is shown in FIG.

In FIG. 5, the signal generation unit 6 synchronizes the first pulse with the rising timing of the 8 kHz clock 8, and in the order of the first pulse, the second pulse, and the third pulse at the rising timing of the 128 kHz clock 10. The signal pulse 13 is generated from the signal pulse information 4.
The waveform of the signal pulse 13 is shown in FIG. In FIG. 6, the generation of the signal pulse 13 is started from the rising timing of the 8 kHz clock 8. Further, signal pulse information is generated bit by bit at the rising timing of the 128 kHz clock 10.

In FIG. 5, the clock delay unit 5 receives the DCS clock source 1, delays it by a predetermined delay time, and outputs it as the DCS clock 12. The delay time is the time required for the DCS clock source 1 to pass through the clock generation unit 7 and be extracted as an 8 kHz clock 8, the signal generation unit 6 to generate the signal pulse 13, and the signal pulse 13 to enter the signal synthesis unit 14. be.
Since the DCS clock source 1 and the DCS clock 12 differ only in the delay time, they have the same waveform in FIG.

As shown in FIG. 5, the signal synthesis unit 14 synthesizes the DCS clock 12 and the signal pulse 13. The signal pulse 13 needs to be generated at a level lower than the electrical threshold for discriminating the DCS clock 30. The electrical threshold is used when the DCS clock 30 and the signal pulse 23 are separated in the signal separation unit 21 of FIG.
The waveform of the DCS clock control signal 15 is shown in FIG. The signal level of the DCS clock control signal 15 is the sum of the signal level of the DCS clock 12 and the signal pulse 13. The hatched portion of the DCS clock control signal 15 indicates a portion changing from the DCS clock 12. Since the signal levels are combined, the magnitudes of V1 and V2 in FIG. 6 are the same.

When the DCS clock control signal 15 is to be output to the outside of the device, the DCS clock control signal 15 is placed on a medium such as a cable and transmitted as the DCS clock control signal 17 via the signal output unit 16.

FIG. 7 is a configuration diagram showing the configuration of the receiving device 200 according to the present embodiment. The arrows simply indicate the direction of the flow of a signal and do not exclude interactivity. The receiving device 200 is the side on which the transmitting device 100 inputs a signal.
The DCS clock control signal 17 output in FIG. 5 is output as a DCS clock control signal 18 to the opposite device (reception device 200) via a medium such as a cable. The DCS clock control signal 18 is input to the signal input unit 19. The DCS clock control signal 20 output by the signal input unit 19 is input to the signal separation unit 21.

The signal separation unit 21 separates the DCS clock control signal 20 into a DCS clock 30 and a signal pulse 23 based on the electrical level threshold value of the signal.
The clock generation unit 31 extracts the 8 kHz clock 22 from the DCS clock 30. The 8 kHz clock 22 is used as a synchronization clock in the device. Further, the 8 kHz clock 22 is sent to the signal receiving unit 26 and the N multiplication unit 27.
The signal pulse 23 is sent to the clock delay unit 24.

The N multiplication unit 27 multiplies the 8 kHz clock 22 by 16 to generate a 128 kHz clock 28, and outputs the 128 kHz clock 28 to the signal reception unit 26.
The clock delay unit 24 delays the signal pulse 23 and transmits the signal pulse 25 to the signal reception unit 26.
The signal receiving unit 26 extracts the signal pulse information 29 from the signal pulse 25 using the timing of the 128 kHz clock 28 and the 8 kHz clock 22, and transmits the signal pulse information 29 to the control signal conversion unit 32.
The control signal conversion unit 32 generates an arbitrary control signal 33 that controls the device from the signal pulse information 29, and outputs the control signal 33 to the device.

The operation of the receiving unit will be described with reference to FIGS. 7 and 8.
FIG. 8 is a timing chart showing a series of operations when a control signal is detected from a clock signal. Similar to FIG. 6, in the timing chart, signal and clock processing and transmission delay are omitted. The timing chart shows a state in which the transmission delay and the like are optimized by the clock delay unit.

The DCS clock control signal 17 output in FIG. 5 is input to the signal input unit 19 of the opposite device (reception device 200) as the DCS clock control signal 18 via a medium such as a cable. The signal input unit 19 outputs the DCS clock control signal 20.
The DCS clock control signal 20 is separated into a DCS clock 30 and a signal pulse 23 by the signal separation unit 21. At this time, the guideline of the electric threshold value for discriminating the DCS clock is about half of the input standard of the DCS clock, and the pulse of the DCS clock is discriminated. Further, it is essential that the guideline of the electric threshold value for discriminating the signal pulse is lower than the electric threshold value for discriminating the DCS clock. The specific value for designing each electrical threshold is arbitrary.

The operation of the signal separation unit 21 will be described with reference to FIG.
The DCS clock control signal 20 is separated into a DCS clock 30 and a signal pulse 23 using a threshold value. The thresholds are the DCS clock threshold 1 and the DCS clock threshold 2 for discriminating the three-value signal level of the DCS signal, and the control signal threshold 1, the control signal threshold 2, and the control signal threshold 3 for discriminating the binary signal level of the control signal. Is.
The DCS clock control signal 20 is separated into a DCS clock 30 and a signal pulse 23 based on the determination criteria shown below.

When the clock signal exceeds the control signal threshold value 1, it is determined that DCS clock High / control signal High. For example, A1 is classified into DCS clock High / control signal High.
When the clock signal does not exceed the control signal threshold value 1 and the DCS clock threshold value is 1 or more, it is determined that the DCS clock is High / the control signal is Low. For example, A2 is classified into DCS clock High / control signal Low.
When the clock signal does not exceed the DCS clock threshold value 1 and the control signal threshold value is 2 or more, it is determined that the DCS clock is Middle / control signal High. For example, A3 is classified into DCS clock Middle / control signal High.
When the clock signal does not exceed the control signal threshold value 2 and the DCS clock threshold value is 2 or more, it is determined that the DCS clock is Middle / control signal Low. For example, A4 is classified into DCS clock Middle / control signal Low.
When the clock signal does not exceed the DCS clock threshold value 2 and the control signal threshold value is 3 or more, it is determined that the DCS clock is Low / control signal High. For example, A5 is classified into DCS clock Low / control signal High.
If the clock signal does not exceed the control signal threshold value 3, it is determined to be DCS clock Low / control signal Low. For example, A6 is classified into DCS clock Low / control signal Low.

In FIG. 7, the separated DCS clock 30 passes through the clock generation unit 31 and extracts the 8 kHz clock 22 in the same manner as the clock generation unit 7 of FIG. The 8 kHz clock 22 is sent to the signal receiving unit 26 and the N multiplication unit 27 while being used as a synchronization clock of the device.
The waveforms of the DCS clock 30 and the 8 kHz clock 22 are shown in FIG.

In FIG. 7, the multiplication factor in the N multiplication unit 27 needs to be the same multiplication number as the N multiplication unit 9 in FIG. The multiplied 128 kHz clock 28 is sent to the signal receiving unit 26. This multiplication factor is arbitrary as in FIG.
The waveform of the 128 kHz clock 28 is shown in FIG.

The clock delay unit 24 delays the received signal pulse 23 and outputs it as a signal pulse 25.
The delay time is the delay time until the DCS clock 30 is extracted as the 8 kHz clock 22 by the clock generation unit 31, the 128 kHz clock 28 is generated via the N multiplication unit 27, and is input to the signal reception unit 26. , 7.8125us / 2 = 3.90625us for a half pulse of 128 kHz (in the case of 16 multiplication this time) is added.
In FIG. 8, the signal pulse 25 is delayed by half a cycle of the 128 kHz clock as compared with the signal pulse 23.

In FIG. 7, the signal receiving unit 26 identifies the rising edge of the 128 kHz clock 28 as the first pulse, the second pulse, and the third pulse for the signal pulse 25, with the rising edge of the 8 kHz clock 22 as the first pulse. The signal receiving unit 26 transmits 16 pulses from the rising edge of the 8 kHz clock 22 to the next rising edge as signal pulse information 29 to the control signal conversion unit 32.
As shown in FIG. 8, the acquisition of the signal pulse information 29 starts from the rising edge of the 8 kHz clock 22. Further, each bit of the signal pulse information 29 is acquired corresponding to the rising edge of the 128 kHz clock.

In FIG. 7, the control signal conversion unit 32 converts the signal pulse information 29 into the control signal 33 and sends it to the device. The control signal 33 that controls the device differs depending on the interface of the device. The signal conversion in the control signal conversion unit 32 is arbitrarily designed according to the device architect, and the control signal 33 is generated.

According to the present embodiment, an electric signal pulse having a level smaller than the electric signal threshold level determined as the synchronization clock is inserted into the clock signal. The mechanism for extracting the timing as a clock signal and the mechanism for determining the control pulse as a control signal are separated, and it is possible to transmit and receive the control signal while using the clock.
In addition, in order to enable transmission of an arbitrary signal, a plurality of signal patterns that can be understood by the communication device may be determined in advance. By interpreting the signal pattern and understanding its meaning, the communication device can perform processing such as resumption. Therefore, it is possible to remotely control the communication device without using the monitoring network. In addition, since the signal is physically transmitted using a medium such as a cable used for the synchronization clock, no work such as laying another physical wiring is required in order to use this embodiment. ..

In this embodiment, the control signal of the device can be superimposed and transmitted in the existing DCS clock interface. Therefore, the control signal generated by the transmitting side device can be understood by the opposite device and the device can be controlled.
Further, since the existing interface is physically used, there is no need to perform new wiring for controlling the device, so that there is an advantage that the cost of physical wiring work is not required.
Furthermore, since the amount of information in the control signal can be arbitrarily determined by multiplying the 8 kHz clock, even if the amount of information to be controlled by the device increases, it is possible to flexibly design the circuit according to the amount. ..

By using this embodiment, when the monitoring network system of the device goes down and the device becomes remotely uncontrollable, the device can be used without going to the place where the device is installed, such as an operation station. It becomes possible to perform control.
It is also possible to monitor the life and death of the DCS interface by transmitting and receiving control signals on a regular basis. For example, the communication device can shift the DCS clock source to another synchronization clock source when it receives an unexpected control signal. In such a case, the device will not be synchronized with the synchronous network, and it will be possible to prevent the occurrence of communication failure due to asynchronous.

The present invention is not limited to the above embodiment, and can be appropriately modified without departing from the spirit.

Some or all of the above embodiments may also be described, but not limited to:

(Appendix 1)
A clock generation means that generates a transmitter synchronization clock from a clock signal used for data communication synchronization,
A signal generation means for generating a control signal from control information for control communication based on the timing of the transmission side synchronization clock, and
A signal synthesizing means for synthesizing the signal levels of the clock signal and the control signal and transmitting the signal as a transmission signal.
A transmitter equipped with.

(Appendix 2)
The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The transmitter according to Appendix 1.

(Appendix 3)
The transmission device further comprises a multiplication means for generating a transmission side multiplication clock obtained by multiplying the transmission side synchronization clock.
The signal generating means generates the control signal based on the timing of the transmitting side multiplication clock.
The transmitter according to any one of Supplementary note 1 or 2.

(Appendix 4)
The transmitting device according to Appendix 3, wherein the control information is information having a bit or less of the multiplication number.

(Appendix 5)
The transmission device according to any one of Supplementary note 1 to 4, wherein the clock signal is a multi-valued signal having three or more signal levels.

(Appendix 6)
A signal separation means for separating the received signal into a clock signal used for synchronization of data communication and a control signal for control communication based on the signal level of the received signal.
A clock generation means for generating a receiving side synchronous clock from the clock signal,
A signal receiving means for acquiring control information from the control signal based on the timing of the receiving side synchronization clock, and
A receiver equipped with.

(Appendix 7)
The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The receiving device according to Appendix 6.

(Appendix 8)
A clock generation means that generates a transmitter synchronization clock from a clock signal used for data communication synchronization,
A signal generation means for generating a control signal from control information for control communication based on the timing of the transmission side synchronization clock, and
A signal synthesizing means for synthesizing the signal levels of the clock signal and the control signal and transmitting the signal as a transmission signal.
With a transmitter and
A signal separation means for separating the received signal into the clock signal and the control signal based on the signal level of the received signal.
A clock generation means for generating a receiving side synchronous clock from the clock signal,
A signal receiving means for acquiring the control information from the control signal based on the timing of the receiving side synchronization clock, and
With a receiver and
Communication system with.

(Appendix 9)
The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The communication system according to Appendix 8.

(Appendix 10)
Generates a sender synchronization clock from the clock signal used to synchronize data communication,
A control signal is generated from the control information for control communication based on the timing of the transmission side synchronization clock.
The signal levels of the clock signal and the control signal are combined and transmitted.
Sending method.

(Appendix 11)
The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The transmission method according to Appendix 10.

(Appendix 12)
Based on the signal level of the received signal, the received signal is separated into a clock signal used for synchronization of data communication and a control signal for control communication.
A receiving side synchronization clock is generated from the clock signal, and the receiving side synchronization clock is generated.
Obtaining control information from the control signal based on the timing of the receiving side synchronization clock.
Receiving method.

(Appendix 13)
The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The receiving method according to Appendix 12.

1 DCS clock source 2, 33 Control signal 3, 32 Control signal converter 4, 29 Signal pulse information 5, 24 Clock delay 6, 102 Signal generator 8, 22 8 kHz clock 9, 27 N multiplication unit 10, 28 128 kHz clock 12, 30 DCS clock 13, 23, 25 signal pulse 14, 103 signal synthesizer 15, 17, 18, 20 DCS clock control signal 16 signal output unit 19 signal input unit 21, 201 signal separation unit 26, 203 signal receiver 7 , 31, 101, 202 Clock generator 100 Transmitter 200 Receiver 300 Communication system 400 Network 501 Monitoring server 502 Monitoring network 503 Monitoring network port

Claims (10)

A clock generation means that generates a transmitter synchronization clock from a clock signal used for data communication synchronization,
A signal generation means for generating a control signal from control information for control communication based on the timing of the transmission side synchronization clock, and
A signal synthesizing means that synthesizes the signal levels of the clock signal and the control signal and transmits them as a transmission signal to a synchronization clock network that is a transmission path of a DCS (Digital Clock Supply) clock .
A transmitter equipped with. The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The transmitter according to claim 1. The transmission device further comprises a multiplication means for generating a transmission side multiplication clock obtained by multiplying the transmission side synchronization clock.
The signal generating means generates the control signal based on the timing of the transmitting side multiplication clock.
The transmitter according to any one of claims 1 or 2. The transmission device according to claim 3, wherein the control information is information having a bit or less of the multiplication number. The transmission device according to any one of claims 1 to 4, wherein the clock signal is a multi-valued signal having three or more signal levels. Based on the signal level of the received signal received from the synchronization clock network which is the transmission path of the DCS (Digital Clock Supply) clock, the clock signal used for synchronizing the data communication and the control signal for control communication Signal separation means to separate into
A clock generation means for generating a receiving side synchronous clock from the clock signal,
A signal receiving means for acquiring control information from the control signal based on the timing of the receiving side synchronization clock, and
A receiver equipped with. The signal level of the control signal is smaller than the threshold value used for determining the logic level of the clock signal.
The receiving device according to claim 6. A clock generation means that generates a transmitter synchronization clock from a clock signal used for data communication synchronization,
A signal generation means for generating a control signal from control information for control communication based on the timing of the transmission side synchronization clock, and
A signal synthesizing means that synthesizes the signal levels of the clock signal and the control signal and transmits them as a transmission signal to a synchronization clock network that is a transmission path of a DCS (Digital Clock Supply) clock .
With a transmitter and
A signal separation means for separating the received signal into the clock signal and the control signal based on the signal level of the received signal received from the synchronization clock network.
A clock generation means for generating a receiving side synchronous clock from the clock signal,
A signal receiving means for acquiring the control information from the control signal based on the timing of the receiving side synchronization clock, and
With a receiver and
Communication system with. Generates a sender synchronization clock from the clock signal used to synchronize data communication,
A control signal is generated from the control information for control communication based on the timing of the transmission side synchronization clock.
The signal levels of the clock signal and the control signal are combined and transmitted to a synchronization clock network which is a transmission path of a DCS (Digital Clock Supply) clock .
Sending method. Based on the signal level of the received signal received from the synchronization clock network which is the transmission path of the DCS (Digital Clock Supply) clock, the clock signal used for synchronizing the data communication and the control signal for control communication Separated into
A receiving side synchronization clock is generated from the clock signal, and the receiving side synchronization clock is generated.
Obtaining control information from the control signal based on the timing of the receiving side synchronization clock.
Receiving method.

Images