JP7032951B2

JP7032951B2 - Op amp

Info

Publication number: JP7032951B2
Application number: JP2018027621A
Authority: JP
Inventors: 敦北島
Original assignee: 日清紡マイクロデバイス株式会社
Priority date: 2018-02-20
Filing date: 2018-02-20
Publication date: 2022-03-09
Anticipated expiration: 2038-02-20
Also published as: JP2019145976A

Description

本発明は差動入力端子間の電圧を電流信号で出力する電流センス回路として好適な演算増幅器に関する。 The present invention relates to an operational amplifier suitable as a current sense circuit that outputs a voltage between differential input terminals as a current signal.

図４に、モータ、インバータその他の測定対象物に流れる電流を検出する電流センス回路として機能する演算増幅器１０Ｄを示す。測定対象物２０は電圧源２１の電圧Ｖａで動作し検出抵抗Ｒｓが直列接続される。検出抵抗Ｒｓにはそこを流れる電流Ｉｓによって電圧Ｖｓが発生する。演算増幅器１０Ｄはこの電圧Ｖｓを入力抵抗Ｒｉｎを介在して取り込み、入力抵抗Ｒｉｎに流れる電流を内部で制御して出力電流Ｉｏｕｔとして出力する。 FIG. 4 shows an operational amplifier 10D that functions as a current sense circuit that detects a current flowing through a motor, an inverter, or other object to be measured. The measurement object 20 operates at the voltage Va of the voltage source 21, and the detection resistors Rs are connected in series. A voltage Vs is generated in the detection resistor Rs by the current Is flowing therethrough. The operational amplifier 10D takes in this voltage Vs via the input resistance Rin, internally controls the current flowing through the input resistance Rin, and outputs it as an output current Iout.

演算増幅器１０Ｄにおいて、１１は反転入力端子、１２は非反転入力端子、１３は出力端子、１４は電源端子、１５は接地ＧＮＤに接続される接地端子、１６は電圧Ｖ２の内部電圧源、１７は内部基準電圧ライン、１８は経路である。ＮＰＮトランジスタＱｎ１，Ｑｎ２、抵抗Ｒ１，Ｒ２、電流源Ｉ１は折返しカスコード回路型差動増幅回路の入力段の差動回路を構成する。ＰＮＰトランジスタＱｐ３、抵抗Ｒ３、電流源Ｉ２は、バイアス回路を構成する。ＰＮＰトランジスタＱｐ１，Ｑｐ２はそのバイアス回路でベースバイアスされるベース接地回路、ＮＰＮトランジスタＱｎ３，Ｑｎ４と抵抗Ｒ４，Ｒ５はベース接地回路の能動負荷としてのカレントミラー回路であり、これらベース接地回路とカレントミラー回路は折返しカスコード回路型差動増幅回路の出力段を構成する。ＰＮＰトランジスタＱｐ４、ＮＰＮトランジスタＱｎ５，Ｑｎ６、抵抗Ｒ６、電流源Ｉ３，Ｉ４は電圧出力回路を構成する。位相補償容量Ｃ１は、トランジスタＱｐ２のコレクタのノードＡとトランジスタＱｎ６のコレクタのノードＢとの間に接続されている。ＰＮＰトランジスタＱｐ５，Ｑｐ６と抵抗Ｒ７，Ｒ８は、入力抵抗Ｒｉｎから経路１８を経由して流れる電流を電圧増幅回路によって制御して出力電流Ｉｏｕｔとして出力する電流出力回路を構成する。Ｒｏｕｔは出力抵抗である。そして、この演算増幅器１０Ｄは電源端子１４の電圧Ｖ１と内部基準電圧ライン１７の電圧Ｖ２ａの差分、つまり内部電圧源１６の電圧Ｖ２によって動作する。位相補償容量と電流出力端子をもつ演算増幅器に類似の演算増幅器としては、特許文献１に記載がある。 In the operational amplifier 10D, 11 is an inverting input terminal, 12 is a non-inverting input terminal, 13 is an output terminal, 14 is a power supply terminal, 15 is a ground terminal connected to a ground GND, 16 is an internal voltage source of voltage V2, and 17 is. The internal reference voltage line, 18 is a path. The NPN transistors Qn1, Qn2, resistors R1 and R2, and current source I1 form a differential circuit at the input stage of a folded cascode circuit type differential amplifier circuit. The PNP transistor Qp3, the resistor R3, and the current source I2 form a bias circuit. The PNP transistors Qp1 and Qp2 are base ground circuits that are base biased by the bias circuit, and the NPN transistors Qn3 and Qn4 and resistors R4 and R5 are current mirror circuits as active loads of the base ground circuit, and these base ground circuits and current mirrors. The circuit constitutes an output stage of a folded cascode circuit type differential amplification circuit. The PNP transistor Qp4, the NPN transistor Qn5, Qn6, the resistance R6, and the current sources I3 and I4 form a voltage output circuit. The phase compensation capacitance C1 is connected between the collector node A of the transistor Qp2 and the collector node B of the transistor Qn6. The PNP transistors Qp5 and Qp6 and the resistors R7 and R8 form a current output circuit in which the current flowing from the input resistor Rin via the path 18 is controlled by a voltage amplifier circuit and output as an output current Iout. Rout is an output resistance. The operational amplifier 10D operates by the difference between the voltage V1 of the power supply terminal 14 and the voltage V2a of the internal reference voltage line 17, that is, the voltage V2 of the internal voltage source 16. Patent Document 1 describes an operational amplifier similar to an operational amplifier having a phase compensation capacity and a current output terminal.

特開昭６３－３０９０１４号公報Japanese Unexamined Patent Publication No. 63-309014

ここで、演算増幅器１０Ｄの使用条件が入力端子１１に３６Ｖの電圧まで印加される条件である場合において、電圧源３０の電圧Ｖ１が３６Ｖであるとする。この場合は各素子には耐圧が４０Ｖのものが使用される。そして、この電圧源３０の電圧Ｖ１の変動の影響を防止するために、電源端子１４と内部基準電圧ライン１７との間に電圧源１６によって電圧Ｖ２が印加される。この電圧源１６の電圧Ｖ２は例えば４Ｖである。この結果、この演算増幅器１０Ｄの内部基準電圧ライン１７に加わる電圧Ｖ２ａは、
Ｖ２ａ＝Ｖ１－Ｖ２
＝３６－４＝３２（Ｖ）（１）
となる。 Here, it is assumed that the voltage V1 of the voltage source 30 is 36V when the usage condition of the operational amplifier 10D is a condition in which a voltage of up to 36V is applied to the input terminal 11. In this case, each element has a withstand voltage of 40 V. Then, in order to prevent the influence of the fluctuation of the voltage V1 of the voltage source 30, the voltage V2 is applied between the power supply terminal 14 and the internal reference voltage line 17 by the voltage source 16. The voltage V2 of this voltage source 16 is, for example, 4V. As a result, the voltage V2a applied to the internal reference voltage line 17 of the operational amplifier 10D becomes
V2a = V1-V2
= 36-4 = 32 (V) (1)
Will be.

よって、このときのトランジスタＱｐ４のベース・エミッタ間電圧をＶｂｅ（Ｑｐ４）、トランジスタＱｎ５のベース・エミッタ間電圧をＶｂｅ（Ｑｎ５）、トランジスタＱｎ６のベース・エミッタ間電圧をＶｂｅ（Ｑｎ６）とし、それらを０．７（Ｖ）とすれば、位相補償容量Ｃ１のノードＡの電圧ＶＡは、
ＶＡ＝Ｖ２ａ＋Ｖｂｅ（Ｑｎ５）＋Ｖｂｅ（Ｑｎ６）－Ｖｂｅ（Ｑｐ４）
＝３２＋０．７＋０．７－０．７＝３２．７
≒３２（Ｖ）（２）
となる。 Therefore, the base-emitter voltage of the transistor Qp4 at this time is Vbe (Qp4), the base-emitter voltage of the transistor Qn5 is Vbe (Qn5), and the base-emitter voltage of the transistor Qn6 is Vbe (Qn6). If it is 0.7 (V), the voltage VA of the node A of the phase compensation capacitance C1 is
VA = V2a + Vbe (Qn5) + Vbe (Qn6) -Vbe (Qp4)
= 32 + 0.7 + 0.7-0.7 = 32.7
≒ 32 (V) (2)
Will be.

次に、入力端子１１が接地ＧＮＤに短絡した場合を考える。この場合、演算増幅器１０Ｄの内部基準電圧ライン１７の電圧Ｖ２ａは０（Ｖ）ではなく、式（１）のように３２（Ｖ）であるために、太線で示す経路で内部基準電圧ライン１７から、抵抗Ｒ６、トランジスタＱｎ６のベース・コレクタ間のＰＮ接合部、抵抗Ｒ７、トランジスタＱｐ６のコレクタ・ベースのＰＮ接合部、抵抗Ｒ８、経路１８を経由して、入力端子１１から接地ＧＮＤに短絡電流が流れる。このため、ノードＢの電圧ＶＢは、トランジスタＱｎ６のコレクタ・ベースのＰＮ接合部の電圧をＶｃｂ（Ｑｎ６）、トランジスタＱｐ６のコレクタ・ベースのＰＮ接合部の電圧をＶｃｂ（Ｑｐ６）とすれば、
ＶＢ＝[（Ｖ２ａ－Ｖｃｂ（Ｑｎ６）－Ｖｃｂ（Ｑｐ６）]×（Ｒ７＋Ｒ８）／
[（Ｒ６＋Ｒ７＋Ｒ８)]＋Ｖｃｂ（Ｑｐ６）≒８（Ｖ）（３）
程度となる。ただし、Ｖｃｂ（Ｑｎ６）＝Ｖｃｂ（Ｑｐ６）＝０．７（Ｖ）、Ｒ６＝１０（ｋΩ）、Ｒ７＝３（ｋΩ）、Ｒ８＝０．２（ｋΩ）である。 Next, consider the case where the input terminal 11 is short-circuited to the ground GND. In this case, since the voltage V2a of the internal reference voltage line 17 of the arithmetic amplifier 10D is not 0 (V) but 32 (V) as in the equation (1), the path shown by the thick line is from the internal reference voltage line 17. A short-circuit current flows from the input terminal 11 to the ground GND via the resistor R6, the PN junction between the base and collector of the transistor Qn6, the resistor R7, the PN junction of the collector base of the transistor Qp6, the resistor R8, and the path 18. It flows. Therefore, for the voltage VB of the node B, if the voltage of the collector-based PN junction of the transistor Qn6 is Vcb (Qn6) and the voltage of the collector-based PN junction of the transistor Qp6 is Vcb (Qp6).
VB = [(V2a-Vcb (Qn6) -Vcb (Qp6)] × (R7 + R8) /
[(R6 + R7 + R8)] + Vcb (Qp6) ≈8 (V) (3)
It will be about. However, Vcb (Qn6) = Vcb (Qp6) = 0.7 (V), R6 = 10 (kΩ), R7 = 3 (kΩ), R8 = 0.2 (kΩ).

よってこの場合は、ノードＡの電圧ＶＡ＝３２（Ｖ）、ノードＢの電圧ＶＢ＝８（Ｖ）であるので、位相補償容量Ｃ１の両端間の電圧ＶＣ１は、
ＶＣ１＝ＶＡ－ＶＢ
＝３２－８＝２４（Ｖ）（４）
となる。 Therefore, in this case, since the voltage VA of the node A = 32 (V) and the voltage VB of the node B = 8 (V), the voltage VC1 between both ends of the phase compensation capacitance C1 is
VC1 = VA-VB
= 32-8 = 24 (V) (4)
Will be.

次に、入力端子１１と接地ＧＮＤの間の短絡状態が解消されると、ノードＢの電圧ＶＢが８（Ｖ）から電圧源３０の電圧である３６（Ｖ）に上昇する。このため、位相補償容量Ｃ１のノードＡの電圧ＶＡは、
ＶＡ＝３２＋（３６－８）＝６０（Ｖ）（５）
となって素子耐圧４０Ｖを超えるため、各素子が破壊してしまう。 Next, when the short-circuit state between the input terminal 11 and the ground GND is resolved, the voltage VB of the node B rises from 8 (V) to 36 (V), which is the voltage of the voltage source 30. Therefore, the voltage VA of the node A having the phase compensation capacity C1 is
VA = 32+ (36-8) = 60 (V) (5)
As a result, the withstand voltage of the element exceeds 40 V, so that each element is destroyed.

接地ＧＮＤの電圧よりも高い電圧Ｖ２ａを内部基準電圧ライン１７に印加して電圧源３０の電圧Ｖ１の変動の影響を抑制することは、位相補償容量Ｃ１を備えた他の演算増幅器にも適用されている。このため、上記の例のように位相補償容量の一方のノードＡの電圧が大きく変化する事態が発生し、大きな問題が発生する。 Applying a voltage V2a higher than the voltage of the ground GND to the internal reference voltage line 17 to suppress the influence of fluctuations in the voltage V1 of the voltage source 30 is also applied to other operational amplifiers having the phase compensation capacitance C1. ing. Therefore, as in the above example, the voltage of one node A of the phase compensation capacity changes significantly, which causes a big problem.

本発明の目的は、内部基準電圧ラインに接地の電圧よりも高い電圧が印加される演算増幅器において、入力端子が接地に短絡しその後に短絡が解消した場合に上記したような問題が発生することを防止することである。 An object of the present invention is that in an operational amplifier in which a voltage higher than the ground voltage is applied to the internal reference voltage line, the above-mentioned problem occurs when the input terminal is short-circuited to the ground and the short circuit is subsequently resolved. Is to prevent.

上記目的を達成するために、請求項１にかかる発明は、接地端子との間に電源電圧が印加される電源端子と、前記電源電圧より低く前記接地端子の電圧よりも高い電圧が印加される内部基準電圧ラインと、第１及び第２入力端子を有する差動回路で構成された入力段並びにベース接地回路とカレントミラー回路で構成された出力段からなる折返しカスコード型の差動増幅回路と、該差動増幅回路の前記出力段に接続される電圧増幅回路と、前記第１入力端子に流れる電流を前記電圧増幅回路の出力信号に応じて制御して出力端子から出力する電流出力回路と、一端が前記電圧増幅回路の入力側に接続され他端が前記電圧増幅回路の出力側に接続される位相補償容量とを備え、前記差動増幅回路と前記電圧増幅回路が前記電源端子と前記内部基準電圧ラインとの間に接続されている演算増幅器において、前記位相補償容量の前記一端を所定電圧にクランプする電圧クランプ素子を設け、前記電圧クランプ素子は、前記位相補償容量の前記一端と前記電源端子との間に、前記電源端子の側がカソードとなるように接続された第１ダイオードであることを特徴とする。
請求項２にかかる発明は、接地端子との間に電源電圧が印加される電源端子と、前記電源電圧より低く前記接地端子の電圧よりも高い電圧が印加される内部基準電圧ラインと、第１及び第２入力端子を有する差動回路で構成された入力段並びにベース接地回路とカレントミラー回路で構成された出力段からなる折返しカスコード型の差動増幅回路と、該差動増幅回路の前記出力段に接続される電圧増幅回路と、前記第１入力端子に流れる電流を前記電圧増幅回路の出力信号に応じて制御して出力端子から出力する電流出力回路と、一端が前記電圧増幅回路の入力側に接続され他端が前記電圧増幅回路の出力側に接続される位相補償容量とを備え、前記差動増幅回路と前記電圧増幅回路が前記電源端子と前記内部基準電圧ラインとの間に接続されている演算増幅器において、前記位相補償容量の前記一端を所定電圧にクランプする電圧クランプ素子を設け、前記差動増幅回路が第１及び第２ＮＰＮトランジスタで構成され、前記ベース接地回路が前記第１ＮＰＮトランジスタのコレクタにエミッタが接続される第１ＰＮＰトランジスタと前記第２ＮＰＮトランジスタのコレクタにエミッタが接続される第２ＰＮＰトランジスタで構成され、該第２ＰＮＰトランジスタのコレクタに前記位相補償容量の前記一端が接続され、前記第２ＰＮＰトランジスタをＶＰＮＰ構造とし、前記第２ＰＮＰトランジスタのコレクタと前記電源端子の間に寄生する第２ダイオードを前記電圧クランプ素子としたことを特徴とする。
請求項３にかかる発明は、接地端子との間に電源電圧が印加される電源端子と、前記電源電圧より低く前記接地端子の電圧よりも高い電圧が印加される内部基準電圧ラインと、第１及び第２入力端子を有する差動回路で構成された入力段並びにベース接地回路とカレントミラー回路で構成された出力段からなる折返しカスコード型の差動増幅回路と、該差動増幅回路の前記出力段に接続される電圧増幅回路と、前記第１入力端子に流れる電流を前記電圧増幅回路の出力信号に応じて制御して出力端子から出力する電流出力回路と、一端が前記電圧増幅回路の入力側に接続され他端が前記電圧増幅回路の出力側に接続される位相補償容量とを備え、前記差動増幅回路と前記電圧増幅回路が前記電源端子と前記内部基準電圧ラインとの間に接続されている演算増幅器において、前記位相補償容量の前記一端を所定電圧にクランプする電圧クランプ素子を設け、前記差動増幅回路が第１及び第２ＮＰＮトランジスタで構成され、前記ベース接地回路が前記第１ＮＰＮトランジスタのコレクタにエミッタが接続される第１ＰＮＰトランジスタと前記第２ＮＰＮトランジスタのコレクタにエミッタが接続される第２ＰＮＰトランジスタで構成され、該第２ＰＮＰトランジスタのコレクタに前記位相補償容量の前記一端が接続され、前記電圧クランプ素子は、前記第２ＰＮＰトランジスタのベースと前記電源端子の間に、前記電源端子の側がカソードとなるように接続された第３ダイオードであることを特徴とする。
請求項４にかかる発明は、請求項１、２又は３に記載の演算増幅器において、前記電流出力回路は、前記第１入力端子に入力する電流を前記電圧増幅回路により制御して前記出力端子に出力する第５及び第６ＰＮＰトランジスタで構成したことを特徴とする。 In order to achieve the above object, the invention according to claim 1 is a power supply terminal to which a power supply voltage is applied between the ground terminal and a voltage lower than the power supply voltage and higher than the voltage of the ground terminal. A folded cascode type differential amplifier circuit consisting of an internal reference voltage line, an input stage composed of a differential circuit having first and second input terminals, and an output stage composed of a base ground circuit and a current mirror circuit. A voltage amplification circuit connected to the output stage of the differential amplification circuit, a current output circuit that controls the current flowing through the first input terminal according to the output signal of the voltage amplification circuit, and outputs the current from the output terminal. One end is connected to the input side of the voltage amplification circuit and the other end is connected to the output side of the voltage amplification circuit, and the differential amplification circuit and the voltage amplification circuit are connected to the power supply terminal and the inside. In the arithmetic amplifier connected to the reference voltage line, a voltage clamping element for clamping one end of the phase compensation capacity to a predetermined voltage is provided , and the voltage clamping element is the one end of the phase compensation capacity and the power supply. The first diode is connected to the terminal so that the side of the power supply terminal serves as a cathode .
The invention according to claim 2 is a power supply terminal to which a power supply voltage is applied between the ground terminal, an internal reference voltage line to which a voltage lower than the power supply voltage and higher than the voltage of the ground terminal is applied, and a first. A folded cascode type differential amplifier circuit consisting of an input stage composed of a differential circuit having a second input terminal and an output stage composed of a base ground circuit and a current mirror circuit, and the output of the differential amplification circuit. A voltage amplification circuit connected to the stage, a current output circuit that controls the current flowing through the first input terminal according to the output signal of the voltage amplification circuit and outputs it from the output terminal, and one end of the input of the voltage amplification circuit. It has a phase compensation capacity connected to the side and the other end connected to the output side of the voltage amplification circuit, and the differential amplification circuit and the voltage amplification circuit are connected between the power supply terminal and the internal reference voltage line. In the arithmetic amplifier, a voltage clamping element for clamping one end of the phase compensation capacity to a predetermined voltage is provided, the differential amplifier circuit is composed of first and second NPN transistors, and the base ground circuit is the first NPN. It is composed of a first PNP transistor whose emitter is connected to the collector of the transistor and a second PNP transistor whose emitter is connected to the collector of the second NPN transistor, and one end of the phase compensation capacitance is connected to the collector of the second PNP transistor. The second PNP transistor has a VPNP structure, and the second diode parasitic between the collector of the second PNP transistor and the power supply terminal is a voltage clamping element.
The invention according to claim 3 is a power supply terminal to which a power supply voltage is applied between the ground terminal, an internal reference voltage line to which a voltage lower than the power supply voltage and higher than the voltage of the ground terminal is applied, and a first. A folded cascode type differential amplifier circuit consisting of an input stage composed of a differential circuit having a second input terminal and an output stage composed of a base grounding circuit and a current mirror circuit, and the output of the differential amplification circuit. A voltage amplification circuit connected to a stage, a current output circuit that controls the current flowing through the first input terminal according to the output signal of the voltage amplification circuit and outputs the output from the output terminal, and one end of the input of the voltage amplification circuit. It has a phase compensation capacity connected to the side and the other end connected to the output side of the voltage amplification circuit, and the differential amplification circuit and the voltage amplification circuit are connected between the power supply terminal and the internal reference voltage line. In the arithmetic amplifier, a voltage clamping element for clamping one end of the phase compensation capacitance to a predetermined voltage is provided, the differential amplifier circuit is composed of first and second NPN transistors, and the base ground circuit is the first NPN. It is composed of a first PNP transistor whose emitter is connected to the collector of the transistor and a second PNP transistor whose emitter is connected to the collector of the second NPN transistor, and one end of the phase compensation capacitance is connected to the collector of the second PNP transistor. The voltage clamping element is characterized by being a third diode connected between the base of the second PNP transistor and the power supply terminal so that the power supply terminal side serves as a cathode.
The invention according to claim 4 is the operational amplifier according to claim 1, 2 or 3 , wherein the current output circuit controls a current input to the first input terminal by the voltage amplification circuit to the output terminal. It is characterized by being composed of the fifth and sixth PNP transistors to be output .

本発明によれば、位相補償容量の一端の電圧を電圧クランプ素子によってクランプできるので、第１入力端子が接地に短絡しその後に短絡が解消した際に位相補償容量の他端の電圧が変動しても、位相補償容量の一端の電圧が大きく変動することを防止でき、素子破壊を防止することができる。 According to the present invention, since the voltage at one end of the phase compensation capacity can be clamped by the voltage clamping element, the voltage at the other end of the phase compensation capacity fluctuates when the first input terminal is short-circuited to the ground and the short circuit is subsequently resolved. However, it is possible to prevent the voltage at one end of the phase compensation capacitance from fluctuating significantly, and it is possible to prevent element destruction.

本発明の第１実施例の演算増幅器の回路図である。It is a circuit diagram of the operational amplifier of 1st Embodiment of this invention. 本発明の第２実施例の演算増幅器の回路図である。It is a circuit diagram of the operational amplifier of the 2nd Embodiment of this invention. 本発明の第３実施例の演算増幅器の回路図である。It is a circuit diagram of the operational amplifier of the 3rd Embodiment of this invention. 従来の演算増幅器の回路図である。It is a circuit diagram of a conventional operational amplifier.

＜第１実施例＞
図１に本発明の第１実施例の演算増幅器１０Ａを示す。図１の演算増幅器１０Ａにおいて、図４で説明した演算増幅器１０Ｄと同じものには同じ符号を付けて重複説明は省略する。 <First Example>
FIG. 1 shows an operational amplifier 10A according to a first embodiment of the present invention. In the operational amplifier 10A of FIG. 1, the same reference amplifiers as those of the operational amplifier 10D described with reference to FIG. 4 are designated by the same reference numerals, and duplicate description will be omitted.

モータ、インバータ等の測定対象物２０は、電圧源２１の電圧Ｖａが検出抵抗Ｒｓを介して印加されることで、その測定対象物２０本来の動作を行い、その動作中に流れる電流Ｉｓによって、検出抵抗Ｒｓに検出電圧Ｖｓが発生する。 The measurement target 20 such as a motor, an inverter, etc. performs the original operation of the measurement target 20 by applying the voltage Va of the voltage source 21 via the detection resistor Rs, and the current Is flowing during the operation causes the measurement target 20 to perform the original operation. A detection voltage Vs is generated in the detection resistance Rs.

この検出電圧Ｖｓは、入力抵抗Ｒｉｎを経由して反転入力端子１１と非反転入力端子１２の間に印加され、トランジスタＱｎ１～Ｑｎ４、Ｑｐ１～Ｑｐ３，抵抗Ｒ１～Ｒ５、電流源Ｉ１，Ｉ２で構成される折返しカスコード型差動増幅回路によって増幅され、ノードＡに出力される。ノードＡの電圧信号は、トランジスタＱｐ４，Ｑｎ５，Ｑｎ６、抵抗Ｒ６、電流源Ｉ３，Ｉ４で構成される電圧増幅回路によって電圧増幅され、ノードＢに出力される。ノードＢの電圧信号は、位相補償容量Ｃ１によってノードＡに帰還される。また、ノードＢの電圧信号は、トランジスタＱｐ５，Ｑｐ６、抵抗Ｒ７，Ｒ８で構成される電流出力回路によって、入力端子１１から出力端子１３に流れる出力電流Ｉｏｕｔを制御する。 This detected voltage Vs is applied between the inverting input terminal 11 and the non-inverting input terminal 12 via the input resistor Rin, and is composed of transistors Qn1 to Qn4, Qp1 to Qp3, resistors R1 to R5, and current sources I1 and I2. It is amplified by the folded cascode type differential amplifier circuit and output to the node A. The voltage signal of the node A is voltage-amplified by a voltage amplification circuit composed of transistors Qp4, Qn5, Qn6, resistors R6, and current sources I3 and I4, and is output to the node B. The voltage signal of the node B is fed back to the node A by the phase compensation capacitance C1. Further, the voltage signal of the node B controls the output current Iout flowing from the input terminal 11 to the output terminal 13 by the current output circuit composed of the transistors Qp5 and Qp6 and the resistors R7 and R8.

この演算増幅器１０Ａでは、トランジスタＱｎ１のベース電流を無視すれば、検出抵抗Ｒｓに発生する電圧Ｖｓによって入力抵抗Ｒｉｎに流れる電流が制御されて出力電流Ｉｏｕｔとなる。このとき、そのトランジスタＱｐ５は入力端子１１、１２の間に入力している電圧Ｖｓに応じて制御されるので、出力電流Ｉｏｕｔは入力端子１１，１２の電圧が同じになるように帰還制御される。このため、抵抗Ｒ８の抵抗値を無視すれば、出力電流Ｉｏｕｔは、
Ｉｏｕｔ＝Ｖｓ／Ｒｉｎ（６）
として出力端子１３に流れる。よって出力電圧Ｖｏｕｔは、
Ｖｏｕｔ＝Ｉｏｕｔ・Ｒｏｕｔ
＝Ｖｓ・Ｒｏｕｔ／Ｒｉｎ（７）
となる。 In this operational amplifier 10A, if the base current of the transistor Qn1 is ignored, the current flowing through the input resistance Rin is controlled by the voltage Vs generated in the detection resistor Rs to become the output current Iout. At this time, since the transistor Qp5 is controlled according to the voltage Vs input between the input terminals 11 and 12, the output current Iout is feedback-controlled so that the voltages of the input terminals 11 and 12 are the same. .. Therefore, if the resistance value of the resistor R8 is ignored, the output current Iout will be.
Iout = Vs / Rin (6)
Flows to the output terminal 13. Therefore, the output voltage Vout is
Vout = Iout ・ Rout
= Vs · Rout / Rin (7)
Will be.

本実施例の演算増幅器１０Ａでは、図４で説明した演算増幅器１０Ｄと異なって、ノードＡと電源端子１４の間にダイオードＤ１を電圧クランプ素子として接続している。ダイオードＤ１のアノードはノードＡに、カソードは電源端子１４に接続されている。このため、ダイオードＤ１の順方向電圧をＶｆ１＝０．７（Ｖ）とすると、ノードＡの電圧ＶＡは、
ＶＡ＝Ｖ１＋Ｖｆ１
＝３６＋０．７＝３６．７（Ｖ）（８）
にクランプされる。 In the operational amplifier 10A of this embodiment, unlike the operational amplifier 10D described with reference to FIG. 4, a diode D1 is connected as a voltage clamp element between the node A and the power supply terminal 14. The anode of the diode D1 is connected to the node A, and the cathode is connected to the power supply terminal 14. Therefore, if the forward voltage of the diode D1 is Vf1 = 0.7 (V), the voltage VA of the node A will be.
VA = V1 + Vf1
= 36 + 0.7 = 36.7 (V) (8)
Clamped to.

したがって、入力端子１１が接地ＧＮＤに短絡し、その後その短絡が解消されたとしても、ノードＢの電圧ＶＢは前記したように８（Ｖ）から３６（Ｖ）に上昇するものの、ノードＡの電圧ＶＡは式（８）で与えられる電圧でクランプされるため、内部回路の素子に高電圧が印加する惧れは無い。 Therefore, even if the input terminal 11 is short-circuited to the ground GND and the short circuit is subsequently resolved, the voltage VB of the node B rises from 8 (V) to 36 (V) as described above, but the voltage of the node A Since the VA is clamped by the voltage given by the equation (8), there is no possibility that a high voltage will be applied to the element of the internal circuit.

＜第２実施例＞
図１の演算増幅器１０Ａでは、ダイオードＤ１によってノードＡの電圧ＶＡをクランプすることはできるものの、ダイオードＤ１で発生するリーク電流によって入力オフセット電圧などの特性に影響を与えてしまう。また、ダイオードＤ１の寄生容量によって周波数特性が劣化する惧れもある。 <Second Example>
In the operational amplifier 10A of FIG. 1, although the voltage VA of the node A can be clamped by the diode D1, the leakage current generated by the diode D1 affects the characteristics such as the input offset voltage. In addition, there is a possibility that the frequency characteristics will deteriorate due to the parasitic capacitance of the diode D1.

そこで、図２に示す本発明の第２実施例の演算増幅器１０Ｂでは、ＰＮＰトランジスタＱｐ１～Ｑｐ６をＶＰＮＰ構造（縦ＰＮＰ構造）で製造している。ＮＰＮトランジスタを製造する工程をそのまま利用してＰＮＰトランジスタを製造する場合には、通常ではラテラルＰＮＰ構造（横ＰＮＰ構造）を採用することが行われるが、本実施例ではＰＮＰトランジスタをＶＰＮＰ構造で製造する。このＶＰＮＰのトランジスタは、そのコレクタと電源端子１４に接続される埋込層（図示せず）の間のＰＮ接合に寄生ダイオードが生成する。ＰＮＰトランジスタＱｐ２についても同様であり、そのコレクタと電源端子１４の間の寄生ダイオードＤ２の順方向電圧をＶｆ２＝０．７（Ｖ）とすると、ノードＡの電圧ＶＡは、
ＶＡ＝Ｖ１＋Ｖｆ２
＝３６＋０．７＝３６．７（Ｖ）（９）
にクランプされる。 Therefore, in the operational amplifier 10B of the second embodiment of the present invention shown in FIG. 2, the PNP transistors Qp1 to Qp6 are manufactured with a VPNP structure (vertical PNP structure). When manufacturing a PNP transistor by using the process of manufacturing an NPN transistor as it is, a lateral PNP structure (horizontal PNP structure) is usually adopted, but in this embodiment, the PNP transistor is manufactured with a VPNP structure. do. In this VPNP transistor, a parasitic diode is generated at the PN junction between the collector and the embedded layer (not shown) connected to the power supply terminal 14. The same applies to the PNP transistor Qp2, and if the forward voltage of the parasitic diode D2 between the collector and the power supply terminal 14 is Vf2 = 0.7 (V), the voltage VA of the node A will be.
VA = V1 + Vf2
= 36 + 0.7 = 36.7 (V) (9)
Clamped to.

このように第２実施例では寄生ダイオードＤ２を電圧クランプ素子として使用し、特別なダイオードを使用しないので、第１実施例における上記した問題を防ぐことができる。 As described above, in the second embodiment, the parasitic diode D2 is used as the voltage clamping element and no special diode is used, so that the above-mentioned problem in the first embodiment can be prevented.

＜第３実施例＞
図２の演算増幅器１０Ｂでは、ＶＰＮＰのための特別な製造プロセスを採用する必要があるので、ウエハプロセス工程が増大するという問題がある。 <Third Example>
In the operational amplifier 10B of FIG. 2, since it is necessary to adopt a special manufacturing process for VPNP, there is a problem that the wafer process process is increased.

そこで、図３に示す本発明の第３実施例の演算増幅器１０Ｃでは、トランジスタＱｐ２（ラテラル構造）のベースと電源端子１４の間にダイオードＤ３を電圧クランプ素子として接続している。ダイオードＤ３のアノードはトランジスタＱｐ３のベースに、カソードは電源端子１４に接続されている。このため、ダイオードＤ３の順方向電圧をＶｆ３、トランジスタＱｐ２のコレクタ・ベースのＰＮ接合部の電圧をＶｃｂ（Ｑｐ２）とし、それらを０．７（Ｖ）とすると、ノードＡの電圧ＶＡは、
ＶＡ＝Ｖ１＋Ｖｆ３＋Ｖｃｂ（Ｑｐ２）
＝３６＋０．７＋０．７＝３７．４（Ｖ）（１０）
にクランプされる。 Therefore, in the operational amplifier 10C of the third embodiment of the present invention shown in FIG. 3, a diode D3 is connected as a voltage clamp element between the base of the transistor Qp2 (lateral structure) and the power supply terminal 14. The anode of the diode D3 is connected to the base of the transistor Qp3, and the cathode is connected to the power supply terminal 14. Therefore, if the forward voltage of the diode D3 is Vf3, the voltage of the collector-based PN junction of the transistor Qp2 is Vcb (Qp2), and they are 0.7 (V), the voltage VA of the node A is
VA = V1 + Vf3 + Vcb (Qp2)
= 36 + 0.7 + 0.7 = 37.4 (V) (10)
Clamped to.

本実施例によれば、ダイオードＤ３で発生するリーク電流は電流源Ｉ２に流れるため、入力オフセット電圧に影響を与えない。また、ダイオードＤ３の容量も、折返しカスコード回路を構成するトランジスタＱｐ２，Ｑｐ３のベースに接続されるため、周波数特性に悪影響を与えない。さらに、ＶＰＮＰの製造プロセスを採用しないので、コスト増を招くこともない。 According to this embodiment, the leak current generated by the diode D3 flows to the current source I2, and therefore does not affect the input offset voltage. Further, since the capacitance of the diode D3 is also connected to the base of the transistors Qp2 and Qp3 constituting the folded cascode circuit, the frequency characteristics are not adversely affected. Further, since the VPNP manufacturing process is not adopted, the cost does not increase.

＜その他の実施例＞
なお、以上の第１乃至第３実施例では電圧源１６を電源端子１４と内部基準電圧ライン１７の間に接続した場合について説明したが、接地ＧＮＤと内部基準電圧ライン１７の間に別の電圧源を接続した場合の演算増幅器についても、同様に適用することができる。 <Other Examples>
In the first to third embodiments described above, the case where the voltage source 16 is connected between the power supply terminal 14 and the internal reference voltage line 17 has been described, but another voltage is used between the ground GND and the internal reference voltage line 17. The same can be applied to an operational amplifier when a source is connected.

１０Ａ～１０Ｄ：演算増幅器、１１：反転入力端子、１２：非反転入力端子、１３：出力端子、１４：電源端子、１５：接地端子、１６：内部電圧源、１７：内部基準電圧ライン、１８：経路
２０：測定対象物、２１：電圧源
３０：電圧源 10A-10D: Operational amplifier, 11: Inverted input terminal, 12: Non-inverting input terminal, 13: Output terminal, 14: Power supply terminal, 15: Ground terminal, 16: Internal voltage source, 17: Internal reference voltage line, 18: Path 20: Object to be measured, 21: Voltage source 30: Voltage source

Claims

Difference having a power supply terminal to which a power supply voltage is applied between the ground terminal, an internal reference voltage line to which a voltage lower than the power supply voltage and higher than the voltage of the ground terminal is applied, and first and second input terminals. A folded cascode type differential amplification circuit consisting of an input stage composed of a dynamic circuit, a base grounding circuit, and an output stage composed of a current mirror circuit, and a voltage amplification circuit connected to the output stage of the differential amplification circuit. A current output circuit that controls the current flowing through the first input terminal according to the output signal of the voltage amplification circuit and outputs it from the output terminal, and one end connected to the input side of the voltage amplification circuit and the other end. In an arithmetic amplifier having a phase compensation capacity connected to the output side of a voltage amplification circuit and connecting the differential amplification circuit and the voltage amplification circuit between the power supply terminal and the internal reference voltage line.
A voltage clamping element for clamping one end of the phase compensation capacity to a predetermined voltage is provided .
The voltage clamp element is an operational amplifier characterized by being a first diode connected between the one end of the phase compensation capacity and the power supply terminal so that the power supply terminal side serves as a cathode .

Difference having a power supply terminal to which a power supply voltage is applied between the ground terminal, an internal reference voltage line to which a voltage lower than the power supply voltage and higher than the voltage of the ground terminal is applied, and first and second input terminals. A folded cascode type differential amplification circuit consisting of an input stage composed of a dynamic circuit, a base grounding circuit, and an output stage composed of a current mirror circuit, and a voltage amplification circuit connected to the output stage of the differential amplification circuit. A current output circuit that controls the current flowing through the first input terminal according to the output signal of the voltage amplification circuit and outputs it from the output terminal, and one end connected to the input side of the voltage amplification circuit and the other end. In an arithmetic amplifier having a phase compensation capacity connected to the output side of a voltage amplification circuit and connecting the differential amplification circuit and the voltage amplification circuit between the power supply terminal and the internal reference voltage line.
A voltage clamping element for clamping one end of the phase compensation capacity to a predetermined voltage is provided.
The differential amplification circuit is composed of first and second NPN transistors, and the grounded base circuit has an emitter connected to a collector of the first PNP transistor and a collector of the second NPN transistor. A second PNP transistor is composed of two PNP transistors, one end of the phase compensation capacitance is connected to the collector of the second PNP transistor, the second PNP transistor has a VPNP structure, and the second PNP transistor is parasitic between the collector of the second PNP transistor and the power supply terminal. An arithmetic amplifier characterized in that a transistor is used as the voltage clamping element.

Difference having a power supply terminal to which a power supply voltage is applied between the ground terminal, an internal reference voltage line to which a voltage lower than the power supply voltage and higher than the voltage of the ground terminal is applied, and first and second input terminals. A folded cascode type differential amplification circuit consisting of an input stage composed of a dynamic circuit, a base grounding circuit, and an output stage composed of a current mirror circuit, and a voltage amplification circuit connected to the output stage of the differential amplification circuit. A current output circuit that controls the current flowing through the first input terminal according to the output signal of the voltage amplification circuit and outputs it from the output terminal, and one end connected to the input side of the voltage amplification circuit and the other end. In an arithmetic amplifier having a phase compensation capacity connected to the output side of a voltage amplification circuit and connecting the differential amplification circuit and the voltage amplification circuit between the power supply terminal and the internal reference voltage line.
A voltage clamping element for clamping one end of the phase compensation capacity to a predetermined voltage is provided.
The differential amplification circuit is composed of first and second NPN transistors, and the grounded base circuit has an emitter connected to a collector of the first PNP transistor and a collector of the second NPN transistor. It is composed of a 2PNP transistor, one end of the phase compensation capacitance is connected to the collector of the second PNP transistor, and the voltage clamping element is a cathode between the base of the second PNP transistor and the power supply terminal. An arithmetic amplifier characterized by being a third transistor connected so as to be.

In the operational amplifier according to claim 1, 2 or 3 .
The current output circuit is an operational amplifier comprising the fifth and sixth PNP transistors that control the current input to the first input terminal by the voltage amplification circuit and output the current to the output terminal.