JP7016256B2 - Manufacturing method of printed wiring board - Google Patents

Description

The present invention relates to a method for manufacturing a printed wiring board having a cavity.

In recent years, with the increasing integration and density of boards and wiring, there are cases where a recess called a cavity is provided in a multilayer board and electronic components are mounted there. However, when mounting electronic components in a cavity, the cavity is used. It is desirable to flatten the bottom to strengthen the adhesive strength of electronic components.

In a conventional printed wiring board, for example, when a cavity is formed by counterbore processing of laser ablation, a solid copper pattern for receiving a laser is formed at the bottom of the cavity, and the solid copper pattern is etched to expose the underlying resin. By selectively removing the resin with a laser, the lower BGA ball pad is exposed, and a pad for connecting electronic components is formed at the bottom of the cavity.

By the way, in a printed wiring board having such a cavity structure, since the resin is removed by laser processing to expose the BGA ball pads, the distance between adjacent pads is determined by the accuracy of laser processing. Therefore, it can be said that there is a limit in terms of so-called miniaturization in which the pad spacing is narrowed to form more wiring.

Further, since the resin layer at the bottom of the cavity is removed to expose the lower BGA ball pad, a conductor layer cannot be formed from the bottom surface of the cavity to the outside on the same surface as the BGA ball pad. Therefore, in order to connect the electronic components housed in the cavity to the circuit of the board, it is necessary to route the wiring by providing a via on the board and dropping the circuit into the upper layer or the lower layer for wiring.

Further, when the connection between the electronic component and the circuit of the board is performed at the upper part by using a method such as wire bonding connection, the electronic component to be mounted in the electronic component cavity is fixed to the resin surface at the bottom of the cavity or the resin surface thereof. Although it becomes a solid copper pattern, the thickness of the resin cannot be controlled due to the penetration of the adhesive, and the solid copper pattern is formed thick by the laminated structure of copper foil and copper plating. There is a difficulty.

Japanese Unexamined Patent Publication No. 2016-12728

In this way, when the electronic components are housed in the cavity and the circuit is connected, in the connection at the bottom of the cavity, vias are provided in the connection between the electronic components in the cavity and the circuit outside the cavity, and the wiring is connected to the lower layer or the upper layer. Need to be routed to.
Further, when the electronic component housed in the cavity is connected at the upper part, there is a problem that the thickness of the layer constituting the bottom surface of the cavity varies and the force for fixing the electronic component is weak.

The present invention has been made to solve such a problem, and is a printed wiring that can increase the fixing force of the electronic component at the bottom of the cavity while facilitating the connection between the electronic component inside the cavity and the circuit outside the cavity. The purpose is to provide a method for manufacturing a board.

The method for manufacturing a printed wiring board of the present invention includes a step of preparing a substrate on which a seed layer having a thickness of 1 μm or more and 5 μm or less has been formed, a step of forming a via hole pilot hole in the substrate on which the seed layer is formed, and a step of forming a via hole pilot hole. The steps of attaching the first dry film on the seed layer, exposing and developing the vias to be formed later and removing the first dry film on the seed layer around the vias, and the above-mentioned formed on the substrate. A step of applying a pattern plating process on the via hole pilot hole and the seed layer around the via hole pilot hole to form a via on the via hole pilot hole and a conductive layer on the seed layer around the via hole pilot hole. The width of the step of peeling off the remaining first dry film from the substrate and the width of the portion of the substrate on which the via and the conductive layer are formed, which will later become a cavity formation planned region, is made wider than the width of the substrate. A step of forming a second dry film, a step of removing a portion of the seed layer outside the second dry film to form a core substrate, and a step of laminating a build-up layer on the core substrate are performed. A step of producing a multilayer board in which a part of the seed layer is embedded inside, and a cavity is formed by drilling a part of the area of the multilayer board from above to remove the insulating resin to a position close to the seed layer. It has a step of forming and a step of using the seed layer as a shielding member for laser light, removing the remaining portion of the insulating resin remaining in the cavity by laser processing, and exposing the seed layer to the bottom of the cavity.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a method for manufacturing a printed wiring board capable of increasing the fixing force of an electronic component at the bottom of the cavity while facilitating the connection between the electronic component inside the cavity and the circuit outside the cavity.

It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 1st Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 2nd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of 3rd Embodiment.

Hereinafter, some embodiments according to the present invention will be described with reference to the drawings.
(First Embodiment)
FIG. 12 is a diagram showing a configuration of a printed wiring board according to the first embodiment of the present invention.

As shown in FIG. 12, the printed wiring board of the first embodiment has a via 15 for interlayerly connecting conductors (conductor layers 16, 17, 69) provided in each layer of the multilayer board 54, and a predetermined layer of the multilayer board 54. A cavity 20 having a cavity bottom formed so that a part of the region (a part of the seed layer 12 region on the surface of the core substrate 51) is exposed, and a thin and flat first conductor layer formed at the bottom of the cavity 20. And formed on the electronic component 84 housed in the cavity 22 and fixed on the seed layer 12 at the bottom of the cavity 20 via the plating layer 81 and the adhesive layer 82, and on the multilayer substrate 54. It has a connection pad 83, and a bonding wire 89 that connects the connection pad 83 and the upper electrode 85 of the electronic component 84.

In order to fix the electronic component 84, the plating layer 81 is not an essential element, and the electronic component 84 may be adhered onto the seed layer 12 via the adhesive layer 82. It is even more preferable to use a material having good thermal conductivity for the adhesive layer 82.

The multilayer board 54 is a multilayer board structure in which a build-up layer 61 is formed on an upper layer of a core substrate 51 and a build-up layer 62 is formed on a lower layer of a core substrate 51. It has a core substrate 51 formed below the insulating resin layer 61b and having a seed layer 12 formed on the upper surface thereof.

The cavity 20 has a predetermined depth (build-up layer) of a part of a region of a predetermined layer of the multilayer substrate 54 (a region 65 to be formed of the cavity 20 in the region of the seed layer 12 formed on the core substrate 54). It is a concave portion formed by drilling and / or laser processing to a position near the upper surface position of the insulating resin layer 61a of 61) and removing the balance remaining by this processing by laser processing.

That is, the cavity 20 is a concave groove portion in which the region 65 is counterbored to a width that can accommodate the electronic component 84 to form the cavity bottom (bottom surface), and the seed layer 12 formed on the upper surface of the core substrate 51 is exposed. The bottom of the cavity (bottom surface) is formed as described above.

The electronic component 84 is, for example, a bare chip (an unpackaged terminalless IC) and has an upper electrode 85 for wire bonding connection. The electronic component 84 is bonded and fixed on the seed layer 12 exposed at the bottom of the cavity 20 via a metal plating layer 81 such as nickel plating and gold plating and an adhesive layer 82.

The conductor layer 63a is provided as a part of a circuit formed on the multilayer board 54 (the core board 51 and the build-up layers 61 and 62 above and below the core board 51). The conductor layer 63a is a solid copper pattern, and is formed by, for example, plating a copper foil (thickness of about 9 μm) with copper plating (thickness of about 15 μm).

A via 15 is connected to the extension destination (direction along the surface) of the conductor layer 63a. The via 15 interconnects conductors (conductor layers 16, 63a, 70, etc.) provided in each layer of the multilayer board 54.

The connection pad 83 is a metal plating layer obtained by gold plating on nickel plating, and is formed on the conductor layer 63a. The connection pad 83 connects the electronic component 84 and the circuit outside the cavity of the multilayer board 54 by connecting the upper electrode 85 of the electronic component 84 via the bonding wire 89. That is, the connection pad 83 is a pad for connecting to the cavity 20 (electronic component 84) by wire bonding.

That is, this printed wiring board is housed in a cavity 20 formed by counterboring a part of a region 65 of a multilayer board 54 in which build-up layers 61 and 62 are formed on a core substrate 51, and is housed in the cavity 20 at the bottom of the cavity. It has an electronic component 84 to be fixed.

The bottom of the cavity 20 is an exposed seed layer 12 formed on the upper surface of the core substrate 51 constituting the core of the inner layer of the build-up layer 61.

The bottom surface of the cavity 22 has a conductive layer (seed layer 12 and / or conductor layer 16) formed on the upper surface of an insulating resin layer 11 (hereinafter referred to as “board 11”) (see FIG. 5) which is a material of the core substrate 51. It is a thing.

Examples of the insulating resin forming the substrate 11 include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicon resin, polybutadiene resin, and polyester. Examples thereof include resins, melamine resins, urea resins, polyphenylene sulfide (PPS) resins, and polyphenylene oxide (PPO) resins. Two or more kinds of these resins may be mixed.

A seed layer 12 arranged around a via hole pilot hole 14 (via 15) (see FIGS. 1 and 2) is provided on the upper surface of the substrate 11, and plating is performed including the seed layer 12 and the via hole pilot hole 14. The conductor layer 16 and the via 15 are formed.

The via 15 is formed by filling the via hole pilot hole 14 with metal plating by a plating process. The conductor layer 16, the seed layer 12 below it, the via 15, and the like are referred to as a circuit unit. The via 15 interconnects conductors (conductor layers 63a, 70, 16, etc.) provided in each layer (including an inner layer and an outer layer) of the multilayer board 54. In the cross-sectional view of this example, it can be seen that the conductor layer 63a is connected to the conductor layer 70 through the via 15.

The seed layer 12 is, for example, copper having a thickness of 1 μm to 5 μm (1 μm or more and 5 μm or less), and is arranged in a state where a part thereof remains under the conductor layer 16. The seed layer 12 is not particularly limited as long as it is electrically connected, but for example, thin copper foil or electroless copper plating is used.

In the core substrate 51, the upper surface of the substrate 11 is circuit-formed by a method such as a modified semi-additive process (MSAP) or a semi-additive process (SAP), and a connection is provided in a part of the seed layer 12 and a part of the seed layer 12. The pad and the conductor layer 16 to be the circuit wiring are protected from flash etching by an etching resist and exposed to form an upper surface portion (see FIG. 5).

The conductor layer 16 is a circuit that electrically connects to the electronic component 84 arranged on the bottom surface of the cavity 20, or a conductive layer that connects the circuit of the same layer to the via 15. A part of the seed layer 12 remains under the conductor layer 16. In other words, the conductor layer 16 is formed by performing pattern plating on a partial region of the seed layer 12.

Hereinafter, a method of manufacturing the printed wiring board of the first embodiment will be described with reference to FIGS. 1 to 12.
(Insulation layer processing process)
As shown in FIG. 1, a seed layer 12 (for example, a conductive metal foil such as a thin copper foil) is laminated and formed on the upper surface and the lower surface of a substrate 11 made of an insulating resin. Alternatively, the substrate 11 on which the seed layer 12 has been formed is prepared. The seed layer 12 is formed on the substrate 11 with a thickness of, for example, about 1 μm to 5 μm. A via hole pilot hole 14 is formed in the substrate 11 on which the seed layer 12 is formed by laser processing.

When the via hole pilot hole 14 is formed by laser processing, a thin resin film may remain at the bottom of the via hole pilot hole 14. In this case, desmear processing is performed. In the desmear treatment, the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.).

In addition, the resin film may be removed by, for example, a wet blast treatment with an abrasive or a plasma treatment. Further, the inner wall surface of the via hole pilot hole 14 may be roughened for the plating treatment. Examples of the roughening treatment include a wet process using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.), a dry process such as a plasma treatment and an ashing treatment, and the like.

Subsequently, the dry film 13 is attached on the seed layer 12, exposed and developed to form a circuit portion such as a conductor layer 16 on the upper surface and a via 15, and a conductor layer 17 which is a conductive circuit on the lower surface. To remove.

(Pattern plating process)
As shown in FIG. 2, the conductor layer 16 on the upper surface of the substrate 11 is subjected to pattern plating treatment on the via hole pilot hole 14 for forming the circuit portion of the laminated board from which a part of the dry film 13 is removed and the seed layer 12 around the via hole pilot hole 14. And the via 15 inside the substrate 11 and the conductive layer (including the seed layer 12 and the conductor layer 17) on the lower surface of the substrate 11 are formed.

(Dry film peeling process)
After the pattern plating treatment, the remaining dry film 13 is peeled off to expose the seed layer 12 as shown in FIG.

(Processing process of the area where the cavity is to be formed)
As shown in FIG. 4, a dry film 18 (photosensitive etching resist) is attached to the upper surface of the substrate 11 by laminating, and then exposed and developed to remove the dry film 18 other than the region where the cavity is to be formed. Of the exposed seed layer 12, unnecessary portions outside the dry film 18 as a conductive circuit are removed by flash etching, and finally the dry film 18 is peeled off.

That is, the dry film 18 is attached to the cavity formation planned region in the area of the seed layer 12 formed on the surface of the substrate 11, the seed layer 12 outside the dry film 18 is removed by flash etching, and then the seed layer 12 is formed. The upper dry film 18 is peeled off.

In this way, the core substrate 51 as shown in FIG. 5 is completed. On the upper surface of the substrate 11 of the core substrate 51, in addition to the conductor layer 16 as a part of the circuit connected to the via 15, the seed layer 12 is formed in the region where the cavity is to be formed. The portion of the seed layer 12 in which the cavity is planned to be formed serves as a laser receiving (shielding member) during laser processing described later. Further, a conductor layer 17 as a conductive circuit is formed on the lower surface of the substrate 11. In this example, the circuit was formed using MSAP as an example, but the circuit can also be formed by SAP using electroless copper plating as the seed layer.

(Build-up layer formation process)
Next, as shown in FIG. 6, the upper layer and / or the lower layer of the core substrate 51 is built up an arbitrary number of times to produce the multilayer substrate 54. That is, in this step, the seed layer 12 is built with the internal core substrate 51 (insulating resin substrate) by forming the build-up layers 61 and 62 on the core substrate 51 while leaving the seed layer 12 in the region where the cavity is to be formed. A multilayer insulating resin substrate 54 (hereinafter referred to as "multilayer substrate 54") embedded between the up layer 61 (superstructure) is manufactured (formed).

For the circuit formation of the build-up layers 61 and 62, for example, not only the subtractive method of removing unnecessary conductors as a circuit by etching but also MSAP, SAP and the like can be applied as in the case of the core substrate 51. Techniques such as multi-stage pressing or resin laminating are used for laminating the build-up layers 61 and 62.

The layer formed by building up on the upper layer of the core substrate 51 is referred to as a build-up layer 61, and the layer formed by building up on the lower layer of the core substrate 51 is referred to as a build-up layer 62.

In this example, the upper build-up layer 61 is composed of two insulating resin layers 61a and 61b. A conductor layer 63 connected to the via 15 is formed on one surface on the upper surface of the insulating resin layer 61b of the uppermost layer (surface layer). Further, a conductor layer 64 is formed on the build-up layer 62 (bottom layer) below the core substrate 51. The conductor layer 64 shall be formed as needed.

(Window formation process)
In this step, of the conductor layer 63 formed on the upper surface of the uppermost layer (insulating resin layer 61b) of the multilayer substrate 54, as shown in FIG. 7, the region 65 directly above the region where the cavity is to be formed is removed. This is to facilitate counterbore processing in the cavity forming step described later.

(Cavity forming process)
1. 1. Drilling In this step, the insulating resin layers 61b and 61a above the planned cavity formation region of the build-up layer 61 are drilled from above the multilayer board 54 to the vicinity of the seed layer 12 on the upper surface of the core board 51. The insulating resin of the insulating resin layers 61b and 61a is removed to form the cavity 20.

Specifically, as shown in FIG. 8, a drill 66 having a sensor at the tip of the bit is arranged at one end of a region 65 from which the pattern directly above the planned cavity formation region is removed, and a seed layer on the surface of the core substrate 51 is arranged. The drill 66 is machined to a position in front of 12 (a position in front of the bottom of the cavity 20), and the drill 66 is moved from that position in the lateral direction A to perform counterbore processing.

In this example, a part of the prepreg resin layer 68 is left on the bottom of the cavity 20, but if the drilling accuracy is high, the seed layer 12 may be scraped to the very limit of the surface.

The reason why the counterbore processing is performed in two stages including not only the laser processing described later but also the drill processing is that the seed layer 12 is used as a receiving conductor (shielding member) for the laser processing described later.

The seed layer 12 is, for example, a conductor of about 1 μm to 5 μm, which is thinner than a conductor of ordinary pattern plating (thickness of 20 μm or more). It is preferable to reduce the output of the laser so as not to penetrate the seed layer 12 without increasing the output.

2. 2. Laser processing In this step, as shown in FIG. 9, a laser beam is irradiated from above the opening of the cavity 20 in the direction of arrow B to be exposed at the bottom in FIG. A part of the prepreg resin layer 68 (the rest of the upper layer portion) left by the drilling process is removed by laser machining. For laser processing, for example, a processing laser such as a carbon dioxide gas laser (CO ₂ laser) or a YAG laser can be applied. In this way, the seed layer 12 is used as a shielding member for laser light, and the remaining portion of the upper layer portion left at the bottom of the cavity 20 is removed by laser processing to expose the seed layer 12 to the bottom of the cavity 20.

When the prepreg resin layer 68 at the bottom of the cavity 20 is machined by laser machining, a thin resin film may remain in that portion. In this case, desmear processing is performed. In the desmear treatment, the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.). Alternatively, the resin film may be removed by a wet blast treatment with an abrasive or a plasma treatment.

By forming the width of the seed layer 12 which is a laser light receiving conductor (laser light shielding member) wider than the cavity 20, the build-up layer 61 next to the cavity 20 on the extension line of the bottom surface of the cavity 20 Since the seed layer 12 remains in the (insulating resin layer) in the form of being inserted, the seed layer 12 can be used as a part of the circuit for connection with the electronic component 84 described later.
Further, since the seed layer 12, which is a thin conductor layer (metal leaf), serves as a heat sink, a good heat dissipation effect can be obtained in terms of heat dissipation when the electronic component 84 is mounted on the upper portion.

(Outer layer circuit formation process)
In this step, as shown in FIG. 10, the conductor layer 70 is formed as a circuit with respect to the conductor layer 64 of the build-up layer 62 at the lower part of the substrate shown in FIG. Further, a part of the region is removed by etching the conductor layer 63 of the build-up layer 61 on the upper part of the substrate to form the conductor layer 63a as a circuit as shown in FIG. For the formation of the outer layer circuit, a subtractive method using an electrodeposited resist having excellent followability to the wall surface of a dent or a through hole as an etching resist is applied. The electrodeposition resist is an etching resist that applies the properties of electrodeposition coating.

(Solder resist process)
In this step, the build-up layers 61 and 62 shown in FIG. 10 are coated with an insulating film including a part of the conductor layers 63a and 70 to form the solder resists 71 and 72 as shown in FIG.

(Process for forming the mounting location of electronic components)
In this step, as shown in FIG. 12, a metal plating layer 81 such as nickel plating and gold plating is formed on the seed layer 12 exposed at the bottom of the cavity 20, and an adhesive is applied on the metal plating layer 81 to form an adhesive layer. Form 82. Further, a connection pad 83 for connection with the electronic component 84 is formed on the conductor layer 63a of the build-up layer 61.

(Electronic component mounting process)
In this step, as shown in FIG. 12, the electronic component 84 is placed on the adhesive layer 82 at the bottom of the cavity 20 and adhered and fixed. In this case, the electronic component 84 is not mounted, and when it is mounted elsewhere, the steps below the electronic component mounting step are unnecessary.

(Electronic component connection process)
In this step, the connection pad 83 and the cavity 20 are connected by wire bonding via a bonding wire 89.
Specifically, by connecting the upper electrode 85 of the electronic component 84 and the connection pad 83 on the conductor layer 63a of the build-up layer 61 by wire bonding, the electronic component 84 and the outside of the cavity 20 of the multilayer board 54 are connected. Connect the circuit. In this way, a printed wiring board in which the electronic component 84 is housed in the cavity 20 can be manufactured.

As described above, according to the printed wiring board of the first embodiment, the multilayer board 54 is counterbored from the surface layer so that a part of the seed layer 12 of the core layer 51 of the inner layer of the multilayer board 54 is exposed. The bottom of 20 is formed, the electronic component 84 is mounted in the cavity 20 (fixed to the bottom of the cavity 20), and the upper electrode 85 of the electronic component 84 and the connection pad 83 on the conductor layer 63a of the build-up layer 61 are bonded. The cavity structure connected by the wire 89 has the following effects.

By connecting to the circuit on the substrate side at the upper part of the electronic component 84 housed in the cavity 20, it is possible to facilitate the circuit connection between the two. Further, by adhering and fixing the electronic component 84 to the seed layer 12 flatly exposed at the bottom of the cavity 20, the fixing force of the electronic component 84 at the bottom of the cavity 20 can be increased.

By setting the average roughness Ra of the surface of the seed layer 12 to, for example, 0.3 μm or more and 0.6 μm or less, the roughness (average roughness) suitable for adhering other members (resin or metal) to the surface of the seed layer 12 is appropriate. If Ra is 0.2 μm or less or 0.7 μm or more, the adhesive strength is reduced). Therefore, the average roughness Ra of the surface of the seed layer 12 is preferably in the range of 0.3 μm or more and 0.6 μm or less.

That is, it is possible to increase the fixing force of the electronic component 84 at the bottom of the cavity 20 while facilitating the connection between the electronic component 84 inside the cavity 20 and the circuit outside the cavity 20.

Hereinafter, the second embodiment will be described with reference to FIGS. 13 to 23. In explaining the second embodiment, the same reference numerals are given to the same configurations as those of the first embodiment, and the description thereof will be omitted.

As shown in FIG. 23, the printed wiring board of the second embodiment has a via 15 for interlayerly connecting conductors (conductor layers 16, 17, 63a, 70) provided in each layer of the multilayer board 55, and a via 15 as a first cavity. The cavity 21 is formed inside the cavity 21 as a second cavity formed in a concave shape (a groove shape in which the bottom of the cavity is flat), and a flat surface is exposed at the bottom of the cavity 22. Above the seed layer 12, the electronic component 84 housed in the cavity 22 and adhered and fixed to the bottom of the cavity 22, the conductor layer 73 formed in the cavity 21 (step 75), and the conductor layer 73. It has a formed connection pad 83, and a bonding wire 89 that connects the connection pad 83 and the upper electrode 85 of the electronic component 84.

The cavity 21 has a predetermined depth (insulation resin of the build-up layer 61) in a part of a predetermined layer of the multilayer substrate 55 (a region 65 to be formed of the cavity 21 on the upper surface of the insulating resin layer 61b of the build-up layer 61). It is a concave portion formed by drilling and / or laser machining to the position near the upper surface position of the layer 61a, and removing the remaining portion by laser machining to form the bottom, and later for forming the cavity 22. Since the central portion is counterbored, the bottom portion (bottom surface) of the cavity remains as the step portion 75.

In other words, in the cavity 21 (step portion 75), a partial region 65 of the insulating resin layer 61b of the multilayer substrate 55 is counterbored so that the conductor layer 73 on the upper surface of the insulating resin layer 61a is exposed at the bottom of the cavity 21. Is formed, and a partial region 69 of the insulating resin layer 61a is counterbored so as to leave a region (step portion 75) at the end at a certain distance from the wall surface at the bottom of the cavity 21.

In the cavity 22, the insulating resin layer 61a is counterbored leaving the region (step portion 75) at the bottom of the cavity 21 so that a part of the region of the seed layer 12 on the upper surface of the core substrate 51 is exposed. It forms the bottom.

Hereinafter, a method for manufacturing the printed wiring board of the second embodiment will be described.
In the second embodiment, as shown in FIG. 13, the upper layer and / or the lower layer of the core substrate 51 shown in FIG. 5 is built up an arbitrary number of times to produce the multilayer substrate 55. That is, in this step, the multilayer substrate 55 is manufactured by forming the build-up layers 61 and 62 on the core substrate 51 while leaving the seed layer 12 in the region where the cavity is to be formed.

For the circuit formation of the build-up layers 61 and 62, for example, not only the subtractive method of removing unnecessary conductors as a circuit by etching but also MSAP, SAP and the like can be applied as in the case of the core substrate 51. Techniques such as multi-stage pressing or resin laminating are used for laminating the build-up layers 61 and 62.

The layer formed by building up on the upper layer of the core substrate 51 is referred to as a build-up layer 61, and the layer formed by building up on the lower layer of the core substrate 51 is referred to as a build-up layer 62.

In this example, the upper build-up layer 61 is composed of two insulating resin layers 61a and 61b. A conductor layer 63 connected to the via 15 is formed on one surface on the upper surface of the insulating resin layer 61b of the uppermost layer (surface layer). Further, in the insulating resin layer 61a of the lower layer of the inner layer of the build-up layer 61, a conductor layer 73 connected to the via 15 and a seed layer 74 formed between the conductor layers 73 are formed. Further, a conductor layer 64 is formed on the build-up layer 62 (bottom layer) below the core substrate 51. The conductor layer 64 shall be formed as needed.

(Window formation process)
In this step, of the conductor layer 63 formed on the upper surface of the uppermost layer (insulating resin layer 61b) of the multilayer substrate 54, as shown in FIG. 14, the region 65 directly above the region where the cavity is to be formed is removed. This is to facilitate counterbore processing in the cavity forming step described later.

(First cavity forming step)
1. 1. Drilling In this step, the portion of the insulating resin layer 61b above the planned cavity formation region of the build-up layer 61 is drilled and removed to the vicinity of the conductor layer 73 and the seed layer 74 of the insulating resin layer 61a below it. To form the cavity 21.

Specifically, as shown in FIG. 15, a drill 66 having a sensor at the tip of the bit is arranged at one end of a region 65 from which the pattern directly above the planned cavity formation region is removed, and a conductor layer on the surface of the core substrate 51 is arranged. The drill 66 is machined to a position in front of the 73 and the seed layer 74 (a position in front of the bottom of the cavity 21), and the drill 66 is moved from that position in the lateral direction A to perform counterbore processing.

In this example, a part of the prepreg resin layer 68 is left on the bottom of the cavity 21, but if the drilling accuracy is high, the conductor layer 73 may be scraped to the very limit of the surface.

The reason why the counterbore processing is performed in two stages including not only the laser processing described later but also the drill processing is that the conductor layer 73 and the seed layer 74 are used as the receiving conductor (shielding member) of the laser processing described later. be.

The seed layer 74 is, for example, a conductor of about 1 μm to 5 μm, which is thinner than a conductor of ordinary pattern plating, so that the laser output is not increased as in the case of removing a thick resin by counterbore processing only by laser processing. It is preferable to reduce the output of the laser so that it does not penetrate the seed layer 74.

2. 2. Laser processing In this step, as shown in FIG. 16, laser light is irradiated from above the opening of the cavity 21 in the direction of arrow B, and the bottom is exposed by the processing of FIG. A part of the prepreg resin layer 68 left by the drilling process is removed by laser processing. For laser processing, for example, a processing laser such as a carbon dioxide gas laser (CO ₂ laser) or a YAG laser can be applied. In this way, the seed layer 74 is used as a shielding member for laser light, the remaining portion of the upper layer portion left at the bottom of the cavity 21 is removed by laser processing, and the conductor layer 73 and the seed layer 74 inside the conductor layer 73 are attached to the bottom of the cavity 20. Expose.

When the prepreg resin layer 68 at the bottom of the cavity 21 is machined by laser machining, a thin resin film may remain in that portion. In this case, desmear processing is performed. In the desmear treatment, the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.). Alternatively, the resin film may be removed by a wet blast treatment with an abrasive or a plasma treatment.

3. 3. Seed layer removal In this step, as shown in FIG. 17, a portion 69 of the seed layer 74 inside the cavity 21 is flash-etched so as to leave a first region (step 75) of the exposed conductor layer 73 at the bottom. Remove. In other words, the seed layer 74 (conductive metal leaf) inside the conductor layer 73 at the bottom of the cavity 21 is removed by flash etching. For flash etching, for example, a sulfuric acid-based etching solution is used.

(Second cavity forming step)
1. 1. Drilling In this step, drilling is performed leaving the area at the end of the bottom of the cavity 21 so that the seed layer 12 (second seed layer) formed below the bottom of the cavity 21 is exposed at the bottom of the cavity. A cavity 22 (second cavity) is formed.
In this drilling, first, in the build-up layer 61, the portion of the insulating resin above the region where the bottom surface of the second cavity is to be formed is drilled to remove the portion of the build-up layer 51 up to the vicinity of the seed layer 12 on the upper surface of the core layer 51, and the cavity 22 is formed. To form.

Specifically, a drill 66 having a sensor at the tip of the bit is arranged at one end of the region 69 shown in FIG. 17, and a position in front of the seed layer 12 from the upper surface of the insulating resin layer 61a (before reaching the bottom of the cavity 22). Shave downward to the position of). In this example, a region (step portion 75) slightly wider than the width of the exposed conductor layer 73 is left so as not to scrape the portion of the conductor layer 73, and the region (step portion 75) is used as the bottom surface (bottom portion) of the cavity 21. And.

After that, as shown in FIG. 18, the drill 66 at the position in front of the seed layer 12 (the position before reaching the bottom of the cavity 22) is moved from that position in the lateral direction A to perform counterbore processing. The cavity 22 is formed.

In this example, the prepreg resin layer 68 is left on the seed layer 12 which is the bottom surface of the cavity 22, but if the drilling accuracy is high, the prepreg resin layer 68 may be scraped to the very limit of the surface of the seed layer 12.

The reason why the counterbore processing is performed in two stages including not only the laser processing described later but also the drill processing is that the seed layer 12 is used as a receiving conductor (shielding member) for the laser processing described later. The seed layer 12 is, for example, a conductor of about 1 μm to 5 μm, which is thinner than a conductor of ordinary pattern plating, so that the laser output is not increased as in the case of removing a thick resin by counterbore processing only by laser processing. It is preferable to reduce the output of the laser so that it does not penetrate the seed layer 12.

2. 2. Laser processing In this step, as shown in FIG. 19, a laser beam is irradiated from above the opening of the cavity 22 in the direction of arrow B to be exposed at the bottom in FIG. The prepreg resin layer 68 left by the drilling process is removed by laser processing. For laser processing, for example, a processing laser such as a carbon dioxide gas laser (CO ₂ laser) or a YAG laser can be applied. As shown in FIG. 20, the seed layer 12 is used as a shielding member for laser light, and the remaining portion (prepreg resin layer 68) of the upper layer portion left at the bottom of the cavity 22 is removed by laser processing. A portion of the layer 12 is exposed to the bottom of the cavity 22.

When the prepreg resin layer 68 at the bottom of the cavity 22 is machined by laser machining, a thin resin film may remain in that portion. In this case, the desmear process is performed in the same manner as described above.

By forming the width of the seed layer 12, which is a laser light receiving conductor (laser light shielding member), wider than that of the cavity 22, the build-up layer 61 next to the cavity 22 on the extension line of the bottom surface of the cavity 22 Since the seed layer 12 remains in the (insulating resin layer) in the form of being inserted, the seed layer 12 can be used as a part of the circuit for connection with the electronic component 86 described later.

(Outer layer circuit formation process)
In this step, as shown in FIG. 20, the conductor layer 70 is formed as a circuit with respect to the conductor layer 64 of the build-up layer 62 at the lower part of the substrate shown in FIG. Further, a part of the region is removed by etching the conductor layer 63 of the build-up layer 61 on the upper part of the substrate shown in FIG. 19, and the conductor layer 63a as a circuit is formed as shown in FIG. For the formation of the outer layer circuit, a subtractive method using an electrodeposited resist having excellent followability to the wall surface of a dent or a through hole as an etching resist is applied. The electrodeposition resist is an etching resist that applies the properties of electrodeposition coating.

(Solder resist process)
In this step, the build-up layers 61 and 62 shown in FIG. 20 are coated with an insulating film including a part of the conductor layers 63a and 70 to form the solder resists 71 and 72 as shown in FIG. 21.

(Process for forming the mounting location of electronic components)
In this step, as shown in FIG. 22, a metal plating layer 81 such as nickel plating and gold plating is formed on the seed layer 12 exposed at the bottom of the cavity 22, and an adhesive material is applied thereto to form an adhesive layer. Form 82. Further, a connection pad 83 for connection with the electronic component 86 is formed on the conductor layer 73 at the bottom (step portion 75) of the cavity 21.

(Electronic component mounting process)
In this step, as shown in FIG. 23, the electronic component 86 is placed on the adhesive layer 82 at the bottom of the cavity 22 and adhered and fixed. In this case, the electronic component 86 is not mounted, and when it is mounted elsewhere, the steps below the electronic component mounting step are unnecessary.

(Electronic component connection process)
In this step, the connection pad 83 and the cavity 22 are connected by wire bonding via a bonding wire 89.
Specifically, by connecting the upper electrode 85 of the electronic component 86 and the connection pad 83 on the conductor layer 73 at the bottom of the cavity 22 by wire bonding, the circuit outside the cavity of the electronic component 86 and the multilayer board 55 can be formed. Connecting. In this way, a printed wiring board in which the electronic component 86 is housed in the cavity 22 can be manufactured.

As described above, according to the printed wiring board of the second embodiment, the multilayer board 55 is counterbored from the surface layer, and the bottom of the cavity 21 is exposed so that a part region 65 of the insulating resin layer 61a of the multilayer board 55 is exposed. The cavity 22 is formed and counterbored to a part of the insulating resin layer 61a so as to leave a region (step portion 75) at a certain distance from the wall surface of the bottom of the cavity 21 so that the cavity 22 can accommodate the electronic component 86. A two-stage cavity structure is formed, in which the electronic component 86 is mounted (fixed) in the cavity 22, and the upper electrode 85 of the electronic component 86 and the connection pad 83 formed in the step portion 75 of the cavity 21 are connected by a bonding wire 89. By doing so, the following effects are obtained.

By connecting to the connection pad 83 of the cavity 21 formed in a stepped manner on the upper part of the electronic component 86 mounted on the cavity 22 by wire bonding, it is not necessary to route the circuit in the inner layer of the multilayer board 55 as in the conventional case, and the cavity 22 is eliminated. The connection between the inner electronic component 86 and the outer circuit can be facilitated.

Further, in the wire bonding connection, since laser processing or the like is not required, the electrode spacing of the upper electrode 85 of the electronic component 86 and the pad spacing of the connection pad 83 can be narrowed (narrowed in pitch), so that further miniaturization is possible in the future.

Further, since the electronic component 84 is fixed on the thin seed layer 12 exposed at the bottom of the cavity 22, the height as in the conventional BGA ball becomes unnecessary, and the space of the cavity 22 can be effectively used. can.

Further, since the connection pad 83 is provided in the cavity 21 provided in the middle stage of the inner layer of the multilayer board 54, the height of the bonding wire 89 is lower (and does not become higher) than the uppermost surface of the multilayer board 54, and the lid is on the uppermost surface. It becomes possible to flatten the multilayer board 55 on which the electronic component 86 is mounted.

As a result, in addition to the same effect as that of the first embodiment, the connection between the electronic component 86 inside the cavity 22 and the circuit outside the cavity can be facilitated, and further miniaturization is possible in the future, and the cavities 21 and 22 can be further miniaturized. Space can be used effectively.

(Third Embodiment)
Next, the printed wiring board of the third embodiment according to the present invention will be described with reference to FIGS. 24 to 37. FIG. 37 is a diagram showing a configuration of a printed wiring board according to a third embodiment of the present invention. In explaining the third embodiment, the same reference numerals are given to the same configurations as those of the first embodiment and the second embodiment, and the description thereof will be omitted.

As shown in FIG. 37, the printed wiring board of the third embodiment is a conductor (conductor layers 17, 97) provided in each layer of the multilayer board 96 (multilayer board 91 and build-up layers 93, 94, 95, etc. on the multilayer board 91). , 98, 102, etc.) through the upper and lower sides (board stacking direction) and connected, and the multilayer board 96 is counterbored from the upper surface of the uppermost layer and provided in a part of the inner layer of the multilayer board 96. The cavity 21 as one cavity, the cavity 22 as a second cavity formed in a concave shape inside the cavity 21, the electronic component 88 housed and fixed (fixed) in the cavity 22, and the bottom of the cavity 21 ( The conductor layer 97 formed in the step portion 75), the connection pad 83 formed on the conductor layer 97, and the bonding wire 89 connecting the connection pad 83 and the upper electrode 85 of the electronic component 86 are formed. Have.

The conductor layer 97 is formed in the inner layer of the insulating resin substrate 95 and is connected to the through hole 100. The conductor layer 98 is a dummy pattern formed on the surface of the uppermost layer of the multilayer substrate.

The conductor layer 102 is formed by insulating the surface of the uppermost layer and / or the lowermost layer of the multilayer board 96 with a solder resist 72 so as to function as a circuit pattern.

The through hole 100 is provided so as to penetrate the multilayer board 96 vertically (in the substrate stacking direction) in a portion outside the region of the cavity 21 of the multilayer board 96.

That is, the printed wiring board of the third embodiment is an example in which the multilayer board 96 provided with the through hole 100 has a two-stage cavity structure.

Hereinafter, a method of manufacturing the printed wiring board of the third embodiment will be described with reference to FIGS. 24 to 37. In this third embodiment, as shown in FIG. 31, vias 15 are formed in the layer below the cavity formation planned region C of the multilayer board 96 to connect the circuits to each other, and the area other than the cavity formation planned region C ( A through hole 100 is formed in the place), and the conductor layers 17 and 97 provided in each layer are connected through in the substrate stacking direction. Since the detailed procedure for forming the core substrate 91, which is the basic portion of the multilayer substrate 96, has been described in the procedure for forming the core substrate 51 of the first embodiment, the description will be simplified here.

(Core substrate forming process)
1. 1. Insulation layer processing step In this step, as shown in FIG. 24, a laser is used in a cavity formation region of the substrate 11 in which a seed layer 12 (for example, a conductive metal foil such as a thin copper foil) is laminated and formed on the upper surface and the lower surface of the substrate 11. The via hole pilot hole 14 is formed by processing.

Subsequently, the seed layer is excluded from the circuit portion such as the conductor layers 16 and 17 on the upper surface of the substrate 11 and the via 15 and the planned formation location (conducting layer 16 and 17 formation region) of the conductor layer 17 which is the conductive circuit on the lower surface. After the dry film 13 is attached on the 12, the upper and lower surfaces are exposed and developed.

2. 2. Pattern plating process In this step, as shown in FIG. 25, the via hole pilot hole 14 for forming the circuit portion of the substrate 11 and the seed layer 12 around the via hole pilot hole 14 are subjected to the pattern plating process, and the conductor layers on the upper surface and the lower surface of the substrate 11 are subjected to the pattern plating process. 16 and 17 are formed.

3. 3. Dry film peeling step After the pattern plating process, the dry film 13 is peeled off to expose the seed layer 12 and the conductor layers 16 and 17 on the surface of the substrate 11 as shown in FIG. 26. A portion of the exposed seed layer 12 that is unnecessary as a conductive circuit is removed by flash etching. As a result, as shown in FIG. 27, the core substrate 90 is completed in which the via 15 is provided in the planned cavity formation region and the conductor layer 17 is provided in a region other than the planned cavity formation region (outside the planned cavity formation region).

(Build-up layer formation process)
Next, as shown in FIG. 28, build-up is performed on the upper layer and / or the lower layer of the core substrate 90 to manufacture a multilayer substrate 91 (in this example, a multilayer substrate 91 having a four-layer structure). In this step, the build-up layer 91a is formed on the core substrate 90, and the multi-layer substrate 91 having a four-layer structure in which the build-up layer 91b is formed under the core substrate 90 is formed.

For circuit formation of the build-up layers 91a and 91b, for example, not only the subtractive method of removing unnecessary conductors as a circuit by etching, but also MSAP, SAP and the like as in the formation method of the core substrate 90 (see FIG. 28) are used. Applicable. Techniques such as multi-stage pressing or resin laminating are used for laminating the build-up layers 91a and 91b.

In this example, in order to form the through hole 100 later, a conductor layer 17 is formed in each of the build-up layers 91a and 91b so as to overlap the conductor layer 17 of the core substrate 90 in the vertical direction (board stacking direction). Further, on the lower surface of the build-up layer 91b, a conductor layer 92 connected to the via 15 is formed on one surface. The conductor layer 92 is left as it is after the plating process in order to form a circuit after bonding.

(One-sided build-up process)
In this step, as shown in FIG. 29, the build-up layer 93 is formed by one-sided build-up on one side (in this example, the upper surface of the board) of the multi-layer board 91 having a four-layer structure. At this time, the seed layer 12 is formed in the cavity formation planned region on the upper surface of the build-up layer 93.

Further, as shown in FIG. 29, a multilayer board 94 manufactured independently of the multilayer board 91 having a four-layer structure in which the build-up layer 93 is laminated is laminated and bonded via a prepreg resin 95. A multilayer substrate 96 that is a source for forming through holes is manufactured. For the laminating process in this case, for example, a multi-stage press or the like is used.

A conductor layer 98 such as a solid copper pattern is formed on one surface of the uppermost layer of the multilayer board 94. Further, in the inner layer of the multilayer substrate 94, the seed layer 74 is formed in advance in the region where the first cavity is planned to be formed, and the conductor layer 97 is formed in the region where the through hole is planned to be formed outside the seed layer 74.

(Through hole forming process)
In this step, as shown in FIG. 30, a through-hole pilot hole 99 is formed in the multilayer substrate 96 by a drill (not shown) so as to penetrate the conductor layers 17 and 97 vertically (in the substrate stacking direction). ..

Next, the multilayer substrate 96 is subjected to electrolytic plating treatment mainly for the purpose of forming a conductor layer on the wall surface of the through-hole pilot hole 99, and the conductor layer 100 is formed as shown in FIG. 31.

Then, the conductor layer 98 (copper solid pattern) on the upper surface of the multilayer board 96 is processed to form an outer layer circuit. At this time, the conductor layer (a part of the conductor layer 98, also referred to as a dummy pattern) in the region C directly above the region where the first cavity is to be formed is removed, and the resin portion under the conductor layer 98 is exposed. And. This is to facilitate drilling (counterbore processing) in the next process.

(First cavity forming step)
1. 1. Drilling In this step, in the multilayer substrate 96 shown in FIG. 31, the region C (the region directly above the region where the first cavity is to be formed) where the uppermost resin layer is exposed is drilled downward to form the inner conductor layer. The resin layer is removed to the vicinity of 97 and the seed layer 74 to form the cavity 21 (see FIG. 32).

Specifically, a drill 66 (see FIG. 32) is placed at the end of the region C from which the pattern directly above the planned cavity formation region is removed, as shown in FIG. 31, and the conductor layer 97 and the seed layer of the multilayer substrate 96 are arranged. The drill 66 is machined to a position in front of 74 (a position in front of the bottom of the cavity 21), and then, as shown in FIG. 32, the drill 66 is moved from that position in the lateral direction A to perform counterbore processing.

In this example, a part of the prepreg resin layer 68 is left on the bottom of the cavity 21, but if the drilling accuracy is high, the conductor layer 97 may be scraped to the very limit of the surface.

The reason why the counterbore processing is performed in two stages including not only the laser processing described later but also the drill processing is that the conductor layer 97 and the seed layer 74 are used as the receiving conductor (shielding member) of the laser processing described later. be. The seed layer 74 is, for example, a conductor of about 1 μm to 5 μm, which is thinner than a conductor of ordinary pattern plating (conductor layer 97). It is preferable to reduce the output of the laser so as not to penetrate the seed layer 74 without increasing the output.

2. 2. Laser processing In this step, as shown in FIG. 33, a laser beam is irradiated from above the opening of the cavity 21 in the direction of arrow B to be exposed at the bottom in FIG. 32. A part of the prepreg resin layer 68 left by the drilling process is removed by laser processing. For laser processing, for example, a processing laser such as a carbon dioxide gas laser (CO ₂ laser) or a YAG laser can be applied. In this way, the conductor layer 97 and the seed layer 74 are used as a shielding member for laser light, and the residual resin of the upper layer left at the bottom of the cavity 21 is removed by laser processing, whereby the seed layer 74 and the conductor layer 97 are removed from the cavity 21. Expose to the bottom of the.

When the prepreg resin layer 68 at the bottom of the cavity 21 is machined by laser machining, a thin resin film may remain in that portion. In this case, desmear processing is performed. In the desmear treatment, the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.). Alternatively, the resin film may be removed by a wet blast treatment with an abrasive or a plasma treatment.

3. 3. Seed layer removal In this step, the portion of the seed layer 74 is removed by flash etching so as to leave the exposed conductor layer 97 at the bottom of the cavity 21. In other words, the seed layer 74 (conductive metal leaf) inside the conductor layer 97 at the bottom of the cavity 21 is removed by flash etching. For flash etching, for example, a sulfuric acid-based etching solution is used.

(Second cavity forming step)
1. 1. Drilling In this step, the resin portion on the seed layer 12 which is the bottom surface of the cavity 22 (second cavity) of the multilayer board 94 is drilled to make the resin layer of the inner layer of the multilayer board 94 near the seed layer 12. To form the outer wall of the cavity 22.

Specifically, as shown in FIG. 34, a drill 66 having a sensor at the tip of a bit is arranged at one end of a region 69, which is a region where a second cavity is planned to be formed, and a drill 66 is arranged from above the multilayer substrate 94 to above the seed layer 12. It is cut down to a nearby position (a position before reaching the bottom of the cavity 22). In this example, a region (step portion 75) slightly wider than the width of the conductor layer 97 is left as a side wall (wall surface) of the cavity 21 so as not to scrape the end portion of the conductor layer 97.

After that, as shown in FIG. 34, the drill 66 is moved from the position to the lateral direction A to perform counterbore processing, thereby forming the cavity 22.

In this example, the prepreg resin layer 68 is left on the seed layer 12 which is the bottom surface of the cavity 22, but if the drilling accuracy is high, the prepreg resin layer 68 may be scraped to the very limit of the surface of the seed layer 12.

The reason why the counterbore processing is performed in two stages including not only the laser processing described later but also the drill processing is that the seed layer 12 is used as a receiving conductor (shielding member) for the laser processing described later. The seed layer 12 is, for example, a conductor of about 1 μm to 5 μm, which is thinner than a conductor of ordinary pattern plating, so that the laser output is not increased as in the case of removing a thick resin by counterbore processing only by laser processing. It is preferable to reduce the output of the laser so that it does not penetrate the seed layer 12.

2. 2. Laser processing In this step, as shown in FIG. 35, laser light is irradiated from above the opening of the cavity 22 in the direction of arrow B to remove the prepreg resin layer 68 exposed at the bottom of the cavity 22 in FIG. 34 (laser processing). ). For this laser processing, for example, a processing laser such as a carbon dioxide gas laser (CO ₂ laser) or a YAG laser can be applied. As shown in FIG. 36, the seed layer 12 is used as a shielding member for laser light, and the remaining portion (prepreg resin layer 68) of the upper layer portion left at the bottom of the cavity 22 is removed by irradiation with laser light. It forms the bottom of the cavity 22 with a portion of the seed layer 12 exposed.

When the prepreg resin layer 68 at the bottom of the cavity 22 is machined by laser machining, a thin resin film may remain in that portion. In this case, the desmear treatment is performed in the same manner as when the first cavity is formed.

By forming the width of the seed layer 12, which is a laser light receiving conductor (laser light shielding member), wider than the width of the cavity 22 as in this example, the cavity 22 on the extension line of the bottom surface of the cavity 22 is formed. Since the seed layer 12 remains in the inner layer of the multilayer board 96 next to the above, the seed layer 12 can be used as a part of the circuit for connection with the electronic component 84 described later.

(Outer layer circuit formation process)
In this step, as shown in FIG. 37, the conductor layer 102 is formed as a circuit on the conductor layer 92 of the lowermost layer of the multilayer substrate 96 shown in FIG. 36 by an electrodeposition resist method or the like. For circuit formation, a subtractive method using an electrodeposited resist having excellent followability to the wall surface of a dent or a through hole as an etching resist is suitable. The electrodeposition resist is one of the etching resists to which the properties of electrodeposition coating are applied. Further, the conductor layer 102 is similarly formed as a circuit for the conductor layer 98 of the uppermost layer.

(Solder resist process)
In this step, as shown in FIG. 37, an insulating film is formed including a part of the upper and lower conductor layers 102 to form a solder resist 72.

(Process for forming the mounting location of electronic components)
In this step, as shown in FIG. 37, a metal plating layer 81 such as nickel plating and gold plating is formed on the seed layer 12 exposed at the bottom of the cavity 22, and an adhesive material is applied thereto to form an adhesive layer. Form 82. Further, a connection pad 83 for connecting to the electronic component 88 is formed on the conductor layer 97 (step portion) at the bottom of the cavity 21 by plating such as nickel plating and gold plating.

(Electronic component mounting process)
In this step, as shown in FIG. 37, the electronic component 88 is placed on the adhesive layer 82 at the bottom of the cavity 22 and adhered and fixed. The electronic component 88 is thicker than the electronic component 86 (see FIG. 23) of the second embodiment.

Subsequently, by connecting the upper electrode 85 of the electronic component 88 and the connection pad 83 at the bottom (step portion 75) of the cavity 21 by wire bonding, the electronic component 86 and the circuit outside the cavity (conductor layer 97) of the multilayer board 96 are connected. And through holes 100 connected to the conductor layer 97, etc.). In this way, a printed wiring board in which the electronic component 86 thicker than that of the first embodiment is housed in the cavity 22 can be manufactured.

The example of the manufacturing procedure of the printed wiring board in each of the above embodiments is an example, and the processing processes can be changed in various ways by replacing each processing process, adding a new processing process, and deleting a part of the processing processes. It is also possible.

As described above, according to the printed wiring board of the third embodiment, the thick multilayer board 96 in which the multilayer board 96 is bonded to the multilayer board 91 has a two-stage cavity structure, and the circuit (conductor layer) of each layer is formed on the multilayer board 96. 17, 97, 102, etc.) are connected through the through hole 100 to facilitate the connection between the electronic component 88 in the cavity 22 and the circuit outside the cavity 21 as in the first embodiment, and further in the future. In addition to the effects that miniaturization is possible and the space of the cavity 22 can be effectively used, the thick electronic component 88 can be mounted so as not to protrude from the upper surface of the multilayer board 96. Furthermore, it is possible to further increase the number of layers, such as laminating and forming build-up boards.

Although the embodiment of the present invention has been described, this embodiment is shown as an example, and can be implemented in various other forms, and the components of the invention are not deviated from the gist of the invention. It can be omitted, replaced, or changed.

11 ... Insulation resin layer (board)
12, 74 ... Seed layer 13 ... Dry film 14 ... Via hole pilot hole 15 ... Via 16, 17, 63, 64, 69, 70, 73, 92, 102 ... Conductor layer 18 ... Dry film 21, 22 ... Cavities 51, 90 ... Core substrate 54, 91, 94, 96 ... Multilayer substrate 61 (61a, 61b), 62 ... Build-up layer 65, 69 ... Region 66 ... Drill 68 ... Prepreg resin layer 72 ... Solder resist 84, 86, 88 ... Electronic components 85 ... Upper electrode 89 ... Bonding wire 99 ... Through hole pilot hole 100 ... Through hole

Claims (7)

The process of preparing a substrate on which a seed layer having a thickness of 1 μm or more and 5 μm or less has been formed, and
A step of forming a via hole pilot hole in the substrate on which the seed layer is formed, and
A step of attaching the first dry film on the seed layer, exposing and developing the vias to be formed later and removing the first dry film on the seed layer around the vias.
The via hole pilot hole formed on the substrate and the seed layer around the via hole pilot hole are subjected to pattern plating treatment to form a via on the via hole pilot hole and on the seed layer around the via hole pilot hole. The process of forming the conductive layer and
The step of peeling off the remaining first dry film from the substrate,
A step of forming a second dry film on the substrate on which the via and the conductive layer are formed, which is wider than the width of a portion to be a region to be formed later.
A step of removing a portion of the seed layer outside the second dry film to form a core substrate.
A step of laminating a build-up layer on the core substrate to produce a multilayer substrate in which a part of the seed layer is embedded inside.
A step of drilling a part of a region of the multilayer board from above to remove an insulating resin to a position close to the seed layer to form a cavity.
The printed wiring is characterized in that the seed layer is used as a shielding member for laser light, the remaining portion of the insulating resin remaining in the cavity is removed by laser processing, and the seed layer is exposed to the bottom of the cavity. How to make a board. The printed wiring board according to claim 1, further comprising a step of forming a connection pad for connecting electronic components housed in the cavity by wire bonding in a region outside the cavity of the substrate . Production method. It is characterized by having a step of forming a second cavity so that the second seed layer formed below the bottom is exposed to the bottom of the cavity by counterbore processing leaving the region at the end of the bottom of the cavity. The method for manufacturing a printed wiring board according to claim 1. It is characterized by having a step of forming a connection pad for connecting electronic components housed in the second cavity by wire bonding in the region of the end of the cavity left during the formation of the second cavity. The method for manufacturing a printed wiring board according to claim 3 . The method for manufacturing a printed wiring board according to claim 1, further comprising a step of adhering an electronic component on the exposed seed layer via an adhesive layer. Any one of claims 1 to 5 , wherein a via is formed in each layer of the multilayer board by penetrating and connecting a conductor provided in each layer of the multilayer board. The method for manufacturing a printed wiring board according to the section. The method for manufacturing a printed wiring board according to any one of claims 1 to 6 , further comprising a step of forming a through hole connected to a conductor provided in each layer of the multilayer board .

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