JP6949167B2 - 半導体装置及びその充電システム - Google Patents
半導体装置及びその充電システム Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 55
- 238000009792 diffusion process Methods 0.000 claims description 52
- 239000002019 doping agent Substances 0.000 claims description 52
- 210000000746 body region Anatomy 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 20
- 230000003071 parasitic effect Effects 0.000 description 27
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000007599 discharging Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 1
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- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
一部実施例において、第1のS/D領域306はN型高濃度ドーパントである。一部実施例において、二重拡散層302の上半部のドープ濃度は二重拡散層の下半部のドープ濃度よりも高い。
12 電池
14 制御素子
16 ノード
18 充電器
19 負荷
30 半導体装置
32 トランジスタ
33 ゲート構造
37 上面
40 充電システム
42 ロジックANDゲート
50 充電システム
54 制御素子
60 半導体装置
62 トランジスタ
70 半導体装置
72 トランジスタ
140 出力端子
142 出力端子
200 半導体装置
201 基板
203 ドレイン
204 本体領域
205 P型ウェル
206 ソース
210 ゲート材料
211 ゲート構造
212 誘電層
215 金属層
300 基板
302 二重拡散層
304 第1のウェル
306 第1のS/D領域
308 第2のウェル
310 第2のS/D領域
312 誘電層
314 導電材料
316 側壁
540 出力端子
602 二重拡散層
604 側面
610 第2のS/D領域
D1 ドレイン
D2 ドレイン
G1 ゲート
G2 ゲート
M0 パワーMOSトランジスタ
M1 パワーMOSトランジスタ
M2 パワーMOSトランジスタ
PD0 寄生ダイオード
PD1 寄生ダイオード
PD3 寄生ダイオード
PD4 寄生ダイオード
S1 ソース
S2 ソース
V− 端子
V+ 端子
Claims (17)
- 半導体装置において、
トランジスタであって、
二重拡散層上の第1のウェル中に設けられており、前記二重拡散層と前記第1のウェルとが接面にてダイオードを形成しており、前記ダイオードの正極とでオープン回路を形成する第1のソース/ドレイン(S/D)領域と、
第2のS/D領域と、
前記第1のS/D領域と前記第2のS/D領域との間に設けられるゲート構造と、
を含むトランジスタ、
を備え、
前記第2のS/D領域は前記二重拡散層上の第2のウェル中に設けられ、前記第2のS/D領域と前記第2のウェルとは同一タイプのドーパントを有し、
前記第1のS/D領域と前記第2のS/D領域とは同じ高さである、半導体装置。 - 前記第1のウェルはトランジスタの本体領域を持たない、請求項1に記載の半導体装置。
- 前記半導体装置は前記トランジスタの本体領域を持たない、請求項1に記載の半導体装置。
- 前記半導体装置は、前記第1のS/D領域と前記第1のウェルとを接続する導電層を持たない、請求項1に記載の半導体装置。
- 前記第2のS/D領域と前記二重拡散層とは同一タイプのドーパントを有し、前記第1のウェルと前記二重拡散層とは異なるタイプのドーパントを有する、請求項1に記載の半導体装置。
- 前記第1のS/D領域はN型ドーパントを有し、前記第1のウェルはP型ドーパントを有し、前記二重拡散層はN型ドーパントを有し、前記第2のウェルはN型ドーパントを有し、前記第2のS/D領域はN型ドーパントを有する、請求項5に記載の半導体装置。
- 前記第1のウェルと前記第2のウェルとは異なるタイプのドーパントを有する、請求項1に記載の半導体装置。
- 前記第1のウェルは基板中に設けられており、前記第1のS/D領域は前記第1のウェルの一つの領域中に設けられ、前記領域は前記基板の上面に近接する、請求項1に記載の半導体装置。
- 半導体装置において、
トランジスタであって、
二重拡散層上の第1のウェル中に設けられており、前記二重拡散層及び前記第1のウェルは基板上に設けられ、前記第1のウェルと前記二重拡散層は異なるタイプのドーパントを有し、 前記第1のウェルの一つの領域中に設けられて、且つ前記領域は前記基板の上面に近接する第1のソース/ドレイン(S/D)領域と、
第2のS/D領域と、
前記第1のS/D領域と前記第2のS/D領域との間に設けられるゲート構造と、
を含むトランジスタ
を備え、
前記第1のS/D領域と前記第2のS/D領域とは同じ高さである、半導体装置。 - 前記第1のウェルと前記第1のS/D領域とは異なるタイプのドーパントを有する、請求項9に記載の半導体装置。
- 前記第2のS/D領域は前記二重拡散層上の第2のウェル中に設けられ、前記第2のS/D領域と前記第2のウェル及び前記二重拡散層とは同一タイプのドーパントを有する、請求項9に記載の半導体装置。
- 前記第1のウェルと前記第2のウェルとは異なるタイプのドーパントを有する、請求項11に記載の半導体装置。
- 前記第1のS/D領域はN型ドーパントを有し、前記第1のウェルはP型ドーパントを有し、前記二重拡散層はN型ドーパントを有し、前記第2のウェルはN型ドーパントを有し、前記第2のS/D領域はN型ドーパントを有する、請求項11に記載の半導体装置。
- 充電システムにおいて、
トランジスタと、
電池と、
前記電池の電圧に基づいて前記トランジスタの導電状態を制御するように設けられる制御素子と、
を備えており、
前記トランジスタは、
二重拡散層上の第1のウェル中に設けられており、前記二重拡散層と前記第1のウェルとが接面にてダイオードを形成しており、前記ダイオードの正極とでオープン回路を形成する第1のソース/ドレイン(S/D)領域と、
第2のS/D領域と、
前記第1のS/D領域と前記第2のS/D領域との間に設けられるゲート構造と、
を含み、
前記第2のS/D領域は前記二重拡散層上の第2のウェル中に設けられ、前記第2のS/D領域と前記第2のウェルとは同一タイプのドーパントを有し、
前記第1のS/D領域と前記第2のS/D領域とは同じ高さである、充電システム。 - 前記電圧がしきい値電圧を超えたとき、前記制御素子は前記トランジスタが導電しないように制御する、請求項14に記載の充電システム。
- 前記電圧がしきい値電圧未満のとき、前記制御素子は前記トランジスタが導電しないように制御する、請求項14に記載の充電システム。
- 前記制御素子は前記トランジスタに接続する出力端子を一つのみ有する、請求項14に記載の充電システム。
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US201762485709P | 2017-04-14 | 2017-04-14 | |
US62/485,709 | 2017-04-14 | ||
US15/858,746 US11227925B2 (en) | 2017-04-14 | 2017-12-29 | Semiconductor device and charging system using the same |
US15/858,746 | 2017-12-29 | ||
JP2018040518A JP2018182307A (ja) | 2017-04-14 | 2018-03-07 | 半導体装置及びその充電システム |
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JPS60154671A (ja) | 1984-01-25 | 1985-08-14 | Hitachi Ltd | 半導体装置 |
JPH0697450B2 (ja) | 1987-10-30 | 1994-11-30 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | コンピユータ・システム |
JPH0335534A (ja) | 1989-07-03 | 1991-02-15 | Seiko Epson Corp | 半導体装置の製造方法 |
US5640034A (en) * | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
US6351009B1 (en) * | 1999-03-01 | 2002-02-26 | Fairchild Semiconductor Corporation | MOS-gated device having a buried gate and process for forming same |
JP2001352683A (ja) | 2000-06-02 | 2001-12-21 | Seiko Instruments Inc | 充放電式電源装置 |
TW495951B (en) | 2001-05-29 | 2002-07-21 | Taiwan Semiconductor Mfg | Electro-static discharge protection design for charged-device mode using deep well structure |
EP1498998A1 (en) * | 2003-07-16 | 2005-01-19 | Dialog Semiconductor GmbH | Protection switch with reverse voltage protection |
CN101364610B (zh) | 2007-08-10 | 2012-06-27 | 力芯科技股份有限公司 | 沟槽式功率金氧半晶体管及其制作方法 |
KR101710599B1 (ko) * | 2011-01-12 | 2017-02-27 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
JP2013004539A (ja) | 2011-06-10 | 2013-01-07 | Toshiba Corp | 半導体装置、金属膜の製造方法及び半導体装置の製造方法 |
JP5927017B2 (ja) * | 2012-04-20 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2014049481A (ja) | 2012-08-29 | 2014-03-17 | Toshiba Corp | 半導体装置 |
TWI560886B (en) * | 2014-09-25 | 2016-12-01 | Inotera Memories Inc | Non-floating vertical transistor structure and method for forming the same |
CN107425072A (zh) * | 2017-09-06 | 2017-12-01 | 睿力集成电路有限公司 | 一种半导体存储器的器件结构 |
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CN108735815A (zh) | 2018-11-02 |
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