JP6924871B2 - Luminous display panel - Google Patents

Description

The present invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistor is I
It is widely applied to electronic devices such as C and electro-optical devices, and its development is urgently needed as a switching element for image display devices. Further, as a semiconductor thin film, metal oxides are attracting attention, and various metal oxides exist and are used for various purposes. In particular, as a metal oxide, indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

Some metal oxides exhibit semiconductor properties. Examples of the metal oxide exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like, and a thin film having a metal oxide exhibiting such semiconductor characteristics as a channel forming region is already known. (Patent Document 1 and Patent Document 2).

Japanese Unexamined Patent Publication No. 2007-123861 JP-A-2007-96055

In the active matrix type display device, the electrical characteristics of the thin film transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the power consumption during non-operation (power consumption during standby) due to the increase in off current (also referred to as leakage current, Ifoff, etc.) becomes important.

In the case of an n-channel thin film transistor, a thin film transistor in which a channel is formed only when a positive voltage is applied to the gate voltage and a drain current flows out is desirable. A thin film transistor in which an off-current flows when the voltage applied to the gate is a negative voltage is not suitable as a thin film transistor used in a circuit.

For example, when the off-current of the thin film transistor constituting the circuit in the semiconductor device is large,
There is a risk of current leakage due to the increase in the off-current. Therefore, one aspect of the present invention is to provide a thin film transistor that operates stably in a wide temperature range and a semiconductor device using the thin film transistor. In the present specification and the like, the off-current of the thin film transistor indicates a current value when the voltage applied to the gate is a negative voltage.

One aspect of the present invention disclosed herein has a gate electrode layer on a substrate having an insulating surface, a gate insulating layer on the gate electrode layer, and an oxide semiconductor layer on the gate insulating layer. An insulating layer having a source electrode layer and a drain electrode layer on the oxide semiconductor layer and in contact with a part of the oxide semiconductor layer on the gate insulating layer, the oxide semiconductor layer, the source electrode layer and the drain electrode layer. Have,
The semiconductor device is characterized in that ^{the off-current value per 1 μm of the channel width is 1 × 10 -12} A or less in the temperature range of -25 ° C. or higher and 150 ° C. or lower.

In the above configuration, the channel length of the oxide semiconductor layer may be 1.5 μm or more and 100 μm or less. Further, the channel length of the oxide semiconductor layer may be 3 μm or more and 10 μm or less.

Further, one aspect of the present invention disclosed in the present specification is to form a gate electrode layer on a substrate having an insulating surface, form a gate insulating layer on the gate electrode layer, and form an oxide semiconductor on the gate insulating layer. After forming the layer and forming the oxide semiconductor layer, the first heat treatment and the second heat treatment are performed to form the source electrode layer and the drain electrode layer on the oxide semiconductor layer, and the gate insulating layer and the oxidation Fabrication of a semiconductor device characterized in that an insulating layer in contact with a part of the oxide semiconductor layer is formed on a physical semiconductor layer, a source electrode layer and a drain electrode layer, and after forming the insulating layer, a third heat treatment is performed. The method.

In the above configuration, the first heat treatment is preferably performed in a nitrogen atmosphere or a noble gas atmosphere. Further, the first heat treatment is preferably performed at a temperature of 350 ° C. or higher and 750 ° C. or lower.

In the above configuration, the second heat treatment is preferably performed in an air atmosphere or an oxygen atmosphere.
The second heat treatment is preferably performed at 100 ° C. or higher and lower than the first heat treatment temperature.

The above configuration solves at least one of the above problems.

_{A thin film represented by InMO 3} (ZnO) _m (m> 0) is formed from the oxide semiconductor used in the present specification, and the thin film is used as the oxide semiconductor layer to produce a thin film transistor. However, m is not necessarily an integer. In addition, M represents one metal element selected from Ga, Fe, Ni, Mn and Co, or a plurality of metal elements. For example, M may be Ga, or may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. Further, in the oxide semiconductor, in addition to the metal element contained as M, Fe, Ni or other transition metal element, or an oxide of the transition metal may be contained as an impurity element. In the present specification _{, among the oxide semiconductor layers having a structure represented by InMO 3} (ZnO) _m (m> 0), an oxide semiconductor having a structure containing Ga as M is oxidized by In-Ga-Zn-O system. It is called a physical semiconductor, and its thin film is also called an In-Ga-Zn-O-based non-single crystal film.

In addition to the above, In-Sn-Zn- is also used as an oxide semiconductor applied to the oxide semiconductor layer.
O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, S
n-Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al
−Zn—O-based, In—O-based, Sn—O-based, and Zn—O-based oxide semiconductors can be applied. Further, the oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx (X> 0)) that inhibits crystallization in the oxide semiconductor layer, it is possible to prevent crystallization when heat treatment is performed after the formation of the oxide semiconductor layer during the manufacturing process. can do. The oxide semiconductor layer is preferably in an amorphous state, and may be partially crystallized.

Further, depending on the heat treatment conditions or the material of the oxide semiconductor layer, the oxide semiconductor layer may change from an amorphous state to a microcrystalline film or a polycrystalline film. Even in the case of a microcrystal film or a polycrystalline film, switching characteristics can be obtained as a TFT.

It is possible to fabricate and provide a thin film transistor having a small fluctuation range of off-current and stable electrical characteristics. Therefore, it is possible to provide a semiconductor device having a thin film transistor having good electrical characteristics and good reliability.

The figure explaining the manufacturing process of the semiconductor device. The figure explaining the semiconductor device. The figure which shows the analysis method and hydrogen concentration in an oxide semiconductor layer. The graph which shows the off-current characteristic of the thin film transistor of Example 1. FIG. The figure which shows the cross-sectional structure used for the calculation of a semiconductor device. The figure explaining the structure assumed in the calculation of a semiconductor device. The figure explaining the block diagram of the semiconductor device. The figure explaining the structure and operation of the signal line drive circuit. A circuit diagram showing the configuration of a shift register. A configuration and timing chart illustrating the operation of the shift register. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the pixel equivalent circuit of the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. A circuit diagram showing the configuration of a semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. A circuit diagram showing the configuration of a semiconductor device. The figure which shows the example of the electronic book. The figure which shows the example of a television apparatus and a digital photo frame. The figure which shows the example of the gaming machine. The figure which shows the example of the portable computer and the mobile phone. The figure explaining the calculation result of the semiconductor device. The figure explaining the calculation result of the semiconductor device. The figure explaining the calculation result of the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be changed in various ways. Further, the present invention is not construed as being limited to the description contents of the embodiments shown below.

(Embodiment 1)
In this embodiment, one embodiment of the method for manufacturing the thin film transistor 150 shown in FIG. 1 (E) will be described with reference to FIGS. 1 (A) to 1 (E), which are cross-sectional views of the thin film transistor manufacturing process. Note that FIG. 1F is a top view of the thin film transistor 150 shown in FIG. 1E. The thin film transistor 150 is one of the bottom gate structures called a channel etch type.

First, in order to form a metal conductive film on the substrate 100, which is a substrate having an insulating surface, and process it into a desired shape, a photolithography step and an etching step are performed using a photomask to provide a gate electrode layer 101. The resist mask may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by the inkjet method,
Manufacturing cost can be reduced.

As the substrate 100, it is preferable to use a glass substrate. As the glass substrate used as the substrate 100, when the temperature of the subsequent heat treatment is high, it is preferable to use a glass substrate having a strain point of 730 ° C. or higher. Further, for the substrate 100, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and bariumborosilicate glass are used. By containing a large amount of barium oxide (BaO) as compared with boric acid, more practical heat-resistant glass can be obtained.
_Therefore, it is preferred that from B 2 _{O 3} is used a glass substrate containing more BaO.

Instead of the above substrate 100, a substrate made of an insulator such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used.

Further, an insulating film serving as a base film may be provided between the substrate 100 and the gate electrode layer 101. The undercoat film has a function of preventing the diffusion of impurity elements from the substrate 100, and has a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride film, or a silicon nitride film. Can be formed.

By impregnating the base film with halogen elements such as chlorine and fluorine, the function of preventing the diffusion of impurity elements from the substrate 100 can be further enhanced. As for the concentration of halogen elements contained in the base film, the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometer) is 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × 10 ²⁰ atoms / cm ³ or less. do it.

A metal conductive film can be used as the gate electrode layer 101. As the material of the metal conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above-mentioned elements as a component, an alloy in which the above-mentioned elements are combined, or the like is used. preferable. For example, a three-layer laminated structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminate in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer. It is preferable to have a structure. Of course, the metal conductive film may have a single layer, a two-layer structure, or a laminated structure of four or more layers.

Next, the gate insulating layer 102 is formed on the gate electrode layer 101.

The gate insulating layer 102 can be formed by using a plasma CVD method, a sputtering method, or the like to form a silicon oxide layer, a silicon nitride layer, a silicon nitride layer, or a silicon nitride layer in a single layer or in a laminated manner. _{For example, plasma CV using SiH 4} , oxygen and nitrogen as the film forming gas.
The silicon oxide layer may be formed by the D method. The film thickness of the gate insulating layer 102 is 100 nm.
In the case of lamination, for example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. And.

Also, before the film formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, or helium, neon, etc.)
The gate insulating layer 102 may be obtained by performing heat treatment (400 ° C. or higher and less than the distortion point of the substrate) under (argon or the like) to remove impurities such as hydrogen and water contained in the layer.

Next, on the gate insulating layer 102, the film thickness is 5 nm or more and 200 nm or less, preferably 10 nm.
An oxide semiconductor film having a diameter of 50 nm or less is formed. Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film is in an amorphous state, so that the film thickness is preferably as thin as 50 nm or less. By reducing the film thickness of the oxide semiconductor film, it is possible to prevent crystallization when heat treatment is performed after the formation of the oxide semiconductor layer.

Before forming the oxide semiconductor film by the sputtering method, it is preferable to introduce argon gas to generate plasma and perform reverse sputtering to remove dust adhering to the surface of the gate insulating layer 102. .. Inverse sputtering is a method in which a voltage is applied to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the target side, and the substrate surface is exposed to plasma to modify the surface. In addition, nitrogen, helium or the like may be used instead of the argon atmosphere.

The oxide semiconductor film is an In-Ga-Zn-O-based non-single crystal film, In-Sn-Zn-O-based film, In.
-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-
Zn-O system, In-Ga-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O
A system, In—O system, Sn—O system, or Zn—O system oxide semiconductor film is used. In the present embodiment, for example, a film is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target. Further, the oxide semiconductor film is formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. Can be done. When using the sputtering method,
Film formation is performed using a target containing SiO _{2 in an amount} of 2% by weight or more and 10% by weight or less, the oxide semiconductor film is impregnated with SiOx (X> 0) that inhibits crystallization, and dehydrogenation or dehydration is performed in a later step. It is preferable to prevent crystallization during heat treatment for dehydrogenation. It is preferable to use a pulsed direct current (DC) power source as the power source because dust can be reduced and the film thickness distribution becomes uniform.

The relative density of the metal oxide in the metal oxide target is preferably 95% or more, more preferably 99% or more. As a result, the concentration of impurities in the formed oxide semiconductor film can be reduced, and a thin film transistor having high electrical characteristics or reliability can be obtained.
In this embodiment, a metal oxide target having a relative density of metal oxides of 97% is used.

The sputtering method includes an RF sputtering method in which a high-frequency power source is used as a power source for sputtering, a DC sputtering method in which a DC power source is used, and a pulse DC sputtering method in which a bias is applied in a pulsed manner. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

There is also a multi-dimensional sputtering device that can install a plurality of targets made of different materials. The multi-dimensional sputtering apparatus can form a laminated film of different material films in the same chamber, or can simultaneously discharge a plurality of types of materials in the same chamber to form a film.

Further, there are a sputtering apparatus using a magnetron sputtering method having a magnet mechanism inside the chamber and a sputtering apparatus using an ECR sputtering method using plasma generated by using microwaves without using glow discharge.

Further, as a film forming method using a sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted to form a thin film of the compound during film formation, or a voltage is applied to a substrate during film formation. There is also a bias sputtering method.

Further, the gate insulating layer 102 and the oxide semiconductor film may be continuously formed without being exposed to the atmosphere. By forming the film without exposing it to the atmosphere, each laminated interface can be formed without being contaminated by atmospheric components such as water and hydrocarbons and impurity elements suspended in the atmosphere, so that the characteristics of the thin film transistor vary. Can be reduced.

Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 103 by a photolithography step (see FIG. 1 (A)). Further, the resist mask for forming the island-shaped oxide semiconductor layer 103 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, so that the manufacturing cost can be reduced.

Next, the first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 103.
The temperature of the first heat treatment for dehydration or dehydrogenation is 350 ° C. or higher and 750 ° C. or lower, preferably 425 ° C. or higher. If the temperature is 425 ° C. or higher, the heat treatment time may be 1 hour or less, but if the temperature is lower than 425 ° C., the heat treatment time is longer than 1 hour. for example,
After introducing the substrate into an electric furnace, which is one of the heat treatment devices, and heat-treating the oxide semiconductor layer 103 in a nitrogen atmosphere, water or water to the oxide semiconductor layer 103 is not exposed to the atmosphere. The oxide semiconductor layer 103 can be obtained by preventing the remixing of hydrogen. In the present embodiment, the same furnace is used from the heating temperature T for dehydrating or dehydrogenating the oxide semiconductor layer 103 to a sufficient temperature so that water does not enter again, specifically, higher than the heating temperature T. Slowly cool in a nitrogen atmosphere until the temperature drops to 100 ° C. or higher. Further, the dehydrogenation or dehydrogenation is performed in an inert gas atmosphere (helium, neon, argon, etc.) without being limited to the nitrogen atmosphere.

The first heat treatment performs atomic-level rearrangement of the oxide semiconductors constituting the oxide semiconductor layer 103. The first heat treatment is important in that it can release the strain that hinders the movement of carriers in the oxide semiconductor layer 103.

In the first heat treatment, it is preferable that nitrogen, or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon to be introduced into the heat treatment apparatus is 6N (99.99999%) or more.
It is preferably 7N (99.999999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

Further, the heat treatment device for the first heat treatment is not limited to the electric furnace, and may include a device for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, G
RTA (Gas Rapid Thermal Anneal) device, LRTA (Lam)
RTA (Rapid The) such as pRapid Thermal Anneal equipment
An rmal Anneal) device can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. The GRTA device is a device that performs heat treatment using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize to become a microcrystalline film or a polycrystalline film. Here, the oxide semiconductor layer may be a microcrystal film having a crystallization rate of 80% or more. Further, depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may have no crystals.

Further, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 103. In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography step is performed.

Here, the results of hydrogen concentration analysis with and without dehydrogenation in the oxide semiconductor layer will be described. FIG. 3A is a schematic cross-sectional structure of the sample used in this analysis. An oxide nitriding insulating layer 401 is formed on a glass substrate 400 by a plasma CVD method, and the oxide nitriding insulating layer 4 is formed.
An In-Ga-Zn-O-based oxide semiconductor layer 402 having an In-Ga-Zn-O oxide semiconductor layer 402 formed on the 01 at about 40 nm was prepared. The prepared sample was divided, one was not dehydrogenated, and the other was dehydrogenated at 650 ° C. for 6 minutes in a nitrogen atmosphere by the GRTA method. The effect of dehydrogenation by heat treatment was investigated by measuring the hydrogen concentration in the oxide semiconductor layer for each sample.

The measurement of hydrogen concentration in the oxide semiconductor layer is performed by secondary ion mass spectrometry (SIMS: Seconda).
Analysis was performed on ry Ion Mass Spectroscopy). FIG. 3B is a SIMS analysis result showing the hydrogen concentration distribution in the film thickness direction in the oxide semiconductor layer. The horizontal axis indicates the depth from the sample surface, and the position at the left end at a depth of 0 nm corresponds to the outermost surface of the sample (the outermost surface of the oxide semiconductor layer). The analysis direction 403 shown in FIG. 3A indicates the analysis direction of the SIMS analysis. The analysis was performed in the direction from the outermost surface of the oxide semiconductor layer toward the glass substrate 400. That is, on the horizontal axis of FIG. 3B, the direction was from the left end to the right end. FIG. 3 (B
) Indicates the hydrogen concentration in the sample at a specific depth and the oxygen ionic strength on the logarithmic axis.

In FIG. 3B, the hydrogen concentration profile 412 shows the hydrogen concentration profile in the oxide semiconductor layer that has not been dehydrogenated, and the hydrogen concentration profile 413 is after dehydrogenation by heat treatment. The hydrogen concentration profile in the oxide semiconductor layer is shown. The oxygen ionic strength profile 411 shows the oxygen ionic strength acquired at the same time when the hydrogen concentration profile 412 was measured. Since there is no extreme fluctuation in the oxygen ion intensity profile 411 and a substantially constant ionic strength is obtained, it can be seen that the SIMS analysis is performed accurately. The oxygen ionic strength was also measured at the time of measuring the hydrogen concentration profile 413, and a substantially constant ionic strength was also obtained here. The hydrogen concentration profile 412 and the hydrogen concentration profile 413 are quantified using a standard sample prepared from the same In-Ga-Zn-O oxide semiconductor layer as the sample.

It is known that it is difficult for SIMS analysis to accurately obtain data in the vicinity of the sample surface or in the vicinity of the interface between laminated films of different materials due to its principle. In this analysis, it is considered that accurate data cannot be obtained from the outermost surface of the sample to a depth of about 15 nm, so the depth is 15 n.
Evaluation was made using the profile after m.

From the hydrogen concentration profile 412, hydrogen is about 3 × 10 ²⁰ atoms / cm ³ or more, about 5 × 10 ²⁰ atoms / cm ³ or less, and an average hydrogen concentration of about 4 in the non-dehydrogenated oxide semiconductor layer. × 10 ²⁰ atoms / cm ³ It can be seen that it is contained. Further, from the hydrogen concentration profile 413, the average hydrogen concentration in the oxide semiconductor layer was reduced to about 2 × by dehydrogenation.
It can be seen that the amount can be reduced to ^{10 19} atoms / cm ^3.

By this analysis, the hydrogen concentration could be reduced by SIMS analysis of the sample that had been heat-treated at 650 ° C for 6 minutes in a nitrogen atmosphere by the GRTA method, so dehydrogenation from the oxide semiconductor layer was confirmed in this heat treatment step. did it.

Next, a second heat treatment is performed. The temperature of the second heat treatment is 100 ° C. or higher and lower than the temperature of the first heat treatment. For example, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and under an atmospheric atmosphere,
Alternatively, heat treatment is performed in an oxygen atmosphere.

Next, a conductive film for forming the source electrode layer and the drain electrode layer is formed on the gate insulating layer 102 and the oxide semiconductor layer 103.

The gate electrode layer 101 is used as a conductive film for forming the source electrode layer and the drain electrode layer.
Similarly, a metal conductive film can be used. Materials for the metal conductive film include Al, Cr,
It is preferable to use an element selected from Cu, Ta, Ti, Mo, and W, an alloy containing the above-mentioned elements as a component, an alloy in which the above-mentioned elements are combined, and the like. For example, a three-layer laminated structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminate in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer. It is preferable to have a structure. Of course, the metal conductive film has a single-layer or two-layer structure, or 4
It may have a laminated structure of more than one layer.

The source electrode layer 105a and the drain electrode layer 105b are formed from the conductive film for forming the source electrode layer and the drain electrode layer by a photolithography step using a photomask (see FIG. 1 (B)). Further, at this time, a part of the oxide semiconductor layer 103 is also etched to become the oxide semiconductor layer 103 having a groove (recess).

The resist mask for forming the source electrode layer 105a and the drain electrode layer 105b may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, so that the manufacturing cost can be reduced.

Further, an oxide conductive layer having a resistance lower than that of the oxide semiconductor layer 103 may be formed between the oxide semiconductor layer 103 and the source electrode layer 105a and the drain electrode layer 105b. With such a laminated structure, the withstand voltage of the thin film transistor can be improved. Specifically, the carrier concentration of the oxide conductive layer having low resistance is, for example, 1 × 10 ²⁰ / cm ³ or more and 1 × 10.
Preferably in the range of from ²¹ / cm ³ or less.

Next, the gate insulating layer 102, the oxide semiconductor layer 103, the source electrode layer 105a, and the drain electrode layer 105b are covered to form an insulating layer 107 in contact with a part of the oxide semiconductor layer 103 (.
See FIG. 1 (C)). The insulating layer 107 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as a CVD method or a sputtering method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer 107. Here, the insulating layer 107 is formed by using a sputtering method. The insulating layer 107 formed in contact with a part of the oxide semiconductor layer 103 ^{does not contain impurities such as water, hydrogen ions, oxygen ions, and OH −,} and is an inorganic substance that blocks the invasion of these from the outside. An insulating film can be used, and typically a silicon oxide film, a silicon nitride film, a silicon nitride film, a gallium oxide film, an aluminum oxide film, an aluminum nitride film, or an aluminum nitride film can be used.

Further, the insulating layer 107 may have a structure in which a silicon nitride film or an aluminum nitride film is laminated on a silicon oxide film, a silicon nitride film, an aluminum oxide film or an aluminum nitride film. In particular, the silicon nitride film is preferable because it does not contain impurities such as water, hydrogen ions, oxygen ions, and OH ^−, and it is easy to block the invasion of these from the outside.

The substrate temperature at the time of film formation of the insulating layer 107 may be room temperature or higher and 300 ° C. or lower, and the film formation of the silicon oxide film by the sputtering method is performed in a noble gas (typically argon) atmosphere, an oxygen atmosphere, or. It can be carried out in a noble gas (typically argon) and oxygen atmosphere. Further, a silicon oxide target or a silicon target can be used as the target.
For example, using a silicon target, silicon oxide can be formed by a sputtering method in an oxygen atmosphere.

Then, a third heat treatment is performed. The third heat treatment is performed at 100 ° C. or higher and lower than the temperature of the first heat treatment. For example, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the heat treatment is performed in a nitrogen atmosphere. The third heat treatment may be performed at any time as long as it is a step after the formation of the insulating layer 107.

From the above steps, the gate electrode layer 101 is provided on the substrate 100 which is a substrate having an insulating surface, the gate insulating layer 102 is provided on the gate electrode layer 101, and the oxide semiconductor layer is provided on the gate insulating layer 102. 103 is provided, and the source electrode layer 105 is provided on the oxide semiconductor layer 103.
a and a drain electrode layer 105b are provided, and a gate insulating layer 102 and an oxide semiconductor layer 103 are provided.
, A channel-etched thin film transistor 150 that covers the source electrode layer 105a and the drain electrode layer 105b and is provided with an insulating layer 107 that is in contact with a part of the oxide semiconductor layer 103.
Can be formed (see FIG. 1 (E)).

FIG. 1 (F) is a top view of the thin film transistor 150 shown in the present embodiment. Figure 1 (E
) Shows the cross-sectional structure of the X1-X2 portion of FIG. 1 (F). In FIG. 1 (F), L indicates the channel length and W indicates the channel width. Further, in A, the oxide semiconductor layer 103 is the source electrode layer 105a and the drain electrode layer 1 in the direction parallel to the channel width direction.
The length of the region that does not overlap with 05b is shown. Ls indicates the length at which the source electrode layer 105a and the gate electrode layer 101 overlap, and Ld indicates the length at which the drain electrode layer 105b and the gate electrode layer 10 overlap.
1 indicates the overlapping length.

In the present embodiment, the thin film transistor 150 has been described using a thin film transistor having a single gate structure, but if necessary, a thin film transistor having a multi-gate structure having a plurality of channel forming regions or a second gate electrode layer on the insulating layer 107. It can also be a thin film transistor having a structure having the above.

Further, in the present embodiment, a method for manufacturing the channel-etched thin film transistor 150 has been described, but the configuration of the present embodiment is not limited to this. A bottom contact type (also referred to as an inverted coplanar type) thin film transistor 160 having a bottom gate structure as shown in FIG. 2 (A) and a channel protection type (channel) having a channel protection layer 110 as shown in FIG. 2 (B). A thin film transistor 170 or the like (also referred to as a stop type) can be formed by using the same material and method. FIG. 2C shows another example of a channel-etched thin film transistor. The width of the gate electrode layer 101 of the thin film transistor 180 shown in FIG. 2C has a structure larger than the width of the oxide semiconductor layer 103.

The channel length of the thin film transistor (L in FIG. 1F) is defined by the distance between the source electrode layer 105a and the drain electrode layer 105b, but the channel length of the channel-protected thin film transistor is the direction in which carriers flow. It is defined by the width of the channel protection layer in the direction parallel to.

According to this embodiment, the off-current per 1 μm of the channel width of the thin film transistor having the oxide semiconductor layer ^{can be reduced to 1 × 10 -12} A or less.

Further, the channel length of the thin film transistor is in the range of 3 μm or more and 10 μm or less, or 1.
In the range of 5 μm or more and 100 μm or less, the channel width of the thin film transistor in the operating temperature range of -25 ° C to 150 ° C is 1 × 10 ^-12 A per off current per 1 μm.
It can be: The channel length of the thin film transistor is 1.5 μm or more, or 3 μm.
When it is m or more, the short channel effect can be suppressed, which is preferable.

Here, -25 ° C to 150 ° C using the thin film transistor having the cross-sectional structure shown in FIG. 4 (A).
The evaluation results of the thin film transistor characteristics under the above environment will be described.

First, a tungsten layer having a thickness of 100 nm is formed on the glass substrate 801 as the gate electrode layer 802, and 10 oxide nitride layers are formed on the gate electrode layer 802 as the gate insulating layer 803.
It is formed with a thickness of 0 nm, an In-Ga-Zn-O based oxide semiconductor layer 804 is formed with a thickness of 30 nm on the gate insulating layer 803, and a source electrode layer 805 is formed on the oxide semiconductor layer 804.
A titanium layer was formed as the drain electrode layer 806, and a thin film transistor was produced. The channel length L of the thin film transistor was 3 μm, and the channel width W was 20 μm.

Next, for the thin film transistor, the substrate temperature at the time of measurement was set to -25 ° C, 0 ° C, 25 ° C, 50.
The off-current of the thin film transistor at each substrate temperature (operating temperature) was measured at different temperatures of ° C., 100 ° C., and 150 ° C. The measurement of off-current characteristics is the voltage between the source and drain (
Hereinafter, the drain voltage (hereinafter referred to as Vd) was set to 10 V, and the voltage between the source and the gate (hereinafter referred to as the gate voltage or Vg) was set to −10 V.

FIG. 4B shows the off-current measurement results obtained in this measurement. The horizontal axis shows the substrate temperature (operating temperature) at the time of measuring the off-current of the thin film transistor on a linear scale, and the vertical axis shows the off-current (Off) at each substrate temperature on a log scale.

In the figure, "□" shown in FIG. 4 (B) shows the off-current when the amorphous silicon film is used as the semiconductor layer, and "●" in the figure shows the case where the oxide semiconductor film is used as the semiconductor layer. Shows off current.

From FIG. 4B, the off-current when the amorphous silicon film is used as the semiconductor layer is
It can be seen that the off-current increases as the substrate temperature at the time of measurement increases. It can be seen that the off-current when the oxide semiconductor film is used as the semiconductor layer is 1 pA, that is, 1 × 10 ^{-12 A or less even if the substrate temperature at the time of measurement rises.}

Here, the temperature dependence of the off-current (Ioff) will be considered below.

It is generally known that the off-current of a thin film transistor flows due to the generation of electrons and holes (hereinafter referred to as carrier generation) and the recombination of electrons and holes (hereinafter referred to as carrier recombination). .. Carrier recombination includes direct recombination in which electrons are excited from the valence band (Ev) to the conduction band (Ec) and excitation via localized levels (Et) in the bandgap (Eg). There is an indirect recombination that is done.

In the case of a semiconductor with a narrow bandgap, less thermal energy is required to excite electrons, so direct recombination and indirect recombination are likely to occur, but the bandgap (E) is similar to that of oxide semiconductors.
In the case of a semiconductor with a wide g), it is assumed that direct recombination and indirect recombination are unlikely to occur because a large amount of thermal energy is required to excite electrons.

Further, when the band gap is wide, the intrinsic carrier concentration of the semiconductor becomes extremely small, and the total number of carriers also becomes extremely small. As a result of the small total number of carriers, the probability of carrier generation and carrier recombination also decreases, so it is assumed that the off-current becomes small.

Attempts were made to calculate the temperature dependence of the off-current of the thin film transistors in semiconductors with different bandgap (Eg).

The structure assumed in the calculation is shown in FIG. 100n tungsten layer as gate electrode layer 701
It is formed with a thickness of m, an oxide nitride layer is formed with a thickness of 100 nm as a gate insulating layer 702 on the gate electrode layer 701, and a semiconductor layer 703 is formed with a thickness of 30 nm on the gate insulating layer 702. A thin film transistor in which the source electrode layer 704 and the drain electrode layer 705 are formed on the semiconductor layer 703 is assumed.

The size of the TFT was L / W = 10/1 μm. Semiconductor bandgap Eg = 1.1e
There are three types of V, 1.8 eV and 3.15 eV, and the oxide semiconductor has a bandgap Eg = 3.
It is assumed to be 15 eV. Further, assuming that the electron affinity χ = 4.3 eV, the source electrode layer 70
The work function of the metal used for 4 and the drain electrode layer 705 was assumed to be 4.3 eV, which is the same as the electron affinity of the oxide semiconductor. Further, the calculation was performed under three conditions of temperature T = 25 ° C., 100 ° C., and 150 ° C. For calculation, device simulation software A manufactured by Silvaco
I used two.

Considering that the defect level strongly affects the temperature characteristics in amorphous semiconductors, the calculation was performed when only direct recombination was assumed and when both direct recombination and indirect recombination were assumed. The level of indirect recombination was assumed to be in the center of the bandgap. The structures assumed in the calculation are shown in FIGS. 6 (A) and 6 (B). Calculations were made using two types: FIG. 6 (A), which assumes only direct recombination, and FIG. 6 (B), which assumes both direct recombination and indirect recombination.

In the drawings of FIGS. 6 (A) and 6 (B), “Ev” indicates a valence band, “Ec” indicates a conductor, and “Et” indicates a localized level. The solid line assumes carrier generation, and the broken line assumes carrier recombination.

The calculation result is shown in FIG. FIG. 29 shows the calculation result when the band gap (Eg) = 1.1 eV is assumed, and FIG. 29 (A) shows the calculation result when only the direct recombination is assumed.
(B) is a calculation result when both direct recombination and indirect recombination are assumed.

The spectrum 201 shown in FIG. 29 (A) is 25 ° C., and the spectrum 202 is 100 ° C.
, Spectrum 203 is a calculation result assuming 150 ° C., and is shown in FIG. 29 (B), spectrum 301 is 25 ° C., spectrum 302 is 100 ° C., and spectrum 303 is 150.
This is the calculation result assuming ℃.

The calculation result is shown in FIG. FIG. 30 shows the calculation result when the band gap (Eg) = 1.8 eV is assumed, and FIG. 30 (A) shows the calculation result when only the direct recombination is assumed.
(B) is a calculation result when both direct recombination and indirect recombination are assumed.

The spectrum 311 and the spectrum 312 shown in FIG. 30 (A) are at 25 ° C. and 100 ° C.
, Spectrum 313 is a calculation result assuming 150 ° C., and is shown in FIG. 30 (B), spectrum 321 is 25 ° C., spectrum 322 is 100 ° C., and spectrum 323 is 150.
This is the calculation result assuming ℃.

The calculation result is shown in FIG. FIG. 31 shows the calculation result when the band gap (Eg) = 3.15 eV is assumed, and FIG. 31 (A) shows the calculation result when only the direct recombination is assumed.
1 (B) is a calculation result assuming both direct recombination and indirect recombination.

The spectrum 451 and the spectrum 452 shown in FIG. 31 (A) are 25 ° C. and 100 ° C.
, Spectrum 453 is a calculation result assuming 150 ° C., and is shown in FIG. 31 (B), spectrum 461 is 25 ° C., spectrum 462 is 100 ° C., and spectrum 463 is 150.
This is the calculation result assuming ℃.

From FIG. 29 (B), assuming a bandgap (Eg) = 1.1 eV, ^{an off-current of 1 × 10 -13} A or more was confirmed at ^{25 ° C, and 1 × 10 -10 at 150 ° C.} An off-current of A or more has been confirmed, indicating that it is temperature-dependent.

From FIG. 30 (B), assuming that the band gap (Eg) = 1.8 eV, FIG. 29 (B)
Compared with the band gap (Eg) = 1.1 eV, the off current at 25 ° C is 1 × ^10-16.
At A or less and 150 ° C., ^{an off-current of 1 × 10 -13} A or less has been confirmed, indicating that there is temperature dependence.

From FIG. 31 (B), assuming that the band gap (Eg) = 3.15 eV, FIG. 29 (B).
) Bandgap (Eg) = 1.1eV, and the bandgap (Eg) of FIG. 30 (B).
) = 1.8 eV, at the calculated temperatures of 25 ° C, 100 ° C, and 150 ° C under the three conditions.
The off-current is 1 × 10 ^-16 A or less, and the result is that there is no temperature dependence.

As described above, in the case of a semiconductor having a narrow bandgap, since the thermal energy for exciting electrons is small, both direct recombination and indirect recombination are likely to occur, but the bandgap (Eg) is large like an oxide semiconductor. In the case of a wide semiconductor, a large amount of thermal energy is required to excite electrons, so calculation results are obtained in which both direct recombination and indirect recombination are unlikely to occur.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 2)
In the present embodiment, an example of producing at least a part of the drive circuit and a thin film transistor to be arranged in the pixel portion on the same substrate will be described below.

The thin film transistor to be arranged in the pixel portion is formed according to the first embodiment. Further, since the thin film transistor shown in the first embodiment is an n-channel type TFT, a part of the drive circuit that can be configured by the n-channel type TFT is formed on the same substrate as the thin film transistor of the pixel portion. ..

An example of a block diagram of the active matrix type display device is shown in FIG. 7 (A). The 5300 on the substrate of the display device includes a pixel unit 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304. A plurality of signal lines are extended from the signal line drive circuit 5304 and arranged in the pixel unit 5301, and the plurality of scan lines are arranged in the first scan line drive circuit 5.
It is arranged so as to extend from 302 and the scanning line drive circuit 5303. In the intersection region of the scanning line and the signal line, pixels having a display element are arranged in a matrix. Further, the substrate 5300 of the display device is FPC (Flexible Printed Circuit).
It is connected to the timing control circuit 5305 (also referred to as a controller or control IC) via a connection portion such as t).

In FIG. 7A, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on the same substrate 5300 as the pixel unit 5301. for that reason,
Since the number of external parts such as drive circuits is reduced, the cost can be reduced. Further, when the drive circuit is provided outside the substrate 5300, the number of connections at the connection portion can be reduced by extending the wiring, and the reliability or the yield can be improved.

The timing control circuit 5305 has, as an example, a start signal (GSP1) (start pulse) for the first scanning line driving circuit and a clock signal (GCK1) for the scanning line driving circuit with respect to the first scanning line driving circuit 5302. To supply. Further, the timing control circuit 5305 has, as an example, a second scanning line driving circuit start signal (GSP2) (also referred to as a start pulse) and a scanning line driving circuit clock signal (also referred to as a start pulse) with respect to the second scanning line driving circuit 5303. GCK2)
To supply. For the signal line drive circuit 5304, as an example, a signal line drive circuit start signal (SSP), a signal line drive circuit clock signal (SCK), and a video signal data (DAT).
A) (also simply referred to as a video signal) and a latch signal (LAT) shall be supplied. Each clock signal (GCK1, GCK2, SCK) may be a plurality of clock signals having different periods, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. It is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303.

In FIG. 7B, a circuit having a low drive frequency (for example, the first scanning line drive circuit 5302, the second
The scanning line drive circuit 5303) is formed on the same substrate 5300 as the pixel unit 5301, and the signal line drive circuit 5304 is formed on a substrate different from the pixel unit 5301. With this configuration, a drive circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility than a transistor using a single crystal semiconductor. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce the cost, or improve the yield.

The thin film transistor shown in the first embodiment is an n-channel TFT. FIG. 8 (A)
8 (B) shows and describes an example of the configuration and operation of the signal line drive circuit configured by the n-channel TFT.

The signal line drive circuit has a shift register 5601 and a switching circuit unit 5602. The switching circuit unit 5602 has a plurality of circuits called switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N are
Each has a plurality of transistors called thin film transistors 5603_1 to 5603_k (k is a natural number). The thin film transistors 5603_1 to 5603_k are n-channel TFTs.
An example is described.

The connection relationship of the signal line drive circuit will be described by taking the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each wired 5604_1.
It is connected to ~ 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the signal lines S1 to Sk, respectively. Thin film transistor 5603_1 to 5603_
The gate of k is connected to the wiring 5605_1.

The shift register 5601 outputs H level (also referred to as H signal, high power supply potential level) signals to the wirings 5605_1 to 5605_N in order, and the switching circuit 5602_1 to 56
It has a function to select 02_N in order.

The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk.
Function to control the continuity state (conduction between the first terminal and the second terminal), that is, wiring 5604_
It has a function of controlling whether or not a potential of 1 to 5604_k is supplied to the signal lines S1 to Sk.
As described above, the switching circuit 5602_1 has a function as a selector. Further, the thin film transistors 5603_1 to 5603_N are each wired 5604_1 to 5604_k.
A function of controlling the conduction state between the signal lines S1 to Sk, that is, wiring 5604_1 to 5604_k.
Has a function of supplying the potential of the above to the signal lines S1 to Sk. Thus, the thin film transistor 56
Each of 03_1 to 5603_N has a function as a switch.

Video signal data (DATA) is input to the wirings 5604_1 to 5604_k, respectively. The video signal data (DATA) is often image information or an analog signal corresponding to the image signal.

Next, the operation of the signal line drive circuit of FIG. 8A will be described with reference to the timing chart of FIG. 8B. 8 (B) shows the signals Sout_1 to Sout_N and the signal Vda.
An example of ta_1 to Vdata_k is shown. The signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, and the signals Vdata_1 to Vdata_k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line drive circuit corresponds to one gate selection period in the display device. As an example, one gate selection period is divided into period T1 to period TN. The periods T1 to TN are periods for writing the video signal data (DATA) to the pixels belonging to the selected row, respectively.

In addition, the bluntness of the signal waveform and the like of each configuration shown in the drawings and the like of the present embodiment may be exaggerated for the sake of clarification. Therefore, it should be added that it is not necessarily limited to that scale.

In the period T1 to the period TN, the shift register 5601 routes the H level signal 560.
Outputs in order from 5-1 to 5605_N. For example, in period T1, shift register 5
The 601 outputs a high level signal to the wiring 5605_1. Then, since the thin film transistors 5603_1 to 5603_k are turned on, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk become conductive. At this time, in the wirings 5604_1 to 5604_k,
Data (S1) to Data (Sk) are input. Data (S1) to Data (Sk)
) Are written to the pixels in the first column to the kth column among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k, respectively. In this way, in the periods T1 to TN, the video signal data (DATA) is written in order of k columns to the pixels belonging to the selected row.

As described above, the number of video signal data (DATA) or the number of wirings can be reduced by writing the video signal data (DATA) to the pixels in a plurality of columns.
Therefore, the number of connections with external circuits can be reduced. Further, by writing the video signal to the pixels in a plurality of columns, the writing time can be lengthened and the writing shortage of the video signal can be prevented.

The shift register 5601 and the switching circuit unit 5602 include the first embodiment.
It is possible to use a circuit composed of the thin film transistor shown in. In this case, the polarities of all the transistors of the shift register 5601 can be configured as an n-channel type.

Next, the configuration of the scanning line drive circuit will be described. The scanning line drive circuit has a shift register and a buffer. In some cases, it may have a level shifter. In the scanning line drive circuit, the clock signal (CK) and start pulse signal (SP) are stored in the shift register.
Is input to generate a selection signal. The generated selection signal is buffer amplified in the buffer and fed to the corresponding scan line. The gate electrode of the transistor of one line of pixels is connected to the scanning line. Then, since the transistors of one line of pixels must be turned on all at once, a buffer capable of passing a large current is used.

A form of a shift register used as a part of a scanning line driving circuit and / or a signal line driving circuit will be described with reference to FIGS. 9 and 10.

The shift registers of the scanning line drive circuit and the signal line drive circuit will be described with reference to FIGS. 9 and 10. The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 9A). The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 9A has
The first clock signal CK1 from the first wiring 11, the second clock signal CK2 from the second wiring 12, the third clock signal CK3 from the third wiring 13, and the fourth clock signal from the fourth wiring 14. CK4 is supplied. Further, in the first pulse output circuit 10_1, the fifth wiring 15
The start pulse SP1 (first start pulse) from is input. Further, in the nth pulse output circuit 10_n (n is a natural number of 2 or more and N or less) in the second and subsequent stages, the signal from the pulse output circuit of the first stage (referred to as the previous stage signal OUT (n-1)) (n is 2). The above natural number) is input. Further, in the first pulse output circuit 10_1, the third pulse output circuit 10 in the second stage after the second stage
In the signal from _3 or the nth pulse output circuit 10_n in the second and subsequent stages, a signal from the second (n + 2) pulse output circuit 10_n + 2 in the second and subsequent stages (referred to as the subsequent signal OUT (n + 2)) is input. Further, from the pulse output circuit of each stage, the first output signal OUT (1) (SR) for inputting to the pulse output circuit of the previous stage and / or the subsequent stage, and the second output signal OUT (1) to another wiring or the like. ) Is output. As shown in FIG. 9A, since the subsequent stage signal OUT (n + 2) is not input to the two final stages of the shift register, as an example, the second start pulse SP2 and the third stage are separately used. The start pulse SP3 may be input respectively.

The clock signal (CK) is a signal that repeats an H level and an L level (also referred to as an L signal or a low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are delayed by 1/4 cycle in order. In the present embodiment, the drive of the pulse output circuit is controlled by using the first clock signal (CK1) to the fourth clock signal (CK4). The clock signal is GCK according to the input drive circuit.
, SCK, but here it will be described as CK.

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are the first wiring 11
-It is electrically connected to any of the fourth wiring 14. For example, in FIG. 9B.
In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third The input terminal 23 is electrically connected to the third wiring 13. Further, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The input terminal 23 of 3 is electrically connected to the 4th wiring 14.

Each of the first pulse output circuits 10_1 to Nth pulse output circuits 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth. It is assumed that the input terminal 25, the first output terminal 26, and the second output terminal 27 are provided (see FIG. 9B). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third input terminal 23 is input to the second clock signal CK2. The third clock signal CK3 is input, the start pulse SP1 is input to the fourth input terminal 24, the subsequent signal OUT (3) is input to the fifth input terminal 25, and the first from the first output terminal 26. Output signals OUT (1) (SR) are output, and the second output terminal 27
The second output signal OUT (1) is output.

The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N can use a 4-terminal thin film transistor in addition to the 3-terminal thin film transistor. The transistor 28 shown in FIG. 9C means a 4-terminal thin film transistor described in the first embodiment.
It will be used below in drawings and the like. The transistor 28 is In by the first control signal G1 input to the first gate electrode and the second control signal G2 input to the second gate electrode.
It is an element that can perform electrical control between the terminal and the Out terminal.

The threshold voltage of the transistor 28 shown in FIG. 9C is such that gate electrodes are provided above and below the channel forming region of the transistor 28 via a gate insulating film to control the potential of the upper and / or lower gate electrodes. Can be controlled to a desired value.

Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. 9D.

The first pulse output circuit 10_1 includes the first transistor 31 to the thirteenth transistor 4
It has 3 (see FIG. 9 (D)). Further, in addition to the above-mentioned first input terminals 21 to 5 fifth input terminals 25, the first output terminal 26, and the second output terminal 27, the first high power supply potential VDD.
The first transistor 31 to the thirteenth transistor 4 from the power supply line 51 to which the power supply line 51 is supplied, the power supply line 52 to which the second high power supply potential VCS is supplied, and the power supply line 53 to which the low power supply potential VSS is supplied.
A signal or power supply potential is supplied to 3. Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 9D is such that the first power supply potential VDD> the second power supply potential VCS> the third power supply potential VSS.
The first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, but are VDD at the H level and V at the L level.
Suppose it is SS. By making the potential VCS of the power supply line 52 lower than the potential VDD of the power supply line 51, the potential applied to the gate electrode of the transistor can be suppressed low without affecting the operation, and the threshold value of the transistor can be suppressed. Shift can be reduced and deterioration can be suppressed. As shown in FIG. 9 (D), among the first transistors 31 to 13 transistors 43, the first transistor 31 and the sixth transistor 36 to the ninth transistor 39 are shown in FIG. 9 (C). ), It is preferable to use the 4-terminal transistor 28. The operation of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 is a transistor in which the potential of the node to which one of the source or drain electrodes is connected is required to be switched by the control signal of the gate electrode. Therefore, it is a transistor that can further reduce the malfunction of the pulse output circuit because the response to the control signal input to the gate electrode is fast (the rise of the on-current is steep). Therefore, the threshold voltage can be controlled by using the 4-terminal transistor 28 shown in FIG. 9C, and the pulse output circuit can further reduce malfunctions. Note that in FIG. 9C, the first
The control signal G1 and the second control signal G2 are the same control signal, but different control signals may be input.

In FIG. 9D, in the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (
The first gate electrode and the second gate electrode) are electrically connected to the fourth input terminal 24. In the second transistor 32, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is the fourth transistor 34. It is electrically connected to the gate electrode. In the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. In the fourth transistor 34, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. In the fifth transistor 35, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate is formed. The electrodes are electrically connected to the fourth input terminal 24. The first terminal of the sixth transistor 36 is the power supply line 5.
Electrically connected to 2, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (first gate electrode and second gate electrode).
Gate electrode) is electrically connected to the fifth input terminal 25. 7th transistor 3
In No. 7, the first terminal is electrically connected to the power supply line 52, the second terminal is electrically connected to the second terminal of the eighth transistor 38, and the gate electrodes (first gate electrode and second gate) The electrode) is electrically connected to the third input terminal 23. In the eighth transistor 38, the first terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrodes (first gate electrode and second gate electrode). Is the second input terminal 2
It is electrically connected to 2. In the ninth transistor 39, the first terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and the second terminal is the gate electrode of the third transistor 33 and the second terminal. It is electrically connected to the gate electrode of the tenth transistor 40, and the gate electrodes (the first gate electrode and the second gate electrode) are electrically connected to the power supply line 52. In the tenth transistor 40, the first terminal is the first input terminal 21.
The second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. Eleventh transistor 4
In No. 1, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the second transistor 32 and the fourth transistor. It is electrically connected to the gate electrode of 34. In the twelfth transistor 42, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27.
The gate electrode is electrically connected to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37. The first terminal of the thirteenth transistor 43 is the power supply line 53.
The second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37. Is connected.

In FIG. 9D, the gate electrode of the third transistor 33 and the tenth transistor 4
A node A is a connection point between the gate electrode of 0 and the second terminal of the ninth transistor 39.
Further, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, And the connection point of the eleventh transistor 41 with the gate electrode is a node B (see FIG. 10A).

The thin film transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region.
A current can flow through the drain region, the channel region, and the source region. here,
Since the source and drain change depending on the structure and operating conditions of the thin film transistor, it is difficult to limit which is the source or drain. Therefore, the region that functions as a source and a drain may not be called a source or a drain. In that case, as an example, they may be referred to as a first terminal and a second terminal, respectively.

Note that, in FIGS. 9D and 10A, a capacitive element may be separately provided to perform the bootstrap operation by putting the node A in a floating state. Further, in order to hold the potential of the node B, a capacitive element in which one electrode is electrically connected to the node B may be separately provided.

Here, the timing chart of the shift register including the plurality of pulse output circuits shown in FIG. 10 (A) is shown in FIG. 10 (B). When the shift register is a scanning line drive circuit, the period 61 in FIG. 10B corresponds to the vertical blanking interval, and the period 62 corresponds to the gate selection period.

As shown in FIG. 10A, by providing the ninth transistor 39 to which the second power supply potential VCS is applied to the gate, there are the following advantages before and after the bootstrap operation. ..

When the gate electrode does not have the ninth transistor 39 to which the second potential VCS is applied, when the potential of the node A rises due to the bootstrap operation, the potential of the source which is the second terminal of the first transistor 31 rises. The potential becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCS is applied to the gate electrode, the potential of the node A rises due to the bootstrap operation, but the second terminal of the first transistor 31 It is possible to prevent the potential from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced, so that the first stress is generated.
Deterioration of the transistor 31 can be suppressed.

It should be noted that the location where the ninth transistor 39 is provided is the second of the first transistor 31.
The configuration may be such that the terminal and the gate of the third transistor 33 are connected via the first terminal and the second terminal. In the case of the shift register including a plurality of pulse output circuits in the present embodiment, the ninth transistor 39 may be omitted in the signal line drive circuit having more stages than the scan line drive circuit, and the number of transistors is reduced. Is an advantage.

By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, it is possible to reduce the off-current of the thin film transistor and increase the on-current and field effect mobility, and the degree of deterioration. Therefore, it is possible to reduce malfunctions in the circuit. Further, the transistor using the oxide semiconductor has a smaller degree of deterioration of the transistor due to the application of a high potential to the gate electrode than the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCS, and the number of power supply lines running between the circuits can be reduced. The circuit can be miniaturized.

The gate electrode of the seventh transistor 37 (first gate electrode and second gate electrode)
The clock signal supplied by the third input terminal 23 and the clock signal supplied by the second input terminal 22 to the gate electrodes (first gate electrode and second gate electrode) of the eighth transistor 38 are Gate electrode of the seventh transistor 37 (first gate electrode and second gate electrode)
The clock signal supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38, and the third input terminal 23 to the gate electrode (first gate electrode and second gate electrode) of the eighth transistor 38.
The same effect is obtained even if the connection relationship is exchanged so that the clock signal is supplied by. In the shift register shown in FIG. 10A, the seventh transistor 37 and the eighth transistor 38 are both on, the seventh transistor 37 is off, the eighth transistor 38 is on, and then. By turning off the seventh transistor 37 and turning off the eighth transistor 38, the second input terminal 22 and the third input terminal 23 are turned off.
The decrease in the potential of the node B caused by the decrease in the potential of the node B occurs twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. It becomes. On the other hand, the shift register shown in FIG. 10 (A) is changed from the state in which both the seventh transistor 37 and the eighth transistor 38 are on as in the period of FIG. 10 (B).
The second input terminal 22 and the second input terminal 22 and the second transistor 38 are turned on by turning the seventh transistor 37 on and the eighth transistor 38 off, then turning the seventh transistor 37 off and turning the eighth transistor 38 off. The decrease in the potential of the node B caused by the decrease in the potential of the input terminal 23 of 3 can be reduced to one time due to the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode)
The clock signal supplied by the third input terminal to the gate electrode of the eighth transistor 38, and the clock signal supplied by the second input terminal to the gate electrode (first gate electrode and second gate electrode) of the eighth transistor 38. This is preferable because noise can be reduced by reducing the fluctuation of the potential of the node B.

In this way, the pulse output is configured so that the H level signal is periodically supplied to the node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level. It is possible to suppress the malfunction of the circuit.

By manufacturing the thin film transistor of the drive circuit by using the method of manufacturing the thin film transistor shown in the first embodiment, high-speed operation of the thin film transistor of the drive circuit unit can be realized and power saving can be achieved.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 3)
In the present embodiment, a case where a thin film transistor is produced and the thin film transistor is used for a pixel portion and further for a drive circuit to produce a semiconductor device (also referred to as a display device) having a display function will be described. Further, using the thin film transistor, a part or the whole of the drive circuit can be integrally formed on the same substrate as the pixel portion to form a system on panel.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose brightness is controlled by current or voltage in its category, and specifically, an inorganic EL (Electr).
o Luminescence), organic EL and the like are included. Further, a display medium whose contrast changes due to an electric action, such as electronic ink, can also be applied.

Further, the display device includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. Further, in the display device, the element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device is
Each of the plurality of pixels is provided with means for supplying a current to the display element. Specifically, the element substrate may be in a state in which only the pixel electrodes of the display element are formed, or after the conductive film to be the pixel electrodes is formed, the pixel electrodes are formed by etching. It may be in the previous state, and all forms apply.

The display device in the present specification refers to an image display device or a light source (including a lighting device). Also, a connector such as FPC (Flexible printed c)
A module with an ircuit) or TAB (Tape Implemented Bonding) tape or TCP (Tape Carrier Package) attached, a module with a printed wiring board at the end of a TAB tape or TCP, or a COG (Chip On Glass) method for the display element. The display device also includes all modules in which ICs (integrated circuits) are directly mounted.

In the present embodiment, an example of a liquid crystal display device as a semiconductor device according to the present invention is shown. First, the appearance and cross section of the liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. FIG. 11 shows a highly reliable thin film transistor 4010, 4011 and a liquid crystal element 4013 including an In—Ga—Zn—O-based non-single crystal film formed on the first substrate 4001 as a semiconductor layer, as a second substrate. Sealed with a sealing material 4005 between 4006,
It is a top view of the panel, and FIG. 11 (B) corresponds to a cross-sectional view taken along the line MN of FIGS. 11 (A1) and 11 (A2).

A sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. Further, a second substrate 4006 is provided on the pixel unit 4002 and the scanning line drive circuit 4004. Therefore, the pixel unit 4002 and the scanning line drive circuit 4004 are composed of the first substrate 4001, the sealing material 4005, and the second substrate 4006.
It is sealed together with the liquid crystal layer 4008. Further, a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Has been done.

The method of connecting the separately formed drive circuit is not particularly limited, and the COG method,
A wire bonding method, a TAB method, or the like can be used. FIG. 11 (A1)
Is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 11 (A2) shows.
This is an example of mounting the signal line drive circuit 4003 by the TAB method.

Further, the pixel unit 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004 have a plurality of thin film transistors, and in FIG. 11B, the thin film transistor 4010 included in the pixel unit 4002 and scanning are performed. Thin film transistor 401 included in line drive circuit 4004
1 and are illustrated. Insulating layers 4020, 40 on thin film transistors 4010, 4011
21 is provided.

As the thin film transistors 4010 and 4011, highly reliable thin film transistors including the oxide semiconductor layer shown in the first embodiment can be applied. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

On the insulating layer 4021, the conductive layer 4040 is provided at a position overlapping the channel forming region of the oxide semiconductor layer of the thin film transistor 4011 for the drive circuit. By providing the conductive layer 4040 at a position overlapping the channel formation region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test. again,
The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011 or may have a different potential, and may function as a second gate electrode layer. In addition, the conductive layer 4
The potential of 040 may be GND, 0V, or a floating state.

Further, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is the second substrate 40.
It is formed on 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap each other corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 are provided with an insulating layer 4032 and an insulating layer 4033 that function as alignment films, respectively, and sandwich the liquid crystal layer 4008 via the insulating layer 4032 and the insulating layer 4033, respectively.

As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, and plastic can be used. As plastic, FRP (Fiberglass-Reinforced Plastics) plate, PV
F (polyvinyl fluoride) film, polyester film or acrylic resin film can be used. Further, a sheet having a structure in which an aluminum foil is sandwiched between a PVC film or a polyester film can also be used.

Further, the spacer 4035 is a columnar spacer obtained by selectively etching the insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. .. A spherical spacer may be used. Further, the counter electrode layer 4
031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Using the common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected via the conductive particles arranged between the pair of substrates. The conductive particles are contained in the sealing material 4005.

Further, a liquid crystal display showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require an orientation treatment, and has a small viewing angle dependence.

The liquid crystal display device shown in the present embodiment is an example of a transmissive liquid crystal display device, but the liquid crystal display device can be applied to either a reflective liquid crystal display device or a semi-transmissive liquid crystal display device.

Further, in the liquid crystal display device shown in the present embodiment, an example is shown in which a polarizing plate is provided on the outside (visual side) of the substrate, a colored layer is provided on the inside, and an electrode layer used for the display element is provided in this order. It may be provided inside. Further, the laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be appropriately set depending on the material of the polarizing plate and the colored layer and the manufacturing process conditions. Further, if necessary, a light-shielding film that functions as a black matrix may be provided.

Further, in the present embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective film or a flattening insulating film of the thin film transistor. It is configured to be covered with. The protective film is for preventing the invasion of pollutant impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and a dense film is preferable. The protective film is a silicon oxide film, using the sputtering method.
It may be formed by a single layer or a laminate of a silicon nitride film, a silicon nitride film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum nitride film, or an aluminum nitride film. In the present embodiment, an example in which the protective film is formed by a sputtering method is shown, but the protective film may be formed by various methods without particular limitation.

Here, an insulating layer 4020 having a laminated structure is formed as a protective film. Here, the insulating layer 402
As the first layer of 0, a silicon oxide film is formed by using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing hilocation of the aluminum film used as the source electrode layer and the drain electrode layer.

In addition, an insulating layer is formed as the second layer of the protective film. Here, as the second layer of the insulating layer 4020, a silicon nitride film is formed by using a sputtering method. When a silicon nitride film is used as the protective film, it is possible to prevent ions such as sodium from invading the semiconductor region and changing the electrical characteristics of the TFT.

Further, after forming the protective film, the semiconductor layer may be annealed (300 ° C. to 400 ° C.).

In addition, an insulating layer 4021 is formed as a flattening insulating film. As the insulating layer 4021, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials)
, Siloxane resin, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. The insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

The siloxane-based resin is Si—O—S formed using a siloxane-based material as a starting material.
Corresponds to a resin containing an i-bond. As the substituent of the siloxane-based resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. Moreover, the organic group may have a fluoro group.

The method for forming the insulating layer 4021 is not particularly limited, and depending on the material thereof, a sputtering method, S.
OG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater and the like can be used. When the insulating layer 4021 is formed by using a material liquid, the semiconductor layer may be annealed (300 ° C. to 400 ° C.) at the same time in the baking step. By combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer, it is possible to efficiently manufacture a semiconductor device.

The pixel electrode layer 4030 and the counter electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, and indium oxide containing titanium oxide.
Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO),
A translucent conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed by using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed by using the conductive composition has a sheet resistance of 10000 Ω / □ or less and a light transmittance of 7 at a wavelength of 550 nm.
It is preferably 0% or more. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be mentioned.

Further, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or a pixel unit 4
Various signals and potentials given to 002 are supplied from FPC4018.

In the present embodiment, the connection terminal electrode 4015 is the pixel electrode layer 40 included in the liquid crystal element 4013.
Formed from the same conductive film as 30, the terminal electrode 4016 is a thin film transistor 4010, 40.
It is formed of the same conductive film as the source electrode layer and the drain electrode layer of No. 11.

The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

Further, FIG. 11 shows an example in which the signal line drive circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line drive circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

FIG. 12 shows an example in which a TFT substrate 2600 is used in a liquid crystal display module corresponding to one form of a semiconductor device.

FIG. 12 is an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, a colored layer 2605, and a polarizing plate are provided between them. 2606 is provided to form a display area. The colored layer 2605 is necessary for color display, and in the case of the RGB method, red, green,
A colored layer corresponding to each blue color is provided corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged outside the TFT substrate 2600 and the opposing substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit section 2608 of the TFT board 2600 by the flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. There is. Also with a polarizing plate
It may be laminated with a retardation plate between it and the liquid crystal layer.

The liquid crystal display module has TN (Twisted Nematic) mode and IPS (I).
n-Plane-Switching mode, FFS (Fringe Field S)
(witching) mode, MVA (Multi-domain Vertical A)
lightweight mode, PVA (Patterned Vertical Alig)
nment), ASM (Axially Symmetrically named Mic)
ro-cell) mode, OCB (Optical Compensated Bire)
fringence mode, FLC (Ferroelectric Liquid C)
rhythm mode, AFLC (Antiferroelectric Liquid)
Crystal) mode and the like can be used.

Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device.

By producing a thin film transistor in the pixel portion of the liquid crystal display device using the thin film transistor shown in the first embodiment, it is possible to suppress an increase in power consumption due to fluctuations in the off-current of the thin film transistor in each pixel.

Further, by manufacturing the thin film transistor of the drive circuit of the liquid crystal display device by using the method of manufacturing the thin film transistor shown in the first embodiment, high-speed operation of the thin film transistor of the drive circuit unit can be realized and power saving can be achieved.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 4)
An example of electronic paper is shown as a form of a semiconductor device.

The thin film transistor of the first embodiment may be used for electronic paper for driving electronic ink by utilizing an element electrically connected to a switching element. Electronic paper is also called an electrophoresis display device (electrophoresis display), and has the advantages of being as easy to read as paper, having lower power consumption than other display devices, and being able to have a thin and light shape. ing.

The electrophoresis display may take various forms, but is a microcapsule containing a first particle having a positive charge and a second particle having a negative charge dispersed in a solvent or a solute. By applying an electric charge to the microcapsules, the particles in the microcapsules are moved in opposite directions, and only the color of the particles aggregated on one side is displayed. The first particle or the second particle contains a dye and does not move in the absence of an electric field. Further, the color of the first particle and the color of the second particle are different (including colorless).

In this way, in the electrophoretic display, a substance having a high dielectric constant moves to an electric field region having a high dielectric constant.
It is a display that utilizes the so-called dielectrophoretic effect.

The microcapsules dispersed in a solvent are called electronic inks, and the electronic inks can be printed on the surface of glass, plastic, cloth, paper, or the like. In addition, color display is also possible by using a color filter or particles having a dye.

Further, if a plurality of the above microcapsules are appropriately arranged on the active matrix substrate so as to be sandwiched between the two electrodes, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. can. For example, an active matrix substrate obtained by the thin film transistor of the first embodiment can be used.

The first particles and the second particles in the microcapsules are a conductor material, an insulator material, and the like.
A semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a kind of material selected from a magnetic electrophoresis material, or a composite material thereof may be used.

FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the semiconductor device can be manufactured in the same manner as the thin film transistor shown in the first embodiment, and is a highly reliable thin film transistor including an oxide semiconductor layer.

The electronic paper of FIG. 13 is an example of a display device using the twist ball display method. In the twist ball display method, spherical particles painted in black and white are arranged between a first electrode layer and a second electrode layer, which are electrode layers used for a display element, and the first electrode layer and the first electrode layer are arranged. This is a method of displaying by controlling the orientation of spherical particles by causing a potential difference in the electrode layer of 2.

The thin film transistor 581 is a thin film transistor having a bottom gate structure, and is covered with an insulating film 583 in contact with the semiconductor layer. The source electrode layer or drain electrode layer of the thin film transistor 581 is in contact with the first electrode layer 587 by an opening formed in the insulating layer 585 and is electrically connected. Spherical particles 58 having a black region 590a and a white region 590b between the first electrode layer 587 and the second electrode layer 588 and containing a cavity 594 surrounded by a liquid.
9 is provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (
See FIG. 13). The first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. The common connection portion can be used to electrically connect the second electrode layer 588 and the common potential line via conductive particles arranged between the pair of substrates.

It is also possible to use an electrophoretic element instead of the twist ball. A diameter of 10 μm to 20 containing a transparent liquid, positively charged white fine particles, and negatively charged black fine particles.
Use microcapsules of about 0 μm. The microcapsules provided between the first electrode layer and the second electrode layer have white fine particles and black fine particles in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer. You can go to and display white or black. A display element to which this principle is applied is an electrophoretic display element, which is generally called electronic paper. Since the electrophoresis display element has a higher reflectance than the liquid crystal display element, an auxiliary light is unnecessary, the power consumption is low, and the display unit can be recognized even in a dim place. Further, since it is possible to hold the image once displayed even when the power is not supplied to the display unit, a semiconductor device with a display function (simply a display device or a semiconductor provided with the display device) from the radio wave transmission source. Even when the device is moved away, the displayed image can be saved.

Through the above steps, highly reliable electronic paper can be produced as a semiconductor device.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 5)
An example of a light emitting display device as a semiconductor device is shown. As the display element included in the display device, a light emitting element using electroluminescence is used here. A light emitting element that utilizes electroluminescence is distinguished by whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are injected into the layer containing the luminescent organic compound from the pair of electrodes, respectively, and a current flows. Then, when those carriers (electrons and holes) are recombined, the luminescent organic compound forms an excited state, and when the excited state returns to the ground state, it emits light. From such a mechanism, such a light emitting element is called a current excitation type light emitting element.

The inorganic EL element is classified into a dispersed inorganic EL element and a thin film type inorganic EL element according to the element configuration. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is donor-acceptor recombination type light emission utilizing a donor level and an acceptor level. In the thin film type inorganic EL element, the light emitting layer is sandwiched between the dielectric layers, and the light emitting layer is sandwiched between the dielectric layers.
Furthermore, it has a structure in which it is sandwiched between electrodes, and the light emission mechanism is localized light emission that utilizes the inner-shell electronic transition of metal ions. Here, an organic EL element will be used as the light emitting element.

FIG. 14 is a diagram showing an example of a pixel configuration to which digital time gradation drive can be applied as an example of a semiconductor device.

The configuration of pixels to which digital time gradation drive can be applied and the operation of pixels will be described. Here, an example is shown in which two n-channel type transistors using an oxide semiconductor layer in the channel forming region are used in one pixel.

Pixel 6400 is a switching transistor 6401, a driving transistor 6402,
It has a light emitting element 6404 and a capacitive element 6403. Switching transistor 64
In 01, the gate is connected to the scanning line 6406, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is the gate of the driving transistor 6402. It is connected to the. The drive transistor 6402 is
The gate is connected to the power supply line 6407 via the capacitive element 6403, and the first electrode is the power supply line 640.
The second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404.
The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

A low power supply potential is set in the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a potential that satisfies the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 6407, and the low power supply potential is set to, for example, GND or 0V. Is also good. Since the potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 and a current is passed through the light emitting element 6404 to cause the light emitting element 6404 to emit light, the potential difference between the high power supply potential and the low power supply potential is the light emitting element 6404. Set each potential so that it is equal to or higher than the forward threshold voltage of.

The capacitive element 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the drive transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

Here, in the case of the voltage input voltage drive system, the gate of the drive transistor 6402 is
A video signal is input so that the drive transistor 6402 is fully turned on or off. That is, the driving transistor 6402 is operated in the linear region.
Since the drive transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the drive transistor 6402. In addition, in the signal line 6405,
Apply a voltage higher than (power supply line voltage + Vth of drive transistor 6402).

Further, when analog gradation drive is performed instead of digital time gradation drive, the same pixel configuration as in FIG. 14 can be used by changing the signal input method.

When performing analog gradation drive, the light emitting element 6404 is connected to the gate of the drive transistor 6402.
The forward voltage of + the voltage of Vth or more of the driving transistor 6402 is applied. Light emitting element 64
The forward voltage of 04 refers to a voltage at which a desired brightness is obtained, and includes at least a forward threshold voltage. By inputting a video signal such that the driving transistor 6402 operates in the saturation region, a current can be passed through the light emitting element 6404. In order to operate the drive transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the drive transistor 6402. By making the video signal analog, a current corresponding to the video signal can be passed through the light emitting element 6404 to drive the analog gradation.

The pixel configuration shown in FIG. 14 is not limited to this. For example, a switch, a resistance element, a capacitance element, a transistor, a logic circuit, or the like may be newly added to the pixel shown in FIG.

Next, the configuration of the light emitting element will be described with reference to FIG. Here, the driving TFT is n
The cross-sectional structure of the pixel will be described by taking the case of a mold as an example. The driving TFTs 7001, 7011, and 7021 used for the light emitting elements of FIGS. 15 (A), (B), and (C) can be manufactured in the same manner as the thin film transistor shown in the first embodiment, and the reliability including the oxide semiconductor layer can be produced. It is a high-quality thin film transistor.

The light emitting element may have at least one of the anode and the cathode transparent in order to extract light emission. Then, a thin film transistor and a light emitting element are formed on the substrate, and the top surface injection that extracts light emission from the surface opposite to the substrate, the bottom surface injection that extracts light emission from the surface on the substrate side, and the surface on the substrate side and the surface opposite to the substrate. There is a light emitting device having a double-sided injection structure that extracts light from the light emitting device, and the pixel configuration can be applied to a light emitting device having any injection structure.

A light emitting element having a bottom injection structure will be described with reference to FIG. 15 (A).

The cross-sectional view of a pixel is shown in the case where the driving TFT 7011 is n type, and the light emitted from the EL layer 7014 is emitted to the cathode 7013 side. In FIG. 15A, the cathode 7013 of the light emitting element 7012 is formed on the translucent conductive film 7017 electrically connected to the driving TFT 7011, and the EL layer 7014 and the anode 7015 are formed on the cathode 7013. Are stacked in order.
The translucent conductive film 7017 is electrically connected to the drain electrode layer of the driving TFT 7011 via a contact hole formed in the oxide insulating layer 7031.

Examples of the translucent conductive film 7017 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide ( Hereinafter, it is referred to as ITO.), Indium tin oxide, indium tin oxide to which silicon oxide is added, and other conductive conductive films having translucency can be used.

Although various materials can be used for the cathode 7013, materials having a small work function, for example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferable. In FIG. 15A, the film thickness of the cathode 7013 is such that light is transmitted (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the cathode 7013.

After laminating and forming a translucent conductive film and an aluminum film, the conductive film 7017 and the cathode 7013 may be selectively etched to form the translucent conductive film 7017 and the cathode 7013. In this case, the same mask is used. Can be etched, which is preferable.

The peripheral edge of the cathode 7013 is covered with a partition wall 7019. The partition wall 7019 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. It is preferable that the partition wall 7019 is formed by using a photosensitive resin material in particular, forming an opening on the cathode 7013, and forming the side wall of the opening so as an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7019, the step of forming the resist mask can be omitted.

Further, the EL layer 7014 formed on the cathode 7013 and the partition wall 7019 may be composed of a single layer or may be configured such that a plurality of layers are laminated. EL layer 70
When 14 is composed of a plurality of layers, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order on the cathode 7013. It is not necessary to provide all of these layers.

Further, the stacking order is not limited, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order on the cathode 7013. However, when comparing the power consumption, it is preferable to stack the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer in this order on the cathode 7013 because the power consumption is low.

Further, as the anode 7015 formed on the EL layer 7014, various materials can be used, but materials having a large work function such as titanium nitride, ZrN, Ti, W, Ni, Pt, and the like can be used.
Transparent conductive materials such as Cr and the like, ITO, IZO (indium oxide zinc oxide), and ZnO are preferable. Further, a shielding film 7016, for example, a metal that blocks light, a metal that reflects light, or the like is formed on the anode 7015. In this embodiment, an ITO film is used as the anode 7015, and a Ti film is used as the shielding film 7016.

At least the region of the cathode 7013 and the anode 7015 sandwiching the EL layer 7014 corresponds to the light emitting element 7012. In the case of the element structure shown in FIG. 15A, the light emitted from the light emitting element 7012 is emitted to the cathode 7013 side as shown by an arrow.

Note that FIG. 15A shows an example in which a conductive film having translucency is used as the gate electrode layer, and the light emitted from the light emitting element 7012 passes through the color filter layer 7033 and is a driving TFT 7011. It is injected through the gate electrode layer and the source electrode layer of. TF
A light-transmitting conductive film can be used as the gate electrode layer and the source electrode layer of T7011, and the aperture ratio can be improved.

The color filter layer 7033 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

Further, the color filter layer 7033 is covered with the overcoat layer 7034, and the insulating layer 7 is further covered.
Cover with 035. Although the overcoat layer 7034 is shown with a thin film thickness in FIG. 15A, the overcoat layer 7034 has a function of flattening the unevenness caused by the color filter layer 7033.

Further, the contact holes formed in the insulating layer 7035 and reaching the drain electrode layer are
It is arranged at a position overlapping the partition wall 7019. In FIG. 15A, the aperture ratio can be improved by arranging the layout in which the contact hole reaching the drain electrode layer and the partition wall 7019 are overlapped.

Next, a light emitting element having a double-sided injection structure will be described with reference to FIG. 15 (B).

In FIG. 15B, the cathode 7023 of the light emitting element 7022 is formed on the translucent conductive film 7027 electrically connected to the driving TFT 7021, and the cathode 70
The EL layer 7024 and the anode 7025 are laminated on the 23 in this order. The translucent conductive film 7027 is the TFT 70 via a contact hole formed in the oxide insulating layer 7041.
It is electrically connected to the drain electrode layer of 21.

Examples of the translucent conductive film 7027 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide ( Hereinafter, it is referred to as ITO.), Indium tin oxide, indium tin oxide to which silicon oxide is added, and other conductive conductive films having translucency can be used.

Although various materials can be used for the cathode 7023, materials having a small work function, for example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferable. In the present embodiment, the film thickness of the cathode 7023 is such that light is transmitted (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm is used as the cathode 7023.

After laminating and forming a translucent conductive film and an aluminum film, the conductive film 7027 and the cathode 7023 may be selectively etched to form the translucent conductive film 7027 and the cathode 7023. In this case, the same mask is used. Can be etched, which is preferable.

The peripheral edge of the cathode 7023 is covered with a partition wall 7029. The partition wall 7029 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. It is preferable that the partition wall 7029 is formed by using a photosensitive resin material in particular, forming an opening on the cathode 7023 so that the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7029, the step of forming the resist mask can be omitted.

Further, the EL layer 7024 formed on the cathode 7023 and the partition wall 7029 may be composed of a single layer or may be configured such that a plurality of layers are laminated. EL layer 70
When 24 is composed of a plurality of layers, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order on the cathode 7023. It is not necessary to provide all of these layers.

Further, the stacking order is not limited, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order on the cathode 7023. However, when comparing the power consumption, it is preferable to stack the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer on the cathode 7023 in this order because the power consumption is low.

Although various materials can be used as the anode 7025 formed on the EL layer 7024, a material having a large work function, for example, a transparent conductive material such as ITO, IZO, and ZnO is preferable. In this embodiment, an ITO film containing silicon oxide is used as the anode 7026.

The region of the cathode 7023 and the anode 7025 sandwiching the EL layer 7024 is the light emitting element 7022.
Corresponds to. In the case of the element structure shown in FIG. 15B, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

Note that FIG. 15B shows an example in which a light-transmitting conductive film is used as the gate electrode layer, and the light emitted from the light emitting element 7022 toward the cathode 7023 is the color filter layer 7043.
And passes through the gate electrode layer and the source electrode layer of the TFT 7021 to inject. TFT
By using a translucent conductive film as the gate electrode layer and the source electrode layer of the 7021, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side can be made substantially the same.

The color filter layer 7043 is formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

Further, the color filter layer 7043 is covered with the overcoat layer 7044, and the insulating layer 7 is further covered.
Cover with 045.

Further, the contact holes formed in the insulating layer 7045 and reaching the drain electrode layer are
It is arranged at a position overlapping with the partition wall 7029. By arranging the layout in which the contact hole reaching the drain electrode layer and the partition wall 7029 are overlapped, the aperture ratio on the anode 7025 side and the aperture ratio on the cathode 7023 side can be made substantially the same.

Further, the contact hole formed in the insulating layer 7045 and reaching the conductive film 7027 having translucency is arranged at a position overlapping with the partition wall 7029.

However, when using a light emitting element with a double-sided injection structure and displaying both display surfaces in full color,
Since the light from the anode 7025 side does not pass through the color filter layer 7043, it is preferable to provide a sealing substrate separately provided with the color filter layer above the anode 7025.

Next, a light emitting element having a top injection structure will be described with reference to FIG. 15 (C).

FIG. 15C shows a cross-sectional view of pixels when the driving TFT 7001 is n-type and the light emitted from the light emitting element 7002 escapes to the anode 7005 side. In FIG. 15 (C),
Cathode 700 of light emitting element 7002 electrically connected to TFT 7001 via a connection electrode layer
3 is formed, and the EL layer 7004 and the anode 7005 are laminated in this order on the cathode 7003.

Although various materials can be used for the cathode 7003, materials having a small work function, for example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these (Mg: Ag, Al: Li, etc.), rare earth metals such as Yb and Er are preferable.

The peripheral edge of the cathode 7003 is covered with a partition wall 7009. The partition wall 7009 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. It is preferable that the partition wall 7009 is formed by using a photosensitive resin material in particular, forming an opening on the cathode 7003, and forming the side wall of the opening so as an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7009, the step of forming the resist mask can be omitted.

Further, the EL layer 7004 formed on the cathode 7003 and the partition wall 7009 may be composed of a single layer or may be configured such that a plurality of layers are laminated. EL layer 70
When 04 is composed of a plurality of layers, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order on the cathode 7003. It is not necessary to provide all of these layers.

Further, the stacking order is not limited, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order on the cathode 7003. When stacking in this order, cathode 700
3 will function as an anode.

In FIG. 15C, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated in this order on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order, and Mg is formed therein. : A
A laminate of a g-alloy thin film and ITO is formed.

However, when comparing the power consumption, the electron injection layer, the electron transport layer, and the light emitting layer are on the cathode 7003.
It is preferable to stack the hole transport layer and the hole injection layer in this order because the power consumption is low.

The anode 7005 is formed by using a translucent conductive material that transmits light, and for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and titanium oxide. A translucent conductive film such as indium tin oxide, indium tin oxide, indium zinc oxide, and indium tin oxide to which silicon oxide is added may be used.

The region sandwiching the EL layer 7004 between the cathode 7003 and the anode 7005 corresponds to the light emitting element 7002. In the case of the pixel shown in FIG. 15C, the light emitted from the light emitting element 7002 is emitted to the anode 7005 side as shown by an arrow.

Further, in FIG. 15C, the TFT 7001 shows an example in which the thin film transistor 150 is used, but the thin film transistor 160, 170, 180 can be used without particular limitation.

Further, in FIG. 15C, the drain electrode layer of the TFT 7001 is electrically connected to the connection electrode layer via the oxide insulating layer 7051, and the connection electrode layers are the insulating layer 7052 and the insulating layer 70.
It is electrically connected to the cathode 7003 via 55. The flattening insulating layer 7053 is made of polyimide,
Resin materials such as acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane-based resins, and P.
SG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. The flattening insulating layer 7053 may be formed by laminating a plurality of insulating films formed of these materials. The method for forming the flattening insulating layer 7053 is not particularly limited, and depending on the material, a sputtering method, an SOG method, a spin coating, a dip, a spray coating, a droplet ejection method (inkjet method, screen printing, offset printing, etc.) , Doctor knife, roll coater,
A curtain coater, a knife coater, or the like can be used.

Further, a partition wall 7009 is provided to insulate the cathode 7003 and the cathodes of adjacent pixels.
The partition wall 7009 is formed by using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. It is preferable that the partition wall 7009 is formed by using a photosensitive resin material in particular, forming an opening on the cathode 7003, and forming the side wall of the opening so as an inclined surface formed with a continuous curvature.

Further, in the structure of FIG. 15C, when performing full-color display, for example, the light emitting element 70
As 02, a green light emitting element is used, one adjacent light emitting element is a red light emitting element, and the other light emitting element is a blue light emitting element. In addition, not only 3 types of light emitting elements but also white elements are added 4
A light emitting display device capable of full-color display with various types of light emitting elements may be manufactured.

Further, in the structure of FIG. 15C, the plurality of light emitting elements to be arranged are all white light emitting elements, and a sealing substrate having a color filter or the like is arranged above the light emitting element 7002.
A light emitting display device capable of full-color display may be manufactured. Full-color display can be performed by forming a material that emits a single color such as white and combining it with a color filter and a color conversion layer.

Of course, monochromatic light emission may be displayed. For example, a white light emitting device may be used to form an illumination device, or a single color light emitting device may be used to form an area color type light emitting device.

Further, if necessary, an optical film such as a polarizing film such as a circular polarizing plate may be provided.

Although the organic EL element has been described here as the light emitting element, the inorganic E as the light emitting element has been described.
It is also possible to provide an L element.

Although an example is shown in which the thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically connected, the current control TFT is connected between the driving TFT and the light emitting element. It may have a configuration that is present.

Next, the appearance and cross section of the light emitting display panel (also referred to as the light emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 16 (A) is a plan view of a panel in which a thin film transistor and a light emitting element formed on the first substrate are sealed between the thin film transistor and the light emitting element with a sealing material, and FIG. 16 (B) is a plan view of the panel. , Corresponds to the cross-sectional view in HI of FIG. 16 (A).

Pixel unit 4502 provided on the first substrate 4501, signal line drive circuits 4503a, 450
Sealing material 4505 so as to surround 3b and scanning line drive circuits 4504a and 4504b.
Is provided. A second substrate 4506 is provided on the pixel unit 4502, the signal line drive circuits 4503a and 4503b, and the scanning line drive circuits 4504a and 4504b. Therefore, the pixel unit 4502, the signal line drive circuits 4503a and 4503b, and the scanning line drive circuit 45
04a and 4504b are sealed together with the filler 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. As described above, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material having high airtightness and little degassing so as not to be exposed to the outside air.

Further, a pixel portion 4502 provided on the first substrate 4501 and a signal line drive circuit 4503a, 4
The 503b and the scanning line drive circuits 4504a and 4504b have a plurality of thin film transistors, and in FIG. 15B, the thin film transistor 4510 included in the pixel unit 4502 and the thin film transistor 4509 included in the signal line drive circuit 4503a are exemplified. doing.

As the thin film transistors 4509 and 4510, highly reliable thin film transistors including the oxide semiconductor layer shown in the first embodiment can be applied. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

The conductive layer 4540 is provided on the insulating layer 4544 at a position overlapping the channel forming region of the oxide semiconductor layer of the thin film transistor 4509 for the drive circuit. By providing the conductive layer 4540 at a position overlapping the channel forming region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test. Further, the conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509 or may have a different potential, and may function as a second gate electrode layer. In addition, the conductive layer 45
The potential of 40 may be GND, 0V, or a floating state.

In the thin film transistor 4509, an insulating layer 4541 is formed as an insulating film in contact with the semiconductor layer including the channel forming region. The insulating layer 4541 is the insulating layer 107 shown in the first embodiment.
It may be formed by the same material and method as above. Further, in order to reduce the surface unevenness of the thin film transistor, it is covered with an insulating layer 4544 that functions as a flattening insulating film. Here, as the insulating layer 4541, a silicon oxide film is formed by a sputtering method in the same manner as the insulating layer 107 shown in the first embodiment.

Further, an insulating layer 4544 is formed as a flattening insulating film. The insulating layer 4544 may be formed by the same material and method as the insulating layer 4021 shown in the second embodiment. Here, acrylic is used as the insulating layer 4544.

Further, 4511 corresponds to a light emitting element, and the first electrode layer 4517, which is a pixel electrode of the light emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The configuration of the light emitting element 4511 is a laminated structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the configuration shown. The configuration of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like.

The partition wall 4520 is formed by using an organic resin film, an inorganic insulating film, or an organic polysiloxane.
In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

The electroluminescent layer 4512 may be composed of a single layer or may be configured such that a plurality of layers are laminated.

A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, water, carbon dioxide, etc. do not enter the light emitting element 4511. As a protective film, a silicon nitride film,
A silicon nitride film, a DLC film, or the like can be formed.

Further, the signal line drive circuits 4503a and 4503b and the scanning line drive circuits 4504a and 4504b
, Or various signals and potentials given to the pixel unit 4502 are FPC4518a, 4518.
It is supplied from b.

The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistors 4509 and 4510. ing.

The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via an anisotropic conductive film 4519.

The substrate located in the direction of extracting light from the light emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

Further, as the filler 4507, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, etc. can be used.
Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV
A (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is provided on the injection surface of the light emitting element.
An optical film such as a retardation plate (λ / 4 plate, λ / 2 plate) or a color filter may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment that can diffuse the reflected light due to the unevenness of the surface and reduce the reflection can be applied.

The signal line drive circuits 4503a and 4503b and the scanning line drive circuits 4504a and 4504b may be mounted by a drive circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Further, only the signal line drive circuit, or a part of the signal line drive circuit, or only the scan line drive circuit, or only a part of the scan line drive circuit may be separately formed and mounted, and the configuration is not limited to that shown in FIG.

Through the above steps, a highly reliable light emitting display device (display panel) can be manufactured as a semiconductor device.

By manufacturing the thin film transistor of the pixel portion of the light emitting display device by using the method for manufacturing the thin film transistor shown in the first embodiment, it is possible to reduce the power consumption caused by the fluctuation of the off current of the thin film transistor of each pixel.

Further, by manufacturing the thin film transistor of the drive circuit of the light emitting display device by using the method of manufacturing the thin film transistor shown in the first embodiment, high-speed operation of the thin film transistor of the drive circuit unit can be realized and power saving can be achieved.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 6)
In the present embodiment, as one embodiment of the semiconductor device, an example of a liquid crystal display device using a liquid crystal element having a thin film transistor shown in the first embodiment will be described with reference to FIGS. 17 to 20. FIG. 17
To the TFT 628 and TFT 629 used in the liquid crystal display device of FIG. 20, the thin film transistor shown in the first embodiment can be applied, and the thin film transistor having high electrical characteristics and reliability can be manufactured in the same manner as the step shown in the first embodiment. be. The TFT 628 and TFT 629 are thin film transistors having an oxide semiconductor layer as a channel forming region. 17 to 20
Then, the case where the thin film transistor shown in FIG. 2C is used as an example of the thin film transistor will be described, but the present invention is not limited to this.

Hereinafter, a VA (Vertical Alignment) type liquid crystal display device will be described.
The VA type liquid crystal display device is a kind of method for controlling the arrangement of liquid crystal molecules on a liquid crystal display panel. The VA type liquid crystal display device is a system in which liquid crystal molecules are oriented in the direction perpendicular to the panel surface when no voltage is applied. In this embodiment, the pixels are particularly divided into several regions (sub-pixels), and the molecules are devised to be tilted in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device in which a multi-domain design is taken into consideration will be described.

18 and 19 show pixel electrodes and counter electrodes, respectively. Note that FIG. 18 is a plan view of the substrate side on which the pixel electrodes are formed, and FIG. 17 shows a cross-sectional structure corresponding to the cutting lines EF shown in the drawing. Further, FIG. 19 is a plan view of the substrate side on which the counter electrode is formed. In the following description, these figures will be referred to.

FIG. 17 shows a state in which the substrate 600 on which the TFT 628, the pixel electrode 624 connected to the TFT 628, and the holding capacitance portion 630 are formed, and the counter substrate 601 on which the counter electrode 640 and the like are formed are superposed, and the liquid crystal is injected. Shown.

At the position where the columnar spacer is formed on the opposed substrate 601, the first colored film 636 and the second
A colored film (not shown), a third colored film (not shown), and a counter electrode 640 are formed. Due to this structure, the heights of the protrusions 644 and the spacers for controlling the orientation of the liquid crystal are different. An alignment film 648 is formed on the pixel electrode 624, and similarly, an alignment film 646 is formed on the counter electrode 640. During this time, the liquid crystal layer 650 is formed.

Although the spacer is shown here using a columnar spacer, a bead spacer may be sprayed. Here, the columnar spacer is an organic film or an inorganic film formed on one of the substrates, which is patterned and etched to a predetermined size by a photolithography process, or a positive or negative patternable organic film. The columnar spacer can control the thickness of the liquid crystal layer. Further, the spacer may be formed on the pixel electrode 624 formed on the substrate 600.

On the substrate 600, the TFT 628, the pixel electrode 624 connected to the TFT 628, and the holding capacitance unit 63
0 is formed. The pixel electrode 624 includes a TFT 628, wiring 616, and a holding capacitance portion 630.
The contact hole 623 penetrates the insulating film 620 that covers the insulating film 620 and the third insulating film 622 that covers the insulating film 620, respectively, and is connected to the wiring 618. As the TFT 628, the thin film transistor shown in the first embodiment can be appropriately used. Further, the holding capacitance portion 630 includes a capacitance wiring 604, which is the first capacitance wiring formed at the same time as the gate wiring 602 of the TFT 628, and a gate insulating film 60.
It is composed of 6 and the capacitance wiring 617 which is the second capacitance wiring formed at the same time as the wirings 616 and 618.

A liquid crystal element is formed by overlapping the pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640.

FIG. 18 shows the structure on the substrate 600. The pixel electrode 624 includes an indium oxide containing tungsten oxide, an indium zinc oxide containing tungsten oxide, an indium oxide containing titanium oxide, an indium tin oxide containing titanium oxide, and an indium tin oxide (hereinafter referred to as ITO. ), Indium zinc oxide, indium tin oxide to which silicon oxide is added, and other conductive materials having translucency can be used.

Further, the pixel electrode 624 can be formed by using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed by using the conductive composition preferably has a sheet resistance of 10000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be mentioned.

The pixel electrode 624 is provided with a slit 625. The slit 625 is for controlling the orientation of the liquid crystal display.

The TFT 628 shown in FIG. 18, the pixel electrode 626 connected to the TFT 628, and the holding capacity portion 631 can be formed in the same manner as the TFT 628, the pixel electrode 624, and the holding capacity portion 630, respectively. Both TFT 628 and TFT 629 are connected to wiring 616. The pixels of the liquid crystal display panel are composed of a pixel electrode 624 and a pixel electrode 626. The pixel electrode 624 and the pixel electrode 626 constitute a sub-pixel.

FIG. 19 shows the structure on the opposite substrate side. The counter electrode 640 is preferably formed by using the same material as the pixel electrode 624. A protrusion 644 that controls the orientation of the liquid crystal is formed on the counter electrode 640.

The equivalent circuit of this pixel structure is shown in FIG. Both TFT 628 and TFT 629 are connected to the gate wiring 602 and the wiring 616. In this case, by making the potentials of the capacitance wiring 604 and the capacitance wiring 605 different, the operations of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, by individually controlling the potentials of the capacitive wiring 604 and the capacitive wiring 605, the orientation of the liquid crystal is precisely controlled to widen the viewing angle.

When a voltage is applied to the pixel electrode 624 provided with the slit 625, electric field distortion (oblique electric field) is generated in the vicinity of the slit 625. The slit 625 and the protrusion 6 on the facing substrate 601 side.
By arranging the 44s so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, so that the direction in which the liquid crystal is oriented is different depending on the location. That is, the viewing angle of the liquid crystal display panel is widened by making it multi-domain.

Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 21 to 24.

21 and 22 show the pixel structure of the VA type liquid crystal display panel. FIG. 22 shows the substrate 600.
21 is a plan view of the above, and the cross-sectional structure corresponding to the cutting line YZ shown in the drawing is shown in FIG. In the following description, both figures will be referred to.

In this pixel structure, one pixel has a plurality of pixel electrodes, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. That is, the multi-domain designed pixel has a configuration in which the signal applied to each pixel electrode is independently controlled.

The pixel electrode 624 is connected to the TFT 628 by wiring 618 in the contact hole 623. Further, the pixel electrode 626 is a TFT in the contact hole 627 with the wiring 619.
It is connected to 629. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be given. On the other hand, the wiring 616 that functions as a data line is commonly used in the TFT 628 and the TFT 629. As the TFT 628 and the TFT 629, the thin film transistor shown in the first embodiment can be appropriately used. Further, a capacitance wiring 690 is provided.

The shapes of the pixel electrode 624 and the pixel electrode 626 are different, and they are separated by a slit 625. The pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of the voltage applied to the pixel electrode 624 and the pixel electrode 626 is set to TFT 628.
The orientation of the liquid crystal is controlled by making the difference with the TFT 629. An equivalent circuit of this pixel structure is shown in FIG. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. By giving different gate signals to the gate wiring 602 and the gate wiring 603, the operation timings of the TFT 628 and the TFT 629 can be made different.

A colored film 636 and a counter electrode 640 are formed on the facing substrate 601. In addition, the colored film 6
A flattening film 637 is formed between the 36 and the counter electrode 640 to prevent the liquid crystal display from being disturbed in orientation. FIG. 23 shows the structure on the opposite substrate side. The counter electrode 640 is an electrode that is common among different pixels, but a slit 641 is formed. The slit 641 and the pixel electrode 62
By arranging the 4 and the slit 625 on the pixel electrode 626 side so as to alternately mesh with each other, it is possible to effectively generate an oblique electric field and control the orientation of the liquid crystal display. As a result, the direction in which the liquid crystal is oriented can be changed depending on the location, and the viewing angle is widened.

The first liquid crystal element is formed by overlapping the pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640. Further, a second liquid crystal element is formed by overlapping the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640. Further, it has a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel.

In the present embodiment, the liquid crystal display device having the thin film transistor shown in the first embodiment is V.
Although the A-type liquid crystal display device has been described, it can also be applied to an IPS-type liquid crystal display device, a TN-type liquid crystal display device, and the like.

By manufacturing the thin film transistor of the pixel portion of the light emitting display device by using the method for manufacturing the thin film transistor shown in the first embodiment, it is possible to reduce the power consumption caused by the fluctuation of the off current of the thin film transistor of each pixel.

(Embodiment 7)
The semiconductor device disclosed in the present specification can be applied as an electronic paper. Electronic paper can be used for electronic devices in all fields as long as it displays information. For example, electronic paper can be used for electronic books (electronic books), posters, in-car advertisements for vehicles such as trains, and display on various cards such as credit cards. An example of an electronic device is shown in FIG.

FIG. 25 shows an example of the electronic book 2700. For example, the electronic book 2700 has a housing 2
It is composed of two housings, 701 and 2703. Housing 2701 and housing 27
03 is integrated by a shaft portion 2711, and can perform an opening / closing operation with the shaft portion 2711 as an axis. With such a configuration, it is possible to perform an operation like a paper book.

A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By displaying different screens, for example, a sentence can be displayed on the right display unit (display unit 2705 in FIG. 25) and an image can be displayed on the left display unit (display unit 2707 in FIG. 25). ..

Further, FIG. 25 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, housing 2
The 701 includes a power supply 2721, operation keys 2723, a speaker 2725, and the like. The page can be fed by the operation key 2723. A keyboard, a pointing device, or the like may be provided on the same surface as the display unit of the housing. Further, the back or side surface of the housing may be provided with an external connection terminal (earphone terminal, USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like. .. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary.

Further, the electronic book 2700 may be configured to be able to transmit and receive information wirelessly. By radio
It is also possible to purchase desired book data or the like from an electronic book server and download it.

(Embodiment 8)
The semiconductor device disclosed in the present specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, cameras such as digital video cameras, digital photo frames, and mobile phones (mobile phones, mobile phones). (Also referred to as a device), a portable game machine, a mobile information terminal, a sound reproduction device, a large game machine such as a pachinko machine, and the like.

FIG. 26A shows an example of the television device 9600. Television device 96
For 00, the display unit 9603 is incorporated in the housing 9601. The display unit 9603 makes it possible to display an image. Further, here, the housing 9601 is provided by the stand 9605.
Shows the configuration that supports.

The operation of the television device 9600 can be performed by the operation switch provided in the housing 9601 or the remote control operation device 9610 separately provided. The operation keys 9609 included in the remote controller 9610 can be used to control the channel and volume, and the image displayed on the display unit 9603 can be operated. Further, the remote controller 9610 may be provided with a display unit 9607 for displaying information output from the remote controller 9610.

The television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via a modem, it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between (or between recipients, etc.).

FIG. 26B shows an example of the digital photo frame 9700. For example, in the digital photo frame 9700, the display unit 9703 is incorporated in the housing 9701. The display unit 9703 can display various images, and by displaying image data taken by, for example, a digital camera, the display unit 9703 can function in the same manner as a normal photo frame.

The digital photo frame 9700 has an operation unit and an external connection terminal (USB terminal, US).
A terminal that can be connected to various cables such as a B cable), a recording medium insertion part, and the like are provided. These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory that stores image data taken by a digital camera can be inserted into a recording medium insertion unit of a digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 9703.

Further, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired image data is captured and displayed wirelessly.

FIG. 27 (A) is a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891, and is openably and closably connected by a connecting portion 9893. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. In addition, the portable gaming machine shown in FIG. 27A has a speaker unit 9884 and a recording medium insertion unit 988.
6. LED lamp 9890, input means (operation key 9858, connection terminal 9887, sensor 9)
888 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature,
It is equipped with chemical substances, voice, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, vibration), microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the configuration including the semiconductor device disclosed in the present specification may be used, and other auxiliary equipment may be appropriately provided. The portable gaming machine shown in FIG. 27 (A) has a function of reading a program or data recorded on a recording medium and displaying it on a display unit, or wirelessly communicates with another portable gaming machine to share information. Has a function. The functions of the portable gaming machine shown in FIG. 27 (A) are not limited to this, and can have various functions.

FIG. 27B shows an example of a slot machine 9900, which is a large-scale gaming machine. In the slot machine 9900, the display unit 9903 is incorporated in the housing 9901. In addition, the slot machine 9900 is provided with operating means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the above, and at least a configuration including the semiconductor device disclosed in the present specification may be used, and other auxiliary equipment may be appropriately provided.

FIG. 28 (A) is a perspective view showing an example of a portable computer.

In the portable computer of FIG. 28A, the upper housing 9301 having the display unit 9303 and the lower housing 9302 having the keyboard 9304 with the hinge unit connecting the upper housing 9301 and the lower housing 9302 in the closed state are closed. It is possible to put the above on top of each other, which is convenient to carry, and when the user inputs on the keyboard, the hinge unit can be opened and the input operation can be performed by looking at the display unit 9303.

Further, the lower housing 9302 has a pointing device 9306 for performing an input operation in addition to the keyboard 9304. Further, if the display unit 9303 is used as a touch input panel, an input operation can be performed by touching a part of the display unit. Further, the lower housing 9302 has a calculation function unit such as a CPU and a hard disk. Further, the lower housing 9302 is used for other devices such as U.
It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted.

The upper housing 9301 has a display unit 93 that can be slid and stored inside the upper housing 9301.
It has 07, and a wide display screen can be realized. In addition, a display unit 93 that can be stored
The user can adjust the orientation of the screen of 07. Further, if the storable display unit 9307 is used as a touch input panel, the input operation can be performed by touching a part of the storable display unit.

The display unit 9303 or the storable display unit 9307 uses an image display device such as a liquid crystal display panel, a light emitting display panel such as an organic light emitting element or an inorganic light emitting element.

Further, the portable computer of FIG. 28A can receive a television broadcast and display an image on a display unit or a display unit as a configuration including a receiver or the like. In addition, the upper housing 93
Display unit 930 with the hinge unit connecting 01 and the lower housing 9302 closed.
The user can also watch the television broadcast by sliding 7 to expose the entire screen and adjusting the screen angle. In this case, since the hinge unit is opened and the display unit 9303 is not displayed and only the circuit for displaying the TV broadcast is started, the minimum power consumption can be achieved and the battery capacity is limited. It is useful in portable computers that are used.

Further, FIG. 28B is a perspective view showing an example of a mobile phone having a form that can be worn on the user's arm like a wristwatch.

This mobile phone has at least a communication device having a telephone function, a main body having a battery, a band portion for attaching the main body to the arm, and an adjustment unit 92 for adjusting the fixed state of the band portion with respect to the arm.
It is composed of 05, a display unit 9201, a speaker 9207, and a microphone 9208.

Further, the main body has an operation switch 9203, and a power input switch, a display changeover switch, an image pickup start instruction switch, and for example, when a button is pressed, a program for the Internet is started.

The input operation of the mobile phone is performed by touching the display unit 9201 with a finger or an input pen, operating the operation switch 9203, or inputting voice to the microphone 9208. In addition, in FIG. 28B, the display button 9202 displayed on the display unit 9201 is illustrated, and input can be performed by touching it with a finger or the like.

Further, the main body has a camera unit 9206 having an imaging means for converting a subject image imaged through a photographing lens into an electronic image signal. It is not necessary to provide a camera unit in particular.

Further, the mobile phone shown in FIG. 28B is configured to include a receiver for television broadcasting and the like, so that it can receive television broadcasting and display an image on the display unit 9201, and further, a storage device such as a memory or the like. As a configuration equipped with, a television broadcast can be recorded in a memory. In addition, FIG. 28 (B)
The mobile phone shown in the above may have a function of collecting position information such as GPS.

The display unit 9201 uses an image display device such as a liquid crystal display panel, a light emitting display panel such as an organic light emitting element or an inorganic light emitting element. Since the mobile phone shown in FIG. 28B is small and lightweight, the battery capacity is limited, and it is preferable that the display device used for the display unit 9201 uses a panel that can be driven with low power consumption.

Although FIG. 28 (B) shows an electronic device of the type to be worn on the "arm", the electronic device is not particularly limited as long as it has a shape that can be carried.

In this example, a thin film transistor is manufactured by using the manufacturing method shown in the first embodiment, and the number is -2.
The results of evaluating the off-current of the thin film transistor characteristics in an environment of 5 ° C. to 150 ° C. are shown.

In this example, a plurality of thin film transistors having a channel length L of 3 μm were prepared on a glass substrate, and the off-current of the thin film transistor characteristics in an environment of −25 ° C. or higher and 150 ° C. or lower was evaluated. The channel width W was set to 20 μm. First, a method for manufacturing a thin film transistor will be described.

First, a silicon oxide film having a film thickness of 100 nm is formed on a glass substrate as a base film by a CVD method, and a gate electrode layer having a film thickness of 100 nm is formed on the silicon oxide film by a sputtering method.
Tungsten film was formed. Here, the tungsten film was selectively etched to form a gate electrode layer.

Next, a silicon oxide film having a film thickness of 100 nm was formed on the gate electrode layer as a gate insulating layer by a CVD method.

Next, on the gate insulating layer, an In-Ga-Zn-O-based oxide semiconductor target (In ₂ O ₃₎
: Ga ₂ O ₃ : ZnO = 1: 1: 1), and the distance between the substrate and the target is 80 m.
m, pressure 0.4 Pa, direct current (DC) power supply 5 kW, argon and oxygen (argon: oxygen = 5)
A film was formed at 200 ° C. under an atmosphere of 0 sccm: 50 sccm) to form an oxide semiconductor layer having a film thickness of 30 nm. Here, the oxide semiconductor layer was selectively etched to form an island-shaped oxide semiconductor layer.

Next, the oxide semiconductor layer was subjected to the first heat treatment at 650 ° C. for 1/6 under a nitrogen atmosphere, and then the second heat treatment was performed at 450 ° C. for 1 hour under an atmospheric atmosphere.

Next, a titanium film (thickness 100) is used as a source electrode layer and a drain electrode layer on the oxide semiconductor layer.
A laminate of an aluminum film (thickness 300 nm) and a titanium film (thickness 100 nm) was formed at 100 ° C. by a sputtering method. Here, the source electrode layer and the drain electrode layer were selectively etched so that the length of the channel length L of the thin film transistor was 3 μm and the channel width W was 20 μm.

Next, the film thickness is 300 n by the sputtering method as an insulating layer so as to be in contact with the oxide semiconductor layer.
A silicon oxide film of m was formed at 200 ° C. Here, the silicon oxide film as the protective layer was selectively etched to form openings on the gate electrode layer, the source electrode layer, and the drain electrode layer. Then, a third heat treatment was performed at 250 ° C. for 1 hour in a nitrogen atmosphere.

Through the above steps, a plurality of thin film transistors having a channel length L of 3 μm and a channel width W of 20 μm were produced on a glass substrate.

Subsequently, the off-current of the thin film transistor was measured. The off-current characteristics were measured by setting the voltage between the source and drain (hereinafter referred to as drain voltage or Vd) to 10 V and the voltage between the source and gate (hereinafter referred to as gate voltage or Vg) at -10 V. .. Figure 4 (
In B), the substrate temperature at the time of measurement is changed to −25 ° C., 0 ° C., 25 ° C., 50 ° C., 100 ° C., and 150 ° C., and the off-current of the thin film transistor at each substrate temperature (operating temperature) is shown.
The horizontal axis shows the substrate temperature (operating temperature) at the time of measuring the off-current of the thin film transistor on a linear scale, and the vertical axis shows the off-current (Off) at each substrate temperature on a log scale.

The thin film transistor produced in this example is in an environment of -25 ° C or higher and 150 ° C or lower.
It was confirmed that the off-current value was 1 × 10 ^{-12 A or less.}

10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 28 Transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 61 Period 62 Period 100 Substrate 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 107 Insulating layer 110 Channel protective layer 150 Thin film transistor 160 Thin film transistor 170 Thin film transistor 180 Thin film transistor 201 Specimen 202 Specimen 203 Specimen 301 Specimen 302 Spectra 303 Specimen 311 Specimen 312 Specimen 313 Specimen 321 Specimen 322 Specimen 323 Spectra 400 Glass substrate 401 In-Ga-Zn-O-based oxide semiconductor Layer 403 Analytical direction 411 Oxygen ion intensity profile 412 Hydrogen concentration profile 413 Hydrogen concentration profile 451 Spectra 452 Specimen 453 Specimen 461 Specimen 462 Specimen 463 Specimen 581 Thin film transistor 583 Insulating film 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling Material 600 Board 601 Opposite board 602 Gate wiring 603 Gate wiring 604 Capacitive wiring 605 Capacitive wiring 606 Gate insulating film 616 Wiring 617 Capacitive wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact hole 624 Pixel electrode 625 Slit 626 Pixel electrode 627 Contact Hall 628 TFT
629 TFT
630 Retaining capacity part 631 Retaining capacity part 636 Colored film 637 Flattening film 640 Opposite electrode 641 Slit 644 Protrusion 646 Alignment film 648 Alignment film 650 In a nitrogen atmosphere 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacity wiring 701 Gate electrode layer 702 Gate Insulation layer 703 Semiconductor layer 704 Source electrode layer 705 Drain electrode layer 801 Glass substrate 802 Gate electrode layer 803 Gate insulation layer 804 Oxide semiconductor layer 805 Source electrode layer 806 Drain electrode layer 105a Source electrode layer 105b Drain electrode layer 2600 TFT substrate 2601 Opposite Board 2602 Sealing material 2603 Pixel part 2604 Display element 2605 Colored layer 2606 Plate plate 2607 Plate plate 2608 Wiring circuit part 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflector plate 2612 Circuit board 2613 Diffusion plate 2700 Electronic book 2701 Housing 2703 Housing 2705 Display 2707 Display 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Board 4002 Pixel 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Board 4008 Liquid crystal layer 4010 Thin film 4011 Thin film 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 Anisotropic conductive film 4020 Insulation layer 4020 Insulation layer (Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Opposite electrode layer 4032 Insulation layer 4040 Conductive layer 4501 Substrate 4502 Pixel part 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electric light emitting layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisometric thin film transistor 4520 Partition 4540 Conductive layer 4541 Insulation layer 4544 Insulation layer 5300 On substrate 5300 Substrate 5301 Pixel part 5302 Scanning line drive circuit 5303 Scan line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit section 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 590a Black area 590b White area 6400 Pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitive element 6404 Light emission Element 6405 Signal line 6406 Scan line 6407 Power line 6408 Common electrode 7001 TFT
7002 Light emitting element 7003 Cathode 7004 EL layer 7005 Anode 7009 Partition wall 7011 TFT
7012 Light emitting element 7013 Cathode 7014 EL layer 7015 Anode 7016 Shielding film 7017 Conductive film 7019 Partition wall 7021 TFT
7022 Light emitting element 7023 Cone 7024 EL layer 7025 Ano 7026 Ano 7027 Conductive 7029 Partition 7031 Oxide insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Insulation layer 7041 Oxide insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Insulation layer 704a Drain electrode layer 704b Source electrode layer 7051 Oxide insulation layer 7052 Insulation layer 7053 Flattening insulation layer 7055 Insulation layer 9201 Display unit 9202 Display button 9203 Operation switch 9205 Adjustment unit 9206 Camera unit 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display unit 9304 Keyboard 9305 External connection port 9306 Pointing device 9307 Display unit 9600 Television device 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation machine 9700 Digital photo frame 9701 Housing 9703 Display 9881 Housing 9882 Display unit 9883 Display unit 9884 Speaker unit 9858 Input means (operation key 9886 Recording medium insertion unit 9878 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connection 9900 Slot machine 9901 Housing 9903 Display 4503a Signal line drive circuit 4504a Scan line drive circuit 4518a FPC

Claims (2)

Has multiple pixels,
The pixel has a transistor and a light emitting element on the transistor.
The transistor has an oxide semiconductor layer having indium, gallium, and zinc, and a metal conductive film located below the oxide semiconductor layer and overlapping the oxide semiconductor layer via an insulating layer.
The transistor has a channel length of 1.5 μm or more and 100 μm or less.
The transistor is a light emitting display panel ^{having an off-current value of 1 × 10 -12} A or less per 1 μm of channel width in a temperature range of -25 ° C or higher and 150 ° C or lower as a measurement temperature. Has multiple pixels,
The pixel has a transistor and a light emitting element on the transistor.
The transistor has an oxide semiconductor layer having indium, gallium, and zinc, and a metal conductive film located below the oxide semiconductor layer and overlapping the oxide semiconductor layer via an insulating layer.
The transistor has a channel length of 3 μm or more and 10 μm or less.
The transistor is a light emitting display panel ^{having an off-current value of 1 × 10 -12} A or less per 1 μm of channel width in a temperature range of -25 ° C or higher and 150 ° C or lower as a measurement temperature.

Images