JP7291275B2 - Display device - Google Patents

Description

The present invention relates to a semiconductor device using an oxide semiconductor and a manufacturing method thereof.

In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

2. Description of the Related Art In recent years, attention has been paid to a technique of forming a thin film transistor (TFT) using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface. The thin film transistor is I
They are widely applied to electronic devices such as C and electro-optical devices, and are urgently being developed especially as switching elements for image display devices. Metal oxides are attracting attention as semiconductor thin films, and various metal oxides exist and are used for various purposes. In particular, indium oxide is a well-known material as a metal oxide, and is used as a transparent electrode material required for liquid crystal displays and the like.

Some metal oxides exhibit semiconductor properties. Metal oxides exhibiting semiconductor characteristics include, for example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors having such metal oxides exhibiting semiconductor characteristics as channel formation regions are already known. (Patent Document 1 and Patent Document 2).

Japanese Patent Application Laid-Open No. 2007-123861 JP 2007-96055 A

In an active matrix display device, the electrical characteristics of thin film transistors forming a circuit are important, and these electrical characteristics determine the performance of the display device. In particular, among the electrical characteristics of thin film transistors, power consumption during non-operation (power consumption during standby) due to an increase in off-state current (also referred to as leakage current, Ioff) is important.

In the case of an n-channel type thin film transistor, a thin film transistor in which a channel is formed for the first time when a positive voltage is applied to the gate voltage and drain current begins to flow is desirable. A thin film transistor in which an off current flows when a voltage applied to a gate is negative is not suitable as a thin film transistor used in a circuit.

For example, when the off current of a thin film transistor that constitutes a circuit in a semiconductor device is large,
Current leakage may occur due to the increase in off current. Accordingly, an object of one embodiment of the present invention is to provide a thin film transistor that operates stably over a wide temperature range and a semiconductor device using the thin film transistor. Note that in this specification and the like, the off-state current of a thin film transistor indicates a current value when the voltage applied to the gate is negative.

In one embodiment of the present invention disclosed in this specification, a gate electrode layer is provided over a substrate having an insulating surface, a gate insulating layer is provided over the gate electrode layer, and an oxide semiconductor layer is provided over the gate insulating layer. a source electrode layer and a drain electrode layer over the oxide semiconductor layer, and an insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer has
The semiconductor device has an off current value of 1×10 ⁻¹² A or less per 1 μm of channel width in a temperature range of −25° C. or more and 150° C. or less.

In the above structure, the channel length of the oxide semiconductor layer may be from 1.5 μm to 100 μm. Further, the channel length of the oxide semiconductor layer may be from 3 μm to 10 μm.

In one embodiment of the present invention disclosed in this specification, a gate electrode layer is formed over a substrate having an insulating surface, a gate insulating layer is formed over the gate electrode layer, and an oxide semiconductor is formed over the gate insulating layer. After forming an oxide semiconductor layer, first heat treatment and second heat treatment are performed to form a source electrode layer and a drain electrode layer over the oxide semiconductor layer, and a gate insulating layer and an oxide semiconductor layer are formed. forming an insulating layer in contact with a part of an oxide semiconductor layer on a semiconductor layer, a source electrode layer, and a drain electrode layer; and performing a third heat treatment after forming the insulating layer. The method.

In the above structure, the first heat treatment is preferably performed in a nitrogen atmosphere or a rare gas atmosphere. Further, the first heat treatment is preferably performed at a temperature of 350° C. or more and 750° C. or less.

In the above structure, the second heat treatment is preferably performed in an air atmosphere or an oxygen atmosphere.
Also, the second heat treatment is preferably performed at a temperature of 100° C. or more and the temperature of the first heat treatment or less.

The above configuration solves at least one of the above problems.

A thin film represented by InMO ₃ (ZnO) _m (m>0) is formed using an oxide semiconductor used in this specification, and a thin film transistor is manufactured using the thin film as an oxide semiconductor layer. However, m is not necessarily an integer. M represents one or more metal elements selected from Ga, Fe, Ni, Mn and Co. For example, M may be Ga, or may include the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M, the oxide semiconductor may contain Fe, Ni, other transition metal elements, or oxides of the transition metals as impurity elements. In this specification, among oxide semiconductor layers having a structure represented by InMO ₃ (ZnO) _m (m>0), an oxide semiconductor having a structure containing Ga as M is subjected to In—Ga—Zn—O-based oxidation. In--Ga--Zn--O-based non-single-crystal films are also called thin films.

In addition to the above oxide semiconductors applied to the oxide semiconductor layer, In—Sn—Zn—
O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, S
n-Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al
A -Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor can be used. Further, the oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx (X>0)) that inhibits crystallization in the oxide semiconductor layer, crystallization is suppressed when heat treatment is performed after the oxide semiconductor layer is formed in the manufacturing process. can do. Note that the oxide semiconductor layer is preferably amorphous, and may be partially crystallized.

Further, depending on the conditions of the heat treatment or the material of the oxide semiconductor layer, the amorphous oxide semiconductor layer may change into a microcrystalline film or a polycrystalline film. Even in the case of a microcrystalline film or a polycrystalline film, it is possible to obtain switching characteristics as a TFT.

It is possible to manufacture and provide a thin film transistor having a small fluctuation range of off current and stable electrical characteristics. Therefore, a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability can be provided.

4A and 4B illustrate a manufacturing process of a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B show an analysis method and hydrogen concentration in an oxide semiconductor layer; 4 is a graph showing off-state current characteristics of the thin film transistor of Example 1; 4A and 4B are views showing cross-sectional structures used for calculation of a semiconductor device; 4A and 4B are diagrams for explaining a structure assumed in calculation of a semiconductor device; FIG. 4 is a block diagram illustrating a semiconductor device; 3A and 3B are diagrams for explaining the configuration and operation of a signal line driver circuit; FIG. FIG. 2 is a circuit diagram showing the configuration of a shift register; 4A and 4B are configuration and timing charts for explaining the operation of a shift register; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; FIG. 10 illustrates a pixel equivalent circuit of a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 1 is a circuit diagram showing a configuration of a semiconductor device; FIG. 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 4A and 4B illustrate a semiconductor device; 1 is a circuit diagram showing a configuration of a semiconductor device; FIG. The figure which shows the example of an electronic book. FIG. 2 shows an example of a television device and a digital photo frame; The figure which shows the example of a game machine. FIG. 3 is a diagram showing an example of a portable computer and mobile phone; 4A and 4B illustrate calculation results of a semiconductor device; 4A and 4B illustrate calculation results of a semiconductor device; 4A and 4B illustrate calculation results of a semiconductor device;

Embodiments of the present invention will be described in detail below with reference to the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the forms and details thereof can be variously changed. Moreover, the present invention should not be construed as being limited to the description of the embodiments shown below.

(Embodiment 1)
In this embodiment, one embodiment of a method for manufacturing the thin film transistor 150 illustrated in FIG. 1E will be described with reference to FIGS. Note that FIG. 1F is a top view of the thin film transistor 150 shown in FIG. 1E. The thin film transistor 150 has a bottom gate structure called a channel-etched type.

First, a metal conductive film is formed over a substrate 100 that has an insulating surface, and a photolithography step and an etching step are performed using a photomask to form a desired shape, thereby providing a gate electrode layer 101 . Note that the resist mask may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by the inkjet method,
Manufacturing costs can be reduced.

A glass substrate is preferably used as the substrate 100 . A glass substrate having a strain point of 730° C. or higher is preferably used as the substrate 100 when the temperature of the subsequent heat treatment is high. Glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used for the substrate 100 . By containing more barium oxide (BaO) than boric acid, more practical heat-resistant glass can be obtained.
Therefore, it is preferable to use a glass substrate containing more BaO than B ₂ O ₃ .

Note that a substrate made of an insulator such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used instead of the substrate 100 described above. In addition, crystallized glass or the like can be used.

Further, an insulating film serving as a base film may be provided between the substrate 100 and the gate electrode layer 101 . The base film has a function of preventing impurity elements from diffusing from the substrate 100, and has a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. can be formed.

By including a halogen element such as chlorine or fluorine in the base film, the function of preventing impurity elements from diffusing from the substrate 100 can be further enhanced. The concentration of the halogen element contained in the base film is such that the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometer) is 1×10 ¹⁵ atoms/cm ³ or more and 1×10 ²⁰ atoms/cm ³ or less. do it.

A metal conductive film can be used as the gate electrode layer 101 . As the material of the metal conductive film, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above elements, or an alloy combining the above elements is preferably used. preferable. For example, a three-layer laminate structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminate structure in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer A structure is preferred. Of course, the metal conductive film may have a single layer structure, a two-layer structure, or a laminated structure of four or more layers.

Next, a gate insulating layer 102 is formed over the gate electrode layer 101 .

The gate insulating layer 102 can be formed with a single layer or a stack of silicon oxide layers, silicon nitride layers, silicon oxynitride layers, or silicon nitride oxide layers by a plasma CVD method, a sputtering method, or the like. For example, plasma CV using SiH ₄ , oxygen and nitrogen as deposition gases
A silicon oxynitride layer may be formed by the D method. The film thickness of the gate insulating layer 102 is 100 nm.
In the case of stacking, for example, a first gate insulating layer with a thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a thickness of 5 nm or more and 300 nm or less are stacked over the first gate insulating layer. and

In addition, an inert gas atmosphere (nitrogen, helium, neon,
The gate insulating layer 102 may be formed by removing impurities such as hydrogen and water contained in the layer by performing heat treatment (at least 400° C. and below the strain point of the substrate) under argon or the like.

Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed over the gate insulating layer 102 .
An oxide semiconductor film with a thickness of 50 nm or less is formed. Even if heat treatment for dehydration or dehydrogenation is performed after the oxide semiconductor film is formed, the oxide semiconductor film remains amorphous; therefore, the film thickness is preferably 50 nm or less. By reducing the thickness of the oxide semiconductor film, crystallization can be suppressed when heat treatment is performed after the oxide semiconductor layer is formed.

Note that it is preferable to remove dust attached to the surface of the gate insulating layer 102 by introducing an argon gas to generate plasma and perform reverse sputtering before forming the oxide semiconductor film by a sputtering method. . Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the target side, and the substrate surface is exposed to plasma to modify the surface. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere.

The oxide semiconductor film is an In--Ga--Zn--O-based non-single-crystal film, an In--Sn--Zn--O-based film, or an In--Ga--Zn--O-based non-single-crystal film.
-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-
Zn-O system, In-Ga-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O
In—O-based, Sn—O-based, or Zn—O-based oxide semiconductor films are used. In this embodiment mode, for example, a film is formed by a sputtering method using an In--Ga--Zn--O-based metal oxide target. Alternatively, the oxide semiconductor film is formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. can be done. Moreover, when using the sputtering method,
A film is formed using a target containing 2% by weight or more and 10% by weight or less of SiO ₂ , the oxide semiconductor film is made to contain SiOx (X>0) that inhibits crystallization, and dehydration or dehydration is performed in a later step. It is preferable to suppress crystallization during heat treatment for hydrogenation. It is preferable to use a pulse direct current (DC) power source as the power source because dust can be reduced and the film thickness distribution can be uniform.

Also, the relative density of the metal oxide in the metal oxide target is preferably 95% or higher, more preferably 99% or higher. Accordingly, the impurity concentration in the formed oxide semiconductor film can be reduced, and a thin film transistor with high electrical characteristics and high reliability can be obtained.
In this embodiment, a metal oxide target with a relative density of metal oxide of 97% is used.

Sputtering methods include an RF sputtering method using a high-frequency power source as a power source for sputtering, a DC sputtering method using a DC power source, and a pulse DC sputtering method in which a bias is applied in pulses. The RF sputtering method is mainly used for forming an insulating film, and the DC sputtering method is mainly used for forming a metal film.

There is also a multi-target sputtering apparatus in which a plurality of targets made of different materials can be installed. The multi-source sputtering apparatus can deposit films of different materials in the same chamber, and can deposit films by simultaneously discharging a plurality of materials in the same chamber.

There are also sputtering apparatuses that use a magnetron sputtering method that has a magnet mechanism inside a chamber, and sputtering apparatuses that use an ECR sputtering method that uses plasma generated using microwaves without using glow discharge.

In addition, as a film formation method using the sputtering method, there is a reactive sputtering method in which a target material and sputtering gas components are chemically reacted during film formation to form a compound thin film, and a voltage is applied to the substrate during film formation. There is also a bias sputtering method.

Alternatively, the gate insulating layer 102 and the oxide semiconductor film may be formed continuously without being exposed to the air. By forming the film without exposing it to the air, each layer interface can be formed without being contaminated by atmospheric components such as water and hydrocarbons and impurity elements floating in the air, resulting in variations in thin film transistor characteristics. can be reduced.

Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 103 by a photolithography process (see FIG. 1A). Alternatively, a resist mask for forming the island-shaped oxide semiconductor layer 103 may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced.

Next, first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer 103 .
The temperature of the first heat treatment for dehydration or dehydrogenation is 350° C. or higher and 750° C. or lower, preferably 425° C. or higher. Note that when the temperature is 425° C. or higher, the heat treatment time may be one hour or less, but when the temperature is lower than 425° C., the heat treatment time is longer than one hour. for example,
The substrate is introduced into an electric furnace, which is one of heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer 103 in a nitrogen atmosphere. The oxide semiconductor layer 103 can be obtained while preventing re-entrance of hydrogen. In this embodiment, the same furnace is used from the heating temperature T at which the oxide semiconductor layer 103 is dehydrated or dehydrogenated to a temperature sufficient to prevent water from entering again. Slowly cool in a nitrogen atmosphere until the temperature drops to 100°C or more. In addition, the dehydration or dehydrogenation is performed in an inert gas atmosphere (helium, neon, argon, etc.) without being limited to the nitrogen atmosphere.

By the first heat treatment, rearrangement at the atomic level of the oxide semiconductor forming the oxide semiconductor layer 103 is performed. The first heat treatment is important in that strain that inhibits carrier movement in the oxide semiconductor layer 103 can be released.

Note that in the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon preferably does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or rare gases such as helium, neon, and argon to be introduced into the heat treatment apparatus is 6N (99.9999%) or more,
It is preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

Further, the heat treatment apparatus for the first heat treatment is not limited to an electric furnace, and may be provided with an apparatus for heating an object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, G
RTA (Gas Rapid Thermal Anneal) device, LRTA (Lam
RTA (Rapid Thermal Anneal) equipment such as
rmal anneal) device can be used. An LRTA apparatus is an apparatus that heats an object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used.

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer might be crystallized to be a microcrystalline film or a polycrystalline film. Here, the oxide semiconductor layer may be a microcrystalline film with a crystallization rate of 80% or more. Further, depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may be a crystalless oxide semiconductor layer.

Alternatively, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor layer before being processed into the island-shaped oxide semiconductor layer 103 . In that case, after the first heat treatment, the substrate is taken out from the heating device and the photolithography process is performed.

Here, the results of hydrogen concentration analysis when the oxide semiconductor layer is dehydrogenated and when it is not dehydrogenated will be described. FIG. 3A is a schematic diagram of the cross-sectional structure of the sample used in this analysis. An oxynitride insulating layer 401 is formed over a glass substrate 400 by a plasma CVD method, and an oxynitride insulating layer 4 is formed.
An In--Ga--Zn--O-based oxide semiconductor layer 402 having a thickness of about 40 nm was formed on the 01 was prepared. The prepared samples were divided, one was not dehydrogenated, and the other was dehydrogenated at 650° C. for 6 minutes in a nitrogen atmosphere by the GRTA method. The effect of dehydrogenation by heat treatment was investigated by measuring the hydrogen concentration in the oxide semiconductor layer of each sample.

Hydrogen concentration measurement in the oxide semiconductor layer is performed by secondary ion mass spectrometry (SIMS: Seconda
Analyzes were performed on the Ion Mass Spectroscopy). FIG. 3B shows SIMS analysis results showing the hydrogen concentration distribution in the thickness direction of the oxide semiconductor layer. The horizontal axis indicates the depth from the surface of the sample, and the leftmost position at a depth of 0 nm corresponds to the outermost surface of the sample (the outermost surface of the oxide semiconductor layer). An analysis direction 403 shown in FIG. 3A indicates the analysis direction of SIMS analysis. The analysis was performed in the direction from the outermost surface of the oxide semiconductor layer toward the glass substrate 400 . In other words, on the horizontal axis of FIG. 3(B), the direction was from the left end to the right end. Figure 3 (B
) indicates the hydrogen concentration in the sample at a specific depth and the oxygen ion intensity on a logarithmic axis.

In FIG. 3B, a hydrogen concentration profile 412 shows the hydrogen concentration profile in the oxide semiconductor layer that is not dehydrogenated, and a hydrogen concentration profile 413 shows the hydrogen concentration profile after dehydrogenation by heat treatment. 4 shows a hydrogen concentration profile in an oxide semiconductor layer; An oxygen ion intensity profile 411 indicates the oxygen ion intensity obtained at the time of measuring the hydrogen concentration profile 412 . There is no extreme fluctuation in the oxygen ion intensity profile 411, and almost constant ion intensity is obtained, so it can be seen that the SIMS analysis is performed accurately. The oxygen ion intensity was also measured in the same way when measuring the hydrogen concentration profile 413, and a substantially constant ion intensity was obtained here as well. The hydrogen concentration profile 412 and the hydrogen concentration profile 413 are quantified using a standard sample formed using the same In--Ga--Zn--O-based oxide semiconductor layer as the sample.

In SIMS analysis, it is known that, due to its principle, it is difficult to obtain accurate data in the vicinity of the surface of a sample or in the vicinity of the interfaces of laminated films made of different materials. In this analysis, it is considered that accurate data is not obtained from the top surface of the sample to a depth of about 15 nm, so a depth of 15 n
It was evaluated using the profile after m.

From the hydrogen concentration profile 412, it can be seen that in the non-dehydrogenated oxide semiconductor layer, hydrogen is about 3×10 ²⁰ atoms/cm ³ or more and about 5×10 ²⁰ atoms/cm ³ or less, and the average hydrogen concentration is about 4. ×10 ²⁰ atoms/cm ³ are included. Further, from the hydrogen concentration profile 413, the average hydrogen concentration in the oxide semiconductor layer is reduced by about 2× due to dehydrogenation.
It can be seen that it can be reduced to 10 ¹⁹ atoms/cm ³ .

According to this analysis, the hydrogen concentration was reduced by SIMS analysis of a sample subjected to heat treatment at 650° C. for 6 minutes in a nitrogen atmosphere by the GRTA method, so it was confirmed that the oxide semiconductor layer was dehydrogenated in this heat treatment process. did it.

Then, a second heat treatment is performed. The temperature of the second heat treatment is higher than or equal to 100° C. and lower than or equal to the temperature of the first heat treatment. For example, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and
Alternatively, heat treatment is performed in an oxygen atmosphere.

Next, a conductive film for forming a source electrode layer and a drain electrode layer is formed over the gate insulating layer 102 and the oxide semiconductor layer 103 .

As a conductive film for forming the source electrode layer and the drain electrode layer, the gate electrode layer 101
Similarly, a metal conductive film can be used. Materials for the metal conductive film include Al, Cr,
It is preferable to use an element selected from Cu, Ta, Ti, Mo and W, an alloy containing the above elements, or an alloy combining the above elements. For example, a three-layer laminate structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminate structure in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer A structure is preferred. Of course, the metal conductive film may have a single layer structure, a two-layer structure, or a four-layer structure.
A laminated structure of more than one layer may be used.

A source electrode layer 105a and a drain electrode layer 105b are formed from a conductive film for forming a source electrode layer and a drain electrode layer by a photolithography step using a photomask (see FIG. 1B). At this time, part of the oxide semiconductor layer 103 is also etched to form the oxide semiconductor layer 103 having grooves (depressions).

Note that a resist mask for forming the source electrode layer 105a and the drain electrode layer 105b may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced.

Alternatively, an oxide conductive layer having lower resistance than the oxide semiconductor layer 103 may be formed between the oxide semiconductor layer 103 and the source electrode layer 105a and the drain electrode layer 105b. With such a stacked structure, the withstand voltage of the thin film transistor can be improved. Specifically, the carrier concentration of the oxide conductive layer with low resistance is, for example, 1×10 ²⁰ /cm ³ or more and 1×10
It is preferably in the range of ²¹ /cm ³ or less.

Next, an insulating layer 107 that covers the gate insulating layer 102, the oxide semiconductor layer 103, the source electrode layer 105a, and the drain electrode layer 105b and is in contact with part of the oxide semiconductor layer 103 is formed (
See FIG. 1(C)). The insulating layer 107 has a thickness of at least 1 nm and can be formed by a method such as a CVD method or a sputtering method that does not allow impurities such as water and hydrogen to enter the insulating layer 107 as appropriate. Here, the insulating layer 107 is formed using a sputtering method. The insulating layer 107 formed in contact with part of the oxide semiconductor layer 103 does not contain impurities such as moisture, hydrogen ions, oxygen ions, and OH ⁻ and is an inorganic material that blocks entry of these from the outside. An insulating film can be used, typically a silicon oxide film, a silicon nitride oxide film, a silicon nitride film, a gallium oxide film, an aluminum oxide film, an aluminum oxynitride film, or an aluminum nitride film.

Alternatively, the insulating layer 107 may have a structure in which a silicon nitride film or an aluminum nitride film is stacked over a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum oxynitride film. In particular, a silicon nitride film is preferable because it does not contain impurities such as moisture, hydrogen ions, oxygen ions, and OH ⁻ and easily blocks entry of these from the outside.

The substrate temperature during the formation of the insulating layer 107 may be room temperature or higher and 300° C. or lower. It can be carried out in a rare gas (typically argon) and oxygen atmosphere. Alternatively, a silicon oxide target or a silicon target can be used as the target.
For example, silicon oxide can be formed by a sputtering method in an oxygen atmosphere using a silicon target.

Then, a third heat treatment is performed. The third heat treatment is performed at a temperature of 100° C. or more and the temperature of the first heat treatment or less. For example, the substrate is introduced into an electric furnace, which is one of heat treatment apparatuses, and heat treatment is performed in a nitrogen atmosphere. The third heat treatment may be performed at any time after the insulating layer 107 is formed.

Through the above steps, the gate electrode layer 101 is provided over the substrate 100 which is a substrate having an insulating surface, the gate insulating layer 102 is provided over the gate electrode layer 101, and the oxide semiconductor layer is provided over the gate insulating layer 102. 103 is provided, and the source electrode layer 105 is provided over the oxide semiconductor layer 103 .
a and a drain electrode layer 105b are provided, and the gate insulating layer 102 and the oxide semiconductor layer 103 are provided.
, the insulating layer 107 covering the source electrode layer 105a and the drain electrode layer 105b and being in contact with part of the oxide semiconductor layer 103, the channel-etched thin film transistor 150.
can be formed (see FIG. 1(E)).

FIG. 1F is a top view of the thin film transistor 150 described in this embodiment. Figure 1 (E
) shows the cross-sectional configuration of the X1-X2 portion of FIG. 1(F). In FIG. 1F, L indicates the channel length and W indicates the channel width. Further, A indicates that the oxide semiconductor layer 103 is the source electrode layer 105a and the drain electrode layer 1 in the direction parallel to the channel width direction.
05b indicates the length of the region that does not overlap. Ls indicates the length of overlap between the source electrode layer 105a and the gate electrode layer 101, and Ld indicates the length of the drain electrode layer 105b and the gate electrode layer 101.
1 indicates the length of overlap.

In this embodiment mode, a thin film transistor with a single-gate structure is used as the thin film transistor 150; A thin film transistor having a structure can also be used.

In addition, although the method for manufacturing the channel-etched thin film transistor 150 is described in this embodiment, the structure of this embodiment is not limited to this. A bottom contact type (also called an inverse coplanar type) thin film transistor 160 with a bottom gate structure as shown in FIG. A thin film transistor 170 or the like (also referred to as a stop type) can be formed using similar materials and methods. FIG. 2C shows another example of a channel-etched thin film transistor. The width of the gate electrode layer 101 of the thin film transistor 180 illustrated in FIG. 2C is larger than the width of the oxide semiconductor layer 103 .

Note that the channel length of a thin film transistor (L in FIG. 1F) is defined by the distance between the source electrode layer 105a and the drain electrode layer 105b, but the channel length of a channel-protective thin film transistor is the direction in which carriers flow. is defined by the width of the channel protective layer in the direction parallel to .

According to this embodiment, the off-state current per 1 μm channel width of a thin film transistor including an oxide semiconductor layer can be reduced to 1×10 ⁻¹² A or less.

In addition, the channel length of the thin film transistor is in the range of 3 μm or more and 10 μm or less, or 1.
In the range of 5 μm or more to 100 μm or less, the off current per 1 μm of the channel width of the thin film transistor in the operating temperature range of −25° C. to 150° C. is 1×10 ⁻¹² A.
You can: The channel length of the thin film transistor is 1.5 μm or more, or 3 μm
It is preferable to set the distance to m or more because the short channel effect can be suppressed.

Here, the temperature was changed from −25° C. to 150° C. using the thin film transistor having the cross-sectional structure shown in FIG.
Evaluation results of the thin film transistor characteristics under the environment up to are explained.

First, a tungsten layer with a thickness of 100 nm is formed as a gate electrode layer 802 on a glass substrate 801 , and an oxynitride layer with a thickness of 10 nm is formed as a gate insulating layer 803 on the gate electrode layer 802 .
An In—Ga—Zn—O-based oxide semiconductor layer 804 is formed with a thickness of 30 nm over the gate insulating layer 803 , and a source electrode layer 805 is formed over the oxide semiconductor layer 804 .
A titanium layer was formed as a drain electrode layer 806 and a thin film transistor was manufactured. Note that the channel length L of the thin film transistor was set to 3 μm, and the channel width W was set to 20 μm.

Next, for the thin film transistors, the substrate temperature during measurement was -25°C, 0°C, 25°C, and 50°C.
C., 100.degree. C., and 150.degree. C., and the off current of the thin film transistor was measured at each substrate temperature (operating temperature). Off-current characteristic measurement is the voltage between source and drain (
The voltage between the source and the gate (hereinafter referred to as gate voltage or Vg) was -10V.

FIG. 4B shows the off-state current measurement results obtained in this measurement. The measurement temperature on the horizontal axis indicates the substrate temperature (operating temperature) at the time of measuring the off current of the thin film transistor on a linear scale, and the vertical axis indicates the off current (Ioff) at each substrate temperature on a log scale.

In FIG. 4B, "□" indicates the off current when an amorphous silicon film is used as the semiconductor layer, and "●" indicates the off current when an oxide semiconductor film is used as the semiconductor layer. It shows the off current.

From FIG. 4B, the off-current when using an amorphous silicon film as a semiconductor layer is
It can be seen that the off current increases as the substrate temperature increases during measurement. It can be seen that the off-current in the case of using the oxide semiconductor film as the semiconductor layer is 1 pA, that is, 1×10 ⁻¹² A or less even if the substrate temperature increases during measurement.

Here, the temperature dependence of the off current (Ioff) is considered below.

It is generally known that the off-state current of a thin film transistor flows due to generation of electrons and holes (hereinafter referred to as carrier generation) and recombination of electrons and holes (hereinafter referred to as carrier recombination). . In addition, the recombination of carriers includes direct recombination in which electrons are excited from the valence band (Ev) to the conduction band (Ec), and excitation via localized levels (Et) in the bandgap (Eg). There is an indirect recombination that is

In the case of a semiconductor with a narrow bandgap, the thermal energy required to excite electrons is small, so both direct and indirect recombination are likely to occur.
In the case of a semiconductor with a wide g), it was assumed that both direct recombination and indirect recombination are unlikely to occur because electron excitation requires large thermal energy.

Moreover, when the bandgap is wide, the intrinsic carrier concentration of the semiconductor is extremely low, and the total number of carriers is also extremely low. It was assumed that the off-state current would be reduced because the probability of carrier generation and carrier recombination would be reduced as a result of the reduced total number of carriers.

An attempt was made to calculate the temperature dependence of the off-state current of thin film transistors in semiconductors with different bandgaps (Eg).

The structure assumed in the calculation is shown in FIG. A tungsten layer of 100 nm is used as the gate electrode layer 701 .
An oxynitride layer with a thickness of 100 nm is formed as a gate insulating layer 702 over the gate electrode layer 701 , and a semiconductor layer 703 is formed with a thickness of 30 nm over the gate insulating layer 702 . A thin film transistor in which a source electrode layer 704 and a drain electrode layer 705 are formed over a semiconductor layer 703 is assumed.

The TFT size was L/W=10/1 μm. Semiconductor bandgap Eg=1.1e
V, 1.8 eV, and 3.15 eV, and the oxide semiconductor has a band gap Eg of 3.15 eV.
It is assumed to be 15 eV. Also, assuming that the electron affinity χ=4.3 eV, the source electrode layer 70
4 and the drain electrode layer 705 were assumed to have a work function of 4.3 eV, which is the same as the electron affinity of the oxide semiconductor. Further, the calculation was performed under three conditions of temperature T=25°C, 100°C, and 150°C. In addition, device simulation software A manufactured by Silvaco was used for the calculation.
tlas was used.

Considering that the defect levels strongly affect the temperature characteristics of amorphous semiconductors, the calculations were carried out assuming only direct recombination and assuming both direct and indirect recombination. The indirect recombination level is assumed to be in the center of the bandgap. The structures assumed in the calculation are shown in FIGS. 6(A) and 6(B). Two types of calculations were performed: FIG. 6(A) assuming only direct recombination and FIG. 6(B) assuming both direct recombination and indirect recombination.

In FIGS. 6A and 6B, "Ev" indicates the valence band, "Ec" the conductor, and "Et" the localized level. Further, the solid line assumes generation of carriers, and the dashed line assumes recombination of carriers.

Calculation results are shown in FIG. FIG. 29 shows the calculation results assuming that the bandgap (Eg)=1.1 eV, FIG. 29A shows the calculation results assuming only direct recombination, and FIG.
(B) is the calculation result when both direct recombination and indirect recombination are assumed.

Note that the spectrum 201 shown in FIG.
, and the spectrum 203 is the result of calculation assuming 150° C., and shown in FIG.
This is the calculation result assuming °C.

Calculation results are shown in FIG. FIG. 30 shows the calculation results assuming that the bandgap (Eg)=1.8 eV, and FIG. 30A shows the calculation results assuming only direct recombination.
(B) is the calculation result when both direct recombination and indirect recombination are assumed.

Note that the spectrum 311 shown in FIG.
, Spectrum 313 is the result of calculation assuming 150° C., and shown in FIG.
This is the calculation result assuming °C.

Calculation results are shown in FIG. FIG. 31 shows the calculation results assuming that the bandgap (Eg)=3.15 eV, FIG. 31A shows the calculation results assuming only direct recombination, and FIG.
1(B) is the calculation result when both direct recombination and indirect recombination are assumed.

Note that the spectrum 451 shown in FIG.
, spectrum 453 is the result of calculation assuming 150° C., and shown in FIG.
This is the calculation result assuming °C.

From FIG. 29B, assuming a bandgap (Eg) of 1.1 eV, an off current of 1×10 ⁻¹³ A or more is confirmed at 25° C., and 1×10 ⁻¹⁰ at 150° C. An off-current of A or more is confirmed, and it is found that there is temperature dependence.

From FIG. 30(B), assuming that the bandgap (Eg)=1.8 eV, FIG. 29(B)
Compared with the bandgap (Eg) of 1.1 eV, the off current at 25 °C is 1 × 10 ^-16
An off current of 1×10 ⁻¹³ A or less is confirmed at 150° C. or less, indicating that there is temperature dependence.

From FIG. 31(B), assuming that the bandgap (Eg)=3.15 eV, FIG.
) bandgap (Eg)=1.1 eV, and the bandgap (Eg
) = 1.8 eV, at three calculated temperatures of 25°C, 100°C and 150°C,
The off-current is 1×10 ⁻¹⁶ A or less, and the result is that there is no temperature dependence.

As described above, in the case of a semiconductor with a narrow bandgap, the thermal energy required to excite electrons is small, so both direct recombination and indirect recombination are likely to occur. In the case of a large semiconductor, a large amount of thermal energy is required to excite electrons, so the calculation results show that neither direct nor indirect recombination occurs.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 2)
In this embodiment mode, an example in which at least part of a driver circuit and a thin film transistor provided in a pixel portion are manufactured over the same substrate will be described below.

A thin film transistor arranged in a pixel portion is formed according to Embodiment Mode 1. FIG. Further, since the thin film transistor described in Embodiment Mode 1 is an n-channel TFT, part of a driver circuit which can be formed using an n-channel TFT is formed over the same substrate as the thin film transistor in the pixel portion. .

An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a signal line driver circuit 5304 are provided over a substrate 5300 of the display device. In the pixel portion 5301, a plurality of signal lines are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit 5304.
302 , and the scanning line driver circuit 5303 . Pixels each having a display element are arranged in a matrix in each intersection region between the scanning lines and the signal lines. Further, the substrate 5300 of the display device is FPC (Flexible Printed Circuit).
t), etc., to a timing control circuit 5305 (also called a controller or control IC).

In FIG. 7A, the first scan line driver circuit 5302, the second scan line driver circuit 5303, and the signal line driver circuit 5304 are formed over the same substrate 5300 as the pixel portion 5301. In FIG. for that reason,
Since the number of parts such as drive circuits provided outside is reduced, the cost can be reduced. In addition, the number of connections in connection portions can be reduced by extending wiring when a driver circuit is provided outside the substrate 5300, and reliability or yield can be improved.

Note that the timing control circuit 5305 supplies the first scanning line driver circuit 5302 with, for example, a first scanning line driver circuit start signal (GSP1) (start pulse) and a scanning line driver circuit clock signal (GCK1). supply. Further, the timing control circuit 5305 supplies the second scanning line driver circuit 5303 with, for example, a second scanning line driver circuit start signal (GSP2) (also referred to as a start pulse), a scanning line driver circuit clock signal ( GCK2)
supply. For the signal line driver circuit 5304, for example, a signal line driver circuit start signal (SSP), a signal line driver circuit clock signal (SCK), and a video signal data (DAT
A) (also simply referred to as a video signal) shall provide a latch signal (LAT). Each of the clock signals (GCK1, GCK2, SCK) may be a plurality of clock signals with different cycles, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that one of the first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 can be omitted.

In FIG. 7B, circuits with low driving frequencies (for example, the first scanning line driver circuit 5302, the second
A scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and a signal line driver circuit 5304 is formed on a substrate different from the pixel portion 5301. FIG. With this structure, a driver circuit formed over the substrate 5300 can be formed using a thin film transistor whose field-effect mobility is lower than that of a transistor using a single crystal semiconductor. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce the cost, improve the yield, or the like.

Further, the thin film transistor described in Embodiment 1 is an n-channel TFT. Figure 8(A)
FIG. 8B shows an example of the configuration and operation of a signal line driver circuit composed of n-channel TFTs.

The signal line driver circuit has a shift register 5601 and a switching circuit portion 5602 . The switching circuit section 5602 has a plurality of circuits called switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N are
Each has a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number). Thin film transistors 5603_1 to 5603_k are n-channel TFTs.
An example will be described.

The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. First terminals of the thin film transistors 5603_1 to 5603_k are each connected to a wiring 5604_1.
~5604_k. Second terminals of the thin film transistors 5603_1 to 5603_k are connected to the signal lines S1 to Sk, respectively. Thin film transistors 5603_1 to 5603_
The gate of k is connected to the wiring 5605_1.

The shift register 5601 sequentially outputs H-level (H signal, also referred to as high power supply potential level) signals to wirings 5605_1 to 5605_N, and switching circuits 5602_1 to 5602_56.
02_N in order.

The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk.
(conductivity between the first terminal and the second terminal), that is, the wiring 5604_
It has a function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk.
Thus, the switching circuit 5602_1 functions as a selector. Thin film transistors 5603_1 to 5603_N are connected to wirings 5604_1 to 5604_k, respectively.
and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k
to the signal lines S1 to Sk. Thus, the thin film transistor 56
03_1 to 5603_N each have a function as a switch.

Note that video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. Video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

Next, the operation of the signal line driver circuit in FIG. 8A is described with reference to the timing chart in FIG. 8B. Signals Sout_1 to Sout_N and signal Vda are shown in FIG.
An example of ta_1 to Vdata_k is shown. Signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata_k are examples of signals input to wirings 5604_1 to 5604_k, respectively. Note that one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN, for example. Each of the periods T1 to TN is a period for writing video signal data (DATA) to the pixels belonging to the selected row.

It should be noted that the rounding of signal waveforms and the like in each configuration shown in the drawings and the like of this embodiment may be exaggerated for clarity. Therefore, it is noted that the scale is not necessarily limited to that scale.

During periods T1 to TN, the shift register 5601 transmits an H level signal to the wiring 560.
5_1 to 5605_N are output in order. For example, in period T1, shift register 5
601 outputs a high-level signal to the wiring 5605_1. Then, the thin film transistors 5603_1 to 5603_k are turned on, so that the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are brought into conduction. At this time, the wirings 5604_1 to 5604_k include:
Data (S1) to Data (Sk) are input. Data (S1) to Data (Sk
) are written to the pixels in the 1st to k-th columns among the pixels belonging to the selected row through the thin film transistors 5603_1 to 5603_k, respectively. In this way, video signal data (DATA) is written in k columns in order to the pixels belonging to the selected row in the periods T1 to TN.

As described above, the number of video signal data (DATA) or the number of wirings can be reduced by writing the video signal data (DATA) to each pixel in a plurality of columns.
Therefore, the number of connections with external circuits can be reduced. In addition, since the video signal is written to the pixels for each of a plurality of columns, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

Note that the shift register 5601 and the switching circuit unit 5602 are the same as those in Embodiment 1.
1 can be used. In this case, the polarities of all the transistors included in the shift register 5601 can be n-channel.

Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register and a buffer. In some cases, it may also have a level shifter. In the scanning line driving circuit, a clock signal (CK) and a start pulse signal (SP) are applied to the shift register.
is input, a selection signal is generated. The generated select signal is buffer amplified in a buffer and supplied to the corresponding scan line. Gate electrodes of transistors of pixels for one line are connected to the scanning line. Since the transistors of the pixels for one line must be turned on all at once, a buffer capable of passing a large current is used.

One mode of a shift register used for part of the scan line driver circuit and/or the signal line driver circuit is described with reference to FIGS.

The shift registers of the scanning line driver circuit and the signal line driver circuit will be described with reference to FIGS. 9 and 10. FIG. The shift register includes a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 9A). The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG.
First clock signal CK1 from first wiring 11, second clock signal CK2 from second wiring 12, third clock signal CK3 from third wiring 13, fourth clock signal from fourth wiring 14 CK4 is supplied. Further, in the first pulse output circuit 10_1, the fifth wiring 15
A start pulse SP1 (first start pulse) is input from . In the second and subsequent n-th pulse output circuits 10_n (n is a natural number of 2 or more and N or less), the signal from the pulse output circuit of the previous stage (previous stage signal OUT (n−1)) (n is 2 natural numbers above) are input. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10 two stages later
_3 or the signal from the (n+2)-th pulse output circuit 10_n+2 two stages later (referred to as subsequent-stage signal OUT(n+2)) is input to the n-th pulse output circuit 10_n in the second and subsequent stages. Further, from the pulse output circuit of each stage, a first output signal OUT(1) (SR) for inputting to the pulse output circuit of the previous stage and/or the subsequent stage, and a second output signal OUT(1 ) is output. As shown in FIG. 9A, since the latter stage signal OUT(n+2) is not input to the last two stages of the shift register, for example, the second start pulse SP2 and the third The configuration may be such that the start pulse SP3 is input respectively.

Note that the clock signal (CK) is a signal that repeats an H level and an L level (also referred to as an L signal or a low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are delayed by 1/4 period in order. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control driving of the pulse output circuit. Note that the clock signal GCK
, and SCK, but will be explained as CK here.

The first input terminal 21 , the second input terminal 22 and the third input terminal 23 are connected to the first wiring 11
to any of the fourth wirings 14 are electrically connected. For example, in FIG. 9(B),
The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11, a second input terminal 22 electrically connected to the second wiring 12, and a third pulse output circuit 10_1. Input terminal 23 is electrically connected to third wiring 13 . In the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the second input terminal 22 is electrically connected to the third wiring 13. 3 input terminal 23 is electrically connected to the fourth wiring 14 .

Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth input terminal. Assume that it has an input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 9B). In the first pulse output circuit 10_1, the first input terminal 21 receives the first clock signal CK1, the second input terminal 22 receives the second clock signal CK2, and the third input terminal 23 receives the second clock signal CK2. A third clock signal CK3 is input, a start pulse SP1 is input to a fourth input terminal 24, a post-stage signal OUT(3) is input to a fifth input terminal 25, and a first clock signal is input from a first output terminal 26. output signal OUT(1) (SR) of the second output terminal 27
Therefore, the second output signal OUT(1) is output.

Note that the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N can use a 4-terminal thin film transistor instead of a 3-terminal thin film transistor. A transistor 28 illustrated in FIG. 9C is the four-terminal thin film transistor described in Embodiment 1.
It will be used below in drawings, etc. The transistor 28 is controlled by the first control signal G1 input to the first gate electrode and the second control signal G2 input to the second gate electrode.
It is an element that can perform electrical control between the terminal and the Out terminal.

The threshold voltage of the transistor 28 shown in FIG. 9C is obtained by providing gate electrodes above and below the channel formation region of the transistor 28 with gate insulating films interposed therebetween and controlling the potentials of the upper and/or lower gate electrodes. can be controlled to a desired value by

Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

The first pulse output circuit 10_1 includes the first transistor 31 to the thirteenth transistor 4
3 (see FIG. 9(D)). In addition to the above-described first input terminal 21 to fifth input terminal 25, first output terminal 26, and second output terminal 27, a first high power supply potential VDD
, a power supply line 52 supplied with the second high power supply potential VCC, and a power supply line 53 supplied with the low power supply potential VSS, the first transistor 31 to the thirteenth transistor 4
3 is supplied with a signal or a power supply potential. Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 9D is defined as first power supply potential VDD>second power supply potential VCC>third power supply potential VSS.
The first clock signal (CK1) to the fourth clock signal (CK4) are signals that alternate between H level and L level at regular intervals.
SS. By making the potential VCC of the power supply line 52 lower than the potential VDD of the power supply line 51, the potential applied to the gate electrode of the transistor can be kept low without affecting the operation of the transistor. can be reduced and deterioration can be suppressed. Note that, as illustrated in FIG. 9D, among the first transistor 31 to the thirteenth transistor 43, the first transistor 31 and the sixth to ninth transistors 36 to 39 are the transistors shown in FIG. ) is preferably used. The operations of the first transistor 31, the sixth transistor 36 to the ninth transistor 39 are transistors in which the potential of a node to which one of the source and drain electrodes is connected is switched by a control signal of the gate electrode. , and the transistor has a fast response to a control signal input to the gate electrode (rapid rise of on-current), thereby reducing malfunction of the pulse output circuit. Therefore, by using the four-terminal transistor 28 shown in FIG. 9C, the threshold voltage can be controlled, and the pulse output circuit can further reduce malfunction. Note that in FIG. 9C, the first
Although the same control signal is used as the control signal G1 and the second control signal G2, different control signals may be input.

9D, the first transistor 31 has a first terminal electrically connected to the power supply line 51, a second terminal electrically connected to the first terminal of the ninth transistor 39, and a gate electrode (
the first gate electrode and the second gate electrode) are electrically connected to the fourth input terminal 24 . The second transistor 32 has a first terminal electrically connected to the power supply line 53 , a second terminal electrically connected to the first terminal of the ninth transistor 39 , and a gate electrode of the fourth transistor 34 . It is electrically connected to the gate electrode. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first output terminal 26 . The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the first output terminal 26 . The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 . An electrode is electrically connected to the fourth input terminal 24 . The sixth transistor 36 has a first terminal connected to the power supply line 5 .
2, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrodes (the first gate electrode and the second
) is electrically connected to the fifth input terminal 25 . Seventh transistor 3
7 has a first terminal electrically connected to the power supply line 52, a second terminal electrically connected to the second terminal of the eighth transistor 38, and a gate electrode (first gate electrode and second gate electrode). electrode) is electrically connected to the third input terminal 23 . The eighth transistor 38 has a first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrodes (the first gate electrode and the second gate electrode) is the second input terminal 2
2 are electrically connected. The ninth transistor 39 has a first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32 , and a second terminal electrically connected to the gate electrode of the third transistor 33 . It is electrically connected to the gate electrode of the tenth transistor 40 , and the gate electrodes (first gate electrode and second gate electrode) are electrically connected to the power supply line 52 . The tenth transistor 40 has a first terminal connected to the first input terminal 21
, the second terminal is electrically connected to the second output terminal 27 , and the gate electrode is electrically connected to the second terminal of the ninth transistor 39 . Eleventh transistor 4
1, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrodes are the gate electrode of the second transistor 32 and the fourth transistor. It is electrically connected to the gate electrode of 34 . The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27,
A gate electrode is electrically connected to the gate electrode (the first gate electrode and the second gate electrode) of the seventh transistor 37 . The thirteenth transistor 43 has a first terminal connected to the power supply line 53 .
, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to the gate electrode (first gate electrode and second gate electrode) of the seventh transistor 37. properly connected.

In FIG. 9D, the gate electrode of the third transistor 33 and the tenth transistor 4
0 and the second terminal of the ninth transistor 39 are connected to each other.
In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is a node B (see FIG. 10A).

Note that a thin film transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region,
Current can flow through the drain, channel and source regions. here,
Since the source and the drain change depending on the structure, operating conditions, etc. of the thin film transistor, it is difficult to define which is the source or the drain. Therefore, regions that function as sources and drains are sometimes not called sources or drains. In that case, as an example, they may be referred to as a first terminal and a second terminal, respectively.

Note that in FIGS. 9D and 10A, a capacitor may be separately provided for performing bootstrap operation by bringing the node A into a floating state. Further, in order to hold the potential of the node B, a capacitor whose one electrode is electrically connected to the node B may be separately provided.

Here, FIG. 10B shows a timing chart of a shift register including a plurality of pulse output circuits shown in FIG. 10A. Note that when the shift register is the scanning line driving circuit, the period 61 in FIG. 10B is the vertical blanking period, and the period 62 corresponds to the gate selection period.

As shown in FIG. 10A, by providing the ninth transistor 39 to the gate of which the second power supply potential VCC is applied, the following advantages are obtained before and after the bootstrap operation. .

In the absence of the ninth transistor 39 whose gate electrode is applied with the second potential VCC, when the potential of the node A rises due to the bootstrap operation, the potential of the source, which is the second terminal, of the first transistor 31 rises. gradually becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, since a large bias voltage is applied between the gate and the source and between the gate and the drain, a large stress is applied to the first transistor 31, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to the gate electrode of which the second power supply potential VCC is applied, although the potential of the node A rises due to the bootstrap operation, the potential of the second terminal of the first transistor 31 increases. A rise in potential can be prevented. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and source of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of this embodiment, the negative bias voltage applied between the gate and source of the first transistor 31 can be reduced.
deterioration of the transistor 31 can be suppressed.

Note that the location where the ninth transistor 39 is provided is the same as the second transistor of the first transistor 31 .
Any configuration may be employed as long as the terminal is connected to the gate of the third transistor 33 via the first terminal and the second terminal. Note that in the case of the shift register including a plurality of pulse output circuits according to this embodiment, the ninth transistor 39 may be omitted in the signal line driver circuit having more stages than the scanning line driver circuit, thereby reducing the number of transistors. is an advantage.

Note that by using an oxide semiconductor for a semiconductor layer of each of the first transistor 31 to the thirteenth transistor 43, the off-state current of the thin film transistor can be reduced, the on-state current and the field-effect mobility can be increased, and the degree of deterioration can be reduced. can be reduced, so malfunctions in the circuit can be reduced. In addition, a transistor using an oxide semiconductor is less likely to deteriorate when a high potential is applied to its gate electrode than a transistor using amorphous silicon. Therefore, even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, the same operation can be obtained, and the number of power supply lines routed between circuits can be reduced. Miniaturization of the circuit can be achieved.

Note that the gate electrode of the seventh transistor 37 (the first gate electrode and the second gate electrode)
The clock signal supplied by the third input terminal 23 to the clock signal supplied by the second input terminal 22 to the gate electrodes (first gate electrode and second gate electrode) of the eighth transistor 38 are: The gate electrode of the seventh transistor 37 (the first gate electrode and the second
A clock signal supplied by a second input terminal 22 to the gate electrode of the eighth transistor 38 , and a third input terminal 23 to the gate electrode (the first gate electrode and the second gate electrode) of the eighth transistor 38 .
The same effect can be obtained by exchanging the connection relationship so that the clock signal is supplied by . Note that in the shift register illustrated in FIG. 10A, the seventh transistor 37 and the eighth transistor 38 are both on, the seventh transistor 37 is off, the eighth transistor 38 is on, and then the By turning off the seventh transistor 37 and turning off the eighth transistor 38, the second input terminal 22 and the third input terminal 23
The potential drop of the node B caused by the drop in the potential of the node B occurs twice due to the drop in the potential of the gate electrode of the seventh transistor 37 and the drop in the potential of the gate electrode of the eighth transistor 38 . becomes. On the other hand, the shift register shown in FIG.
By turning on the seventh transistor 37 and turning off the eighth transistor 38, and then turning off the seventh transistor 37 and turning off the eighth transistor 38, the second input terminal 22 and the A drop in the potential of the node B caused by a drop in the potential of the input terminal 23 of No. 3 can be reduced at once by a drop in the potential of the gate electrode of the eighth transistor 38 . Therefore, the gate electrode of the seventh transistor 37 (the first gate electrode and the second
A clock signal supplied by a third input terminal to the gate electrode of the eighth transistor 38 , and a clock signal supplied by a second input terminal to the gate electrode (first gate electrode and second gate electrode) of the eighth transistor 38 . This is preferable because noise can be reduced by reducing a change in the potential of the node B.

In this manner, the pulse output is performed by periodically supplying an H level signal to the node B while the potentials of the first output terminal 26 and the second output terminal 27 are held at an L level. Malfunction of the circuit can be suppressed.

By manufacturing the thin film transistor in the driver circuit by the method for manufacturing the thin film transistor described in Embodiment Mode 1, the thin film transistor in the driver circuit portion can operate at high speed and power can be saved.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 3)
In this embodiment mode, a case where a thin film transistor is manufactured and a semiconductor device having a display function (also referred to as a display device) is manufactured using the thin film transistor in a pixel portion and a driver circuit will be described. Further, part or all of a driver circuit can be formed over the same substrate as a pixel portion using a thin film transistor, whereby a system-on-panel can be formed.

A display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include elements whose luminance is controlled by current or voltage.
o Luminescence), organic EL, and the like. In addition, a display medium such as electronic ink whose contrast is changed by an electrical action can also be applied.

Also, the display device includes a panel in which a display element is sealed, and a module in which an IC including a controller is mounted on the panel. Furthermore, in the display device, an element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device is
Means are provided for each of the plurality of pixels for supplying current to the display element. Specifically, the element substrate may be in a state in which only the pixel electrodes of the display elements are formed, or after forming a conductive film to be the pixel electrodes, etching is performed to form the pixel electrodes. It may be in the previous state, and any form is applicable.

Note that the display device in this specification refers to an image display device or a light source (including a lighting device). Connectors such as FPC (Flexible printed c
(ircuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) mounted module, module with printed wiring board at the end of TAB tape or TCP, or COG (Chip On Glass) method for display element All modules in which an IC (integrated circuit) is directly mounted by , are also included in the display device.

In this embodiment, an example of a liquid crystal display device is described as a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, are described with reference to FIGS. FIG. 11 shows highly reliable thin film transistors 4010 and 4011 including In--Ga--Zn--O-based non-single-crystal films formed over a first substrate 4001 as semiconductor layers, and a liquid crystal element 4013, which are formed over a second substrate. 4006 and sealed with a sealing material 4005,
FIG. 11B is a top view of the panel, and FIG. 11B corresponds to a cross-sectional view taken along line MN of FIGS. 11A1 and 11A2.

A sealant 4005 is provided so as to surround a pixel portion 4002 provided over a first substrate 4001 and a scanning line driver circuit 4004 . A second substrate 4006 is provided over the pixel portion 4002 and the scanning line driver circuit 4004 . Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are formed by the first substrate 4001, the sealant 4005, and the second substrate 4006.
are sealed together with the liquid crystal layer 4008 . A signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001 . It is

The connection method of the drive circuit formed separately is not particularly limited, and the COG method,
A wire bonding method, a TAB method, or the like can be used. Fig. 11 (A1)
is an example of mounting the signal line driver circuit 4003 by the COG method, and FIG.
This is an example of mounting the signal line driver circuit 4003 by the TAB method.

The pixel portion 4002 and the scanning line driver circuit 4004 provided over the first substrate 4001 each include a plurality of thin film transistors. A thin film transistor 401 included in the line driver circuit 4004
1 are exemplified. Insulating layers 4020 and 40 are formed on the thin film transistors 4010 and 4011
21 are provided.

As the thin film transistors 4010 and 4011, the highly reliable thin film transistors including the oxide semiconductor layer described in Embodiment 1 can be used. In this embodiment mode, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

A conductive layer 4040 is provided over the insulating layer 4021 so as to overlap with a channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driver circuit. By providing the conductive layer 4040 so as to overlap with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. again,
The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011 or may have a different potential, and can function as a second gate electrode layer. Also, the conductive layer 4
040 may be GND, 0V, or floating.

A pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010 . The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40
06. A portion where the pixel electrode layer 4030 , the counter electrode layer 4031 , and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013 . Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with insulating layers 4032 and 4033 functioning as alignment films, respectively, and sandwich the liquid crystal layer 4008 with the insulating layers 4032 and 4033 interposed therebetween.

Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, FRP (Fiberglass-Reinforced Plastics) plate, PV
F (polyvinyl fluoride) film, polyester film or acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can also be used.

A spacer 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. . A spherical spacer may be used. In addition, the counter electrode layer 4
031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010 . The common connection portion can be used to electrically connect the counter electrode layer 4031 and the common potential line through the conductive particles arranged between the pair of substrates. Note that the conductive particles are contained in the sealing material 4005 .

Alternatively, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase is expressed only in a narrow temperature range, the liquid crystal layer 4008 is made of a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has low viewing angle dependency.

Note that although the liquid crystal display device described in this embodiment mode is an example of a transmissive liquid crystal display device, the liquid crystal display device may be a reflective liquid crystal display device or a transflective liquid crystal display device.

In the liquid crystal display device described in this embodiment mode, a polarizing plate is provided outside the substrate (visible side), and a colored layer and an electrode layer used for a display element are provided inside the substrate in this order. It may be provided inside. Also, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and may be appropriately set according to the materials of the polarizing plate and the colored layer and the manufacturing process conditions. A light-shielding film functioning as a black matrix may be provided as necessary.

Further, in this embodiment mode, insulating layers (insulating layers 4020 and 4021) functioning as a protective film or a planarizing insulating film for the thin film transistor are used in order to reduce the surface unevenness of the thin film transistor and to improve the reliability of the thin film transistor. It is configured to be covered with The protective film is intended to prevent intrusion of pollutants such as organic substances, metal substances, and water vapor floating in the atmosphere, and is preferably a dense film. The protective film is formed by sputtering a silicon oxide film,
A single layer or stacked layers of a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film may be formed. Although an example in which the protective film is formed by a sputtering method is shown in this embodiment mode, the protective film is not particularly limited and may be formed by various methods.

Here, an insulating layer 4020 having a stacked structure is formed as a protective film. Here, the insulating layer 402
As the first layer of 0, a silicon oxide film is formed using a sputtering method. The use of a silicon oxide film as the protective film is effective in preventing hillocks in aluminum films used as the source electrode layer and the drain electrode layer.

Also, an insulating layer is formed as the second layer of the protective film. Here, as the second layer of the insulating layer 4020, a silicon nitride film is formed by a sputtering method. When a silicon nitride film is used as the protective film, ions such as sodium can be prevented from entering the semiconductor region and changing the electrical characteristics of the TFT.

Also, after forming the protective film, the semiconductor layer may be annealed (at 300° C. to 400° C.).

In addition, an insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials)
, siloxane-based resin, PSG (phosphorus glass), BPSG (phosphor boron glass), and the like can be used. Note that the insulating layer 4021 may be formed by stacking a plurality of insulating films formed using these materials.

Note that the siloxane-based resin refers to Si—O—S formed using a siloxane-based material as a starting material.
Corresponds to resins containing i-bonds. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Moreover, the organic group may have a fluoro group.

The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, sputtering, S
OG method, spin coating, dip coating, spray coating, droplet discharge method (ink jet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When the insulating layer 4021 is formed using a material liquid, the semiconductor layer may be annealed (300° C. to 400° C.) at the same time as the baking step. A semiconductor device can be manufactured efficiently by combining the baking step of the insulating layer 4021 with the annealing step of the semiconductor layer.

The pixel electrode layer 4030 and the counter electrode layer 4031 are formed using indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide,
indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO),
A light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10000 Ω/□ or less and a light transmittance of 7 at a wavelength of 550 nm.
It is preferably 0% or more. Moreover, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or derivatives thereof, polypyrrole or derivatives thereof, polythiophene or derivatives thereof, or copolymers of two or more of these.

In addition, the signal line driver circuit 4003 and the scanning line driver circuit 4004 or the pixel portion 4 are separately formed.
002 are supplied from the FPC 4018.

In this embodiment mode, the connection terminal electrode 4015 is the pixel electrode layer 40 included in the liquid crystal element 4013 .
The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 .
11 is formed of the same conductive film as the source electrode layer and the drain electrode layer.

The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 through the anisotropic conductive film 4019 .

FIG. 11 shows an example in which the signal line driver circuit 4003 is separately formed and mounted over the first substrate 4001; however, this embodiment mode is not limited to this structure. The scanning line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or part of the scanning line driver circuit may be separately formed and mounted.

FIG. 12 shows an example in which a TFT substrate 2600 is used in a liquid crystal display module which corresponds to one mode of a semiconductor device.

FIG. 12 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed with a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, a colored layer 2605, and a polarizing plate are provided therebetween. 2606 are provided to form a display area. The colored layer 2605 is necessary for color display, and in the case of the RGB system, red, green,
A colored layer corresponding to each color of blue is provided corresponding to each pixel. A polarizing plate 2606 , a polarizing plate 2607 and a diffusion plate 2613 are arranged outside the TFT substrate 2600 and the counter substrate 2601 . A light source is composed of a cold cathode tube 2610 and a reflector 2611. A circuit board 2612 is connected to a wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. there is and a polarizing plate,
It may be laminated with a retardation plate between it and the liquid crystal layer.

Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (I
n-Plane-Switching) mode, FFS (Fringe Field S
switching) mode, MVA (Multi-domain Vertical A
alignment) mode, PVA (Patterned Vertical Align
nment), ASM (Axially Symmetrically aligned Mic
ro-cell) mode, OCB (Optical Compensated Bire
fringence) mode, FLC (Ferroelectric Liquid C
rystal) mode, AFLC (Anti-Ferroelectric Liquid
Crystal) mode or the like can be used.

Through the above steps, a highly reliable liquid crystal display device as a semiconductor device can be manufactured.

By manufacturing a thin film transistor in a pixel portion of a liquid crystal display device using the thin film transistor described in Embodiment 1, an increase in power consumption due to a change in off-state current of the thin film transistor in each pixel can be suppressed.

Further, by manufacturing a thin film transistor in a driver circuit of a liquid crystal display device by using the method for manufacturing a thin film transistor described in Embodiment 1, high-speed operation of the thin film transistor in the driver circuit portion can be realized and power consumption can be reduced.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 4)
An example of electronic paper is shown as one mode of a semiconductor device.

The thin film transistor of Embodiment 1 may be used for electronic paper in which an element electrically connected to a switching element is used to drive electronic ink. Electronic paper, also known as an electrophoretic display (electrophoretic display), has the advantages of being as easy to read as paper, consuming less power than other display devices, and being able to be made thin and light. ing.

Various forms of electrophoretic displays can be considered, but a plurality of microcapsules containing positively charged first particles and negatively charged second particles are dispersed in a solvent or solute. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to display only the color of the particles gathered on one side. The first particles or the second particles contain a dye and do not move in the absence of an electric field. Also, the color of the first particles and the color of the second particles are different (including colorless).

Thus, electrophoretic displays are characterized by the fact that materials with a high dielectric constant migrate to regions of high electric field,
This is a display that utilizes the so-called dielectrophoretic effect.

A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surface of glass, plastic, cloth, paper, and the like. Color display is also possible by using a color filter or pigment-containing particles.

Further, by arranging a plurality of microcapsules appropriately on an active matrix substrate so as to be sandwiched between two electrodes, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. can. For example, an active matrix substrate obtained by the thin film transistor of Embodiment Mode 1 can be used.

In addition, the first particles and the second particles in the microcapsules are a conductor material, an insulator material,
A material selected from a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof may be used.

FIG. 13 shows active matrix electronic paper as an example of a semiconductor device. A thin film transistor 581 used for a semiconductor device can be manufactured in a manner similar to that of the thin film transistor described in Embodiment 1 and is a highly reliable thin film transistor including an oxide semiconductor layer.

The electronic paper in FIG. 13 is an example of a display device using a twist ball display method. In the twist ball display method, spherical particles separately painted in white and black are arranged between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and the first electrode layer and the second electrode layer are arranged. In this method, display is performed by controlling the orientation of spherical particles by generating a potential difference between two electrode layers.

A thin film transistor 581 is a bottom-gate thin film transistor and is covered with an insulating film 583 in contact with a semiconductor layer. A source electrode layer or a drain electrode layer of the thin film transistor 581 is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the insulating layer 585 . A spherical particle 58 comprising a liquid-filled cavity 594 around which it has a black region 590a and a white region 590b between a first electrode layer 587 and a second electrode layer 588.
9 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (
See Figure 13). The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 581 . A common connection can be used to electrically connect the second electrode layer 588 and a common potential line through conductive particles disposed between the pair of substrates.

Also, an electrophoresis element can be used instead of the twist ball. 10 μm to 20 μm in diameter containing transparent liquid, positively charged white fine particles and negatively charged black fine particles
Microcapsules of about 0 μm are used. In the microcapsules provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, white fine particles and black fine particles are oriented in opposite directions. Can move to and display white or black. A display device to which this principle is applied is an electrophoretic display device, and is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than the liquid crystal display element, it does not require an auxiliary light, consumes less power, and can be recognized even in a dimly lit place. In addition, even when power is not supplied to the display unit, it is possible to hold an image that has been displayed once. It is possible to save the displayed image even when the device (also called a device) is moved away.

Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 5)
An example of a light-emitting display device is shown as a semiconductor device. As a display element included in the display device, a light-emitting element utilizing electroluminescence is used here. Light-emitting elements utilizing electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In the organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, recombination of these carriers (electrons and holes) causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to the element structure. A dispersion-type inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. A thin-film inorganic EL device has a light-emitting layer sandwiched between dielectric layers,
Furthermore, it is a structure in which it is sandwiched between electrodes, and the light emission mechanism is localized light emission using inner-shell electronic transition of metal ions. Note that an organic EL element is used as a light-emitting element in this description.

FIG. 14 is a diagram showing an example of a pixel configuration to which digital time grayscale driving can be applied as an example of a semiconductor device.

A configuration of a pixel to which digital time grayscale driving can be applied and an operation of the pixel will be described. Here, an example in which one pixel includes two n-channel transistors in which an oxide semiconductor layer is used for a channel formation region is shown.

A pixel 6400 includes a switching transistor 6401, a driving transistor 6402,
It has a light-emitting element 6404 and a capacitor 6403 . switching transistor 64
01 has a gate connected to the scanning line 6406, a first electrode (one of the source electrode and the drain electrode) is connected to the signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) is the gate of the driving transistor 6402. It is connected to the. The driving transistor 6402 is
The gate is connected to the power supply line 6407 through the capacitor 6403, and the first electrode is connected to the power supply line 640.
7 and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404 .
A second electrode of the light emitting element 6404 corresponds to the common electrode 6408 . Common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

Note that the second electrode (common electrode 6408) of the light emitting element 6404 is set to a low power supply potential. Note that the low power supply potential is a potential that satisfies low power supply potential<high power supply potential with reference to the high power supply potential set to the power supply line 6407. As the low power supply potential, for example, GND, 0 V, or the like is set. Also good. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 to cause the light emitting element 6404 to emit light. Each potential is set so as to be equal to or higher than the forward threshold voltage of .

Note that the capacitor 6403 can be omitted by using the gate capacitance of the driving transistor 6402 instead. As for the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

Here, in the case of the voltage input voltage driving method, the gate of the driving transistor 6402 has
A video signal is input such that the driving transistor 6402 is sufficiently turned on or turned off. That is, the driving transistor 6402 is operated in the linear region.
In order to operate the driving transistor 6402 in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402 . Note that the signal line 6405 includes
A voltage equal to or higher than (power supply line voltage+Vth of driving transistor 6402) is applied.

When analog grayscale driving is performed instead of digital time grayscale driving, the same pixel configuration as in FIG. 14 can be used by changing the signal input method.

When performing analog gradation driving, a light emitting element 6404 is connected to the gate of the driving transistor 6402 .
+ Vth of the driving transistor 6402 or more is applied. light emitting element 64
The forward voltage in 04 indicates a voltage at which a desired luminance is obtained, and includes at least a forward threshold voltage. By inputting a video signal that causes the driving transistor 6402 to operate in a saturation region, current can flow to the light emitting element 6404 . In order to operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402 . By using an analog video signal, a current corresponding to the video signal can be supplied to the light emitting element 6404 to perform analog gradation driving.

Note that the pixel configuration shown in FIG. 14 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, logic circuit, or the like may be added to the pixel shown in FIG.

Next, the structure of the light-emitting element will be described with reference to FIG. Here, the number of driving TFTs is n
Taking the case of a mold as an example, the cross-sectional structure of a pixel will be described. The TFTs 7001, 7011, and 7021, which are driving TFTs used in the light-emitting elements in FIGS. It is a thin film transistor with high .

At least one of the anode and the cathode of the light-emitting element should be transparent in order to emit light. Then, a thin film transistor and a light emitting element are formed on a substrate, and top emission for extracting light from the surface opposite to the substrate, bottom emission for extracting light from the surface on the substrate side, and surface on the side of the substrate and the surface opposite to the substrate. There is a light emitting element with a double emission structure in which light is extracted from the light emitting element, and the pixel configuration can be applied to the light emitting element with any emission structure.

A light-emitting element with a bottom emission structure is described with reference to FIG.

A cross-sectional view of a pixel in the case where the driving TFT 7011 is n-type and light emitted from the EL layer 7014 is emitted to the cathode 7013 side is shown. In FIG. 15A, a cathode 7013 of a light-emitting element 7012 is formed over a light-transmitting conductive film 7017 electrically connected to a driving TFT 7011 , and an EL layer 7014 and an anode 7015 are formed over the cathode 7013 . are stacked in order.
Note that the light-transmitting conductive film 7017 is electrically connected to the drain electrode layer of the driving TFT 7011 through a contact hole formed in the oxide insulating layer 7031 .

As the light-transmitting conductive film 7017, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or indium tin oxide ( (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

Although various materials can be used for the cathode 7013, materials with a small work function, specifically, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In FIG. 15A, the thickness of the cathode 7013 is such that light can be transmitted (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode 7013 .

Note that the light-transmitting conductive film 7017 and the cathode 7013 may be formed by selectively etching after stacking a light-transmitting conductive film and an aluminum film; in this case, the same mask is used. It can be etched by using

In addition, the periphery of the cathode 7013 is covered with a partition wall 7019 . The partition 7019 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition wall 7019 is preferably made of a particularly photosensitive resin material, has an opening formed above the cathode 7013, and is preferably formed so that the side wall of the opening forms an inclined surface having a continuous curvature. When a photosensitive resin material is used for the partition 7019, a step of forming a resist mask can be omitted.

Further, the EL layer 7014 formed over the cathode 7013 and the partition wall 7019 may be composed of a single layer or a laminate of a plurality of layers. EL layer 70
When 14 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on the cathode 7013 in this order. Note that it is not necessary to provide all of these layers.

Further, the stacking order is not limited to the above, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be stacked on the cathode 7013 in this order. However, when comparing the power consumption, it is preferable to stack an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer on the cathode 7013 in this order because power consumption is low.

Various materials can be used for the anode 7015 formed over the EL layer 7014. Materials with a large work function, such as titanium nitride, ZrN, Ti, W, Ni, Pt,
A transparent conductive material such as Cr or the like, ITO, IZO (indium zinc oxide), or ZnO is preferable. Also, a shielding film 7016 such as a metal that blocks light or a metal that reflects light is formed on the anode 7015 . In this embodiment, an ITO film is used as the anode 7015 and a Ti film is used as the shielding film 7016 .

A region where at least the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light emitting element 7012 . In the case of the element structure shown in FIG. 15A, light emitted from the light emitting element 7012 is emitted to the cathode 7013 side as indicated by arrows.

Note that FIG. 15A shows an example in which a light-transmitting conductive film is used as the gate electrode layer. is injected through the gate electrode layer and the source electrode layer. TFs
By using a light-transmitting conductive film for the gate electrode layer and the source electrode layer of T7011, the aperture ratio can be improved.

The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

In addition, the color filter layer 7033 is covered with an overcoat layer 7034, and the insulating layer 703
035. Note that the overcoat layer 7034 has a thin film thickness in FIG.

In addition, the contact hole formed in the insulating layer 7035 and reaching the drain electrode layer is
It is arranged at a position overlapping with the partition wall 7019 . In FIG. 15A, the contact hole reaching the drain electrode layer and the partition 7019 are overlapped with each other, so that the aperture ratio can be improved.

Next, a light-emitting element with a dual emission structure is described with reference to FIG.

In FIG. 15B, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive film 7027 electrically connected to a TFT 7021 which is a driving TFT.
23, an EL layer 7024 and an anode 7025 are stacked in this order. Note that the light-transmitting conductive film 7027 is connected to the TFT 70 through a contact hole formed in the oxide insulating layer 7041 .
21 is electrically connected to the drain electrode layer.

As the light-transmitting conductive film 7027, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or indium tin oxide ( (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used.

Although various materials can be used for the cathode 7023, materials with a small work function, specifically, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In this embodiment, the thickness of the cathode 7023 is such that light can be transmitted (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is used as the cathode 7023 .

Note that the light-transmitting conductive film 7027 and the cathode 7023 may be formed by selectively etching after stacking a light-transmitting conductive film and an aluminum film; in this case, the same mask is used. It can be etched by using

In addition, the periphery of the cathode 7023 is covered with a partition wall 7029 . The partition 7029 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition wall 7029 is preferably made of a particularly photosensitive resin material, has an opening formed above the cathode 7023, and is preferably formed so that the side wall of the opening forms an inclined surface having a continuous curvature. When a photosensitive resin material is used for the partition 7029, a step of forming a resist mask can be omitted.

Further, the EL layer 7024 formed over the cathode 7023 and the partition 7029 may be composed of a single layer or a laminate of a plurality of layers. EL layer 70
24 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on the cathode 7023 in this order. Note that it is not necessary to provide all of these layers.

Further, the stacking order is not limited to the above, and the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be stacked on the cathode 7023 in this order. However, when power consumption is compared, it is preferable to stack an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, and a hole-injection layer on the cathode 7023 in this order because power consumption is low.

Various materials can be used for the anode 7025 formed over the EL layer 7024, but materials with a large work function, such as transparent conductive materials such as ITO, IZO, and ZnO, are preferable. In this embodiment mode, an ITO film containing silicon oxide is used as the anode 7026 .

A light-emitting element 7022 is a region where the EL layer 7024 is sandwiched between the cathode 7023 and the anode 7025.
corresponds to In the element structure shown in FIG. 15B, light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Note that FIG. 15B shows an example in which a light-transmitting conductive film is used as the gate electrode layer, and light emitted from the light-emitting element 7022 toward the cathode 7023 is
, and passes through the gate electrode layer and the source electrode layer of the TFT 7021 to be emitted. TFT
By using a light-transmitting conductive film for the gate electrode layer and the source electrode layer of 7021, the aperture ratio on the anode 7025 side and that on the cathode 7023 side can be made substantially the same.

The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography technique, or the like.

In addition, the color filter layer 7043 is covered with an overcoat layer 7044, and the insulating layer 704
045.

Further, the contact hole formed in the insulating layer 7045 and reaching the drain electrode layer is
It is arranged at a position overlapping with the partition wall 7029 . The opening ratio on the anode 7025 side and the cathode 7023 side can be made substantially the same by adopting a layout in which the contact hole reaching the drain electrode layer overlaps the partition wall 7029 .

A contact hole formed in the insulating layer 7045 and reaching the light-transmitting conductive film 7027 is arranged so as to overlap with the partition wall 7029 .

However, when using a light-emitting element with a double-sided emission structure and both display surfaces are full-color,
Since light from the anode 7025 side does not pass through the color filter layer 7043 , it is preferable to separately provide a sealing substrate having a color filter layer above the anode 7025 .

Next, a light-emitting element with a top emission structure is described with reference to FIG.

FIG. 15C shows a cross-sectional view of a pixel when the TFT 7001 which is a driving TFT is of n-type and light emitted from the light emitting element 7002 passes through the anode 7005 side. In FIG. 15(C),
Cathode 700 of light-emitting element 7002 electrically connected to TFT 7001 through a connection electrode layer
3 is formed, and an EL layer 7004 and an anode 7005 are stacked in this order on a cathode 7003 .

Although various materials can be used for the cathode 7003, materials with a small work function, specifically, alkali metals such as Li and Cs, alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

In addition, the periphery of the cathode 7003 is covered with a partition wall 7009 . The partition 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition 7009 is preferably made of a particularly photosensitive resin material, has an opening above the cathode 7003, and is preferably formed so that the side wall of the opening forms an inclined surface with a continuous curvature. When a photosensitive resin material is used for the partition 7009, a step of forming a resist mask can be omitted.

Further, the EL layer 7004 formed over the cathode 7003 and the partition wall 7009 may be composed of a single layer or a laminate of a plurality of layers. EL layer 70
When 04 is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are laminated on the cathode 7003 in this order. Note that it is not necessary to provide all of these layers.

Moreover, the order of stacking is not limited to the above, and a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer may be stacked on the cathode 7003 in this order. When laminating in this order, the cathode 700
3 will function as an anode.

In FIG. 15C, a Ti film, an aluminum film, and a Ti film are stacked in this order, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are stacked in this order, and Mg is formed thereon. :A
A lamination of g alloy thin film and ITO is formed.

However, when power consumption is compared, an electron injection layer, an electron transport layer, a light emitting layer,
It is preferable to stack the hole transport layer and the hole injection layer in this order because power consumption is low.

The anode 7005 is formed using a light-transmitting conductive material that transmits light, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive film such as indium tin oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

A region where the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light emitting element 7002 . In the case of the pixel shown in FIG. 15C, light emitted from the light emitting element 7002 is emitted to the anode 7005 side as indicated by arrows.

FIG. 15C shows an example in which the thin film transistor 150 is used as the TFT 7001, but the thin film transistors 160, 170, and 180 can be used.

15C, the drain electrode layer of the TFT 7001 is electrically connected to the connection electrode layer through the oxide insulating layer 7051, and the connection electrode layer is composed of the insulating layers 7052 and 70.
55 to the cathode 7003 . The planarizing insulating layer 7053 is polyimide,
Resin materials such as acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane resins, P
SG (phosphor glass), BPSG (phosphor boron glass), or the like can be used. Note that the planarization insulating layer 7053 may be formed by stacking a plurality of insulating films formed using any of these materials. A method for forming the planarization insulating layer 7053 is not particularly limited, and depending on the material, a sputtering method, an SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (inkjet method, screen printing, offset printing, etc.) can be used. , doctor knife, roll coater,
A curtain coater, a knife coater, or the like can be used.

A partition wall 7009 is provided to insulate the cathode 7003 from the cathodes of adjacent pixels.
The partition 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or organic polysiloxane. The partition 7009 is preferably made of a particularly photosensitive resin material, has an opening above the cathode 7003, and is preferably formed so that the side wall of the opening forms an inclined surface with a continuous curvature.

In addition, in the structure of FIG. 15C, when full color display is performed, for example, the light emitting element 70
02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other light emitting element is a blue light emitting element. In addition to the three types of light-emitting elements, 4
A light-emitting display device capable of full-color display may be manufactured using various types of light-emitting elements.

In the structure of FIG. 15C, all the plurality of light emitting elements to be arranged are white light emitting elements, and a sealing substrate having a color filter or the like is arranged above the light emitting element 7002.
A light-emitting display device capable of full-color display may be manufactured. Full-color display can be performed by forming a material that emits monochromatic light such as white and combining it with a color filter or a color conversion layer.

Of course, monochromatic light emission display may be performed. For example, a lighting device may be formed using white light emission, or an area color type light emitting device may be formed using monochromatic light emission.

Moreover, if necessary, an optical film such as a polarizing film such as a circularly polarizing plate may be provided.

Note that although the organic EL element is described as the light emitting element here, the inorganic E element is used as the light emitting element.
It is also possible to provide an L element.

Note that an example in which a thin film transistor (driving TFT) for controlling driving of the light emitting element and the light emitting element are electrically connected is shown, but a current controlling TFT is connected between the driving TFT and the light emitting element. It may be a configuration with

Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described with reference to FIGS. FIG. 16A is a plan view of a panel in which a thin film transistor and a light-emitting element formed over a first substrate are sealed with a sealing material between them and a second substrate, and FIG. , corresponds to a cross-sectional view taken along line HI of FIG. 16(A).

A pixel portion 4502 and signal line driver circuits 4503a and 450 provided over a first substrate 4501
3b, and scanning line driver circuits 4504a and 4504b, a sealing material 4505
is provided. A second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuit 45
04a, 4504b are sealed together with filler 4507 by first substrate 4501, sealing material 4505 and second substrate 4506. FIG. It is preferable to package (enclose) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and little outgassing so as not to be exposed to the outside air.

In addition, a pixel portion 4502 and signal line driver circuits 4503a and 4503a, 4503a and 4503a, 4503a and 4503a, 4503a and 4503a, 4503a and 4503a, 4503a, 4503a, and 4503a, 4503a and 4503a,
503b and the scan line driver circuits 4504a and 4504b include a plurality of thin film transistors. FIG. 15B illustrates a thin film transistor 4510 included in the pixel portion 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503a. are doing.

As the thin film transistors 4509 and 4510, the highly reliable thin film transistors including the oxide semiconductor layer described in Embodiment 1 can be used. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

A conductive layer 4540 is provided over the insulating layer 4544 so as to overlap with the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driver circuit. By providing the conductive layer 4540 so as to overlap with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the thin film transistor 4509 before and after the BT test can be reduced. The conductive layer 4540 may have the same potential as or different potential from the gate electrode layer of the thin film transistor 4509, and can function as a second gate electrode layer. Also, the conductive layer 45
The potential of 40 may be GND, 0V, or floating.

In the thin film transistor 4509, an insulating layer 4541 is formed as an insulating film in contact with the semiconductor layer including the channel formation region. The insulating layer 4541 is the insulating layer 107 described in Embodiment 1.
It may be formed with the same material and method as . In addition, the thin film transistor is covered with an insulating layer 4544 functioning as a planarization insulating film in order to reduce the unevenness of the surface of the thin film transistor. Here, as the insulating layer 4541, a silicon oxide film is formed by a sputtering method in a manner similar to that of the insulating layer 107 described in Embodiment 1. FIG.

In addition, an insulating layer 4544 is formed as a planarization insulating film. The insulating layer 4544 may be formed using a material and a method similar to those of the insulating layer 4021 described in Embodiment 2. Here, acrylic is used as the insulating layer 4544 .

A first electrode layer 4517 which is a pixel electrode included in the light emitting element 4511 is electrically connected to a source electrode layer or a drain electrode layer of the thin film transistor 4510 . Note that although the structure of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, it is not limited to the structure shown. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4511 or the like.

The partition 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane.
In particular, it is preferable to use a photosensitive material, form an opening over the first electrode layer 4517, and form an inclined surface with a continuous curvature on the side wall of the opening.

The electroluminescent layer 4512 may be composed of a single layer or may be composed of a plurality of stacked layers.

A protective film may be formed over the second electrode layer 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4511 . As the protective film, a silicon nitride film,
A silicon oxynitride film, a DLC film, or the like can be formed.

Further, signal line driver circuits 4503a and 4503b and scanning line driver circuits 4504a and 4504b
, or various signals and potentials applied to the pixel portion 4502 are FPCs 4518a, 4518
supplied by b.

The connection terminal electrode 4515 is formed using the same conductive film as the first electrode layer 4517 included in the light emitting element 4511, and the terminal electrode 4516 is formed using the same conductive film as the source electrode layer and the drain electrode layer included in the thin film transistors 4509 and 4510. ing.

The connection terminal electrode 4515 is electrically connected to a terminal of the FPC 4518a through an anisotropic conductive film 4519. FIG.

A substrate positioned in the direction in which light is extracted from the light emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

As the filler 4507, in addition to an inert gas such as nitrogen or argon, an ultraviolet curing resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic,
Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV
A (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

In addition, if necessary, a polarizing plate or a circularly polarizing plate (including an elliptical polarizing plate) is provided on the exit surface of the light emitting element.
A retardation plate (λ/4 plate, λ/2 plate), an optical film such as a color filter may be provided as appropriate. Also, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be applied to diffuse reflected light by unevenness of the surface and reduce glare.

The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b may be mounted with a driver circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film over a separately prepared substrate. In addition, only or part of the signal line driver circuit, or only or part of the scanning line driver circuit may be separately formed and mounted, and the configuration is not limited to that of FIG.

Through the above steps, a highly reliable light-emitting display device (display panel) as a semiconductor device can be manufactured.

By manufacturing a thin film transistor in a pixel portion of a light-emitting display device using the method for manufacturing a thin film transistor described in Embodiment 1, power consumption due to a change in off-state current of the thin film transistor in each pixel can be reduced.

Further, by manufacturing a thin film transistor in a driver circuit of a light-emitting display device by the method for manufacturing a thin film transistor described in Embodiment 1, high-speed operation of the thin film transistor in the driver circuit portion can be achieved and power consumption can be reduced.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 6)
In this embodiment, as one mode of a semiconductor device, an example of a liquid crystal display device using a liquid crystal element including the thin film transistor described in Embodiment 1 will be described with reference to FIGS. Figure 17
The thin film transistors described in Embodiment 1 can be applied to the TFTs 628 and 629 used in the liquid crystal display devices of FIGS. be. The TFTs 628 and 629 are thin film transistors whose channel formation regions are oxide semiconductor layers. 17 to 20
Although the case where the thin film transistor illustrated in FIG. 2C is used as an example of the thin film transistor is described, the present invention is not limited to this.

A VA (Vertical Alignment) type liquid crystal display device will be described below.
A VA-type liquid crystal display device is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is of a type in which the liquid crystal molecules are oriented perpendicularly to the panel surface when no voltage is applied. In this embodiment, a pixel is particularly divided into several regions (sub-pixels), and the molecules are tilted in different directions. This is called multi-domainization or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

18 and 19 show the pixel electrode and counter electrode, respectively. Note that FIG. 18 is a plan view of the substrate side on which the pixel electrodes are formed, and FIG. 17 shows a cross-sectional structure corresponding to the cutting line EF shown in the drawing. Also, FIG. 19 is a plan view of the substrate side on which the counter electrode is formed. The following description refers to these figures.

FIG. 17 shows a state in which a substrate 600 on which a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor portion 630 are formed, and a counter substrate 601 on which a counter electrode 640 and the like are formed are overlapped and liquid crystal is injected. showing.

A first colored film 636, a second
A colored film (not shown), a third colored film (not shown), and a counter electrode 640 are formed. With this structure, the projections 644 for controlling the alignment of the liquid crystal and the spacers have different heights. An alignment film 648 is formed on the pixel electrode 624 , and an alignment film 646 is similarly formed on the counter electrode 640 . A liquid crystal layer 650 is formed between them.

Although columnar spacers are used here as spacers, bead spacers may be scattered. Here, the columnar spacer means an organic film or an inorganic film formed on one of the substrates, patterned and etched to a predetermined size by a photolithography process, or a positive or negative patternable organic film. The columnar spacer can control the thickness of the liquid crystal layer. Furthermore, spacers may be formed on the pixel electrodes 624 formed on the substrate 600 .

A TFT 628 , a pixel electrode 624 connected thereto, and a storage capacitor portion 63 are formed on the substrate 600 .
0 is formed. The pixel electrode 624 includes a TFT 628, a wiring 616, and a storage capacitor portion 630.
and a third insulating film 622 covering the insulating film 620 . The thin film transistor described in Embodiment Mode 1 can be used as the TFT 628 as appropriate. The storage capacitor portion 630 includes a capacitor wiring 604 which is a first capacitor wiring formed at the same time as the gate wiring 602 of the TFT 628 and the gate insulating film 60 .
6 and a capacitance wiring 617 which is a second capacitance wiring formed at the same time as the wirings 616 and 618 .

A liquid crystal element is formed by overlapping the pixel electrode 624 , the liquid crystal layer 650 , and the counter electrode 640 .

The structure on the substrate 600 is shown in FIG. The pixel electrode 624 is made of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or indium tin oxide (hereinafter referred to as ITO). ), indium zinc oxide, and indium tin oxide to which silicon oxide is added.

Alternatively, the pixel electrode 624 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10000Ω/□ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or derivatives thereof, polypyrrole or derivatives thereof, polythiophene or derivatives thereof, or copolymers of two or more of these.

A slit 625 is provided in the pixel electrode 624 . The slit 625 is for controlling the alignment of the liquid crystal.

The TFT 628 shown in FIG. 18 and the pixel electrode 626 and the storage capacitor section 631 connected thereto can be formed in the same manner as the TFT 628, the pixel electrode 624 and the storage capacitor section 630, respectively. Both the TFT 628 and the TFT 629 are connected to the wiring 616 . A picture element (pixel) of this liquid crystal display panel is composed of a pixel electrode 624 and a pixel electrode 626 . Pixel electrode 624 and pixel electrode 626 constitute a sub-pixel.

FIG. 19 shows the structure on the counter substrate side. The counter electrode 640 is preferably formed using a material similar to that of the pixel electrode 624 . A protrusion 644 is formed on the counter electrode 640 to control the orientation of the liquid crystal.

An equivalent circuit of this pixel structure is shown in FIG. Both the TFT 628 and the TFT 629 are connected to the gate wiring 602 and the wiring 616 . In this case, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different by making the potentials of the capacitor wiring 604 and the capacitor wiring 605 different. That is, by individually controlling the potentials of the capacitor wiring 604 and the capacitor wiring 605, the orientation of the liquid crystal is precisely controlled to widen the viewing angle.

When a voltage is applied to the pixel electrode 624 provided with the slit 625 , electric field distortion (oblique electric field) is generated in the vicinity of the slit 625 . This slit 625 and the projection 6 on the counter substrate 601 side
44 are alternately interlocked to effectively generate an oblique electric field to control the orientation of the liquid crystal, thereby making the orientation direction of the liquid crystal different depending on the location. That is, the viewing angle of the liquid crystal display panel is widened by multi-domain.

Next, a VA liquid crystal display device different from the above will be described with reference to FIGS.

21 and 22 show the pixel structure of a VA liquid crystal display panel. FIG. 22 shows a substrate 600
FIG. 21 is a plan view of FIG. 21, and FIG. 21 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will be made with reference to these two figures.

In this pixel structure, one pixel has a plurality of pixel electrodes, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. That is, in a pixel designed in a multi-domain, it has a configuration in which signals applied to individual pixel electrodes are independently controlled.

The pixel electrode 624 is connected to the TFT 628 through the wiring 618 through the contact hole 623 . In addition, the pixel electrode 626 is connected to the contact hole 627 and the wiring 619 to the TFT.
629 is connected. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be applied. On the other hand, a wiring 616 functioning as a data line is shared by the TFTs 628 and 629 . The thin film transistors described in Embodiment Mode 1 can be used as appropriate for the TFTs 628 and 629 . A capacitor wiring 690 is also provided.

The pixel electrodes 624 and 626 have different shapes and are separated by a slit 625 . A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 extending in a V shape. The timing of the voltage applied to the pixel electrode 624 and the pixel electrode 626 is controlled by the TFT 628
and the TFT 629 to control the orientation of the liquid crystal. An equivalent circuit of this pixel structure is shown in FIG. The TFT 628 is connected to the gate wiring 602 and the TFT 629 is connected to the gate wiring 603 . By applying different gate signals to the gate wiring 602 and the gate wiring 603, the operation timings of the TFTs 628 and 629 can be made different.

A colored film 636 and a counter electrode 640 are formed on the counter substrate 601 . In addition, the colored film 6
A flattening film 637 is formed between 36 and the counter electrode 640 to prevent alignment disorder of the liquid crystal. FIG. 23 shows the structure on the counter substrate side. The counter electrode 640 is an electrode that is shared between different pixels, and has slits 641 formed therein. This slit 641 and the pixel electrode 62
4 and the slits 625 on the pixel electrode 626 side are arranged so as to alternately mesh with each other, an oblique electric field can be effectively generated to control the alignment of the liquid crystal. As a result, the direction in which the liquid crystal is oriented can be changed depending on the location, and the viewing angle is widened.

A first liquid crystal element is formed by overlapping the pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 together. A second liquid crystal element is formed by overlapping the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 together. Further, it has a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel.

In this embodiment mode, the liquid crystal display device having the thin film transistor described in Embodiment Mode 1 is V.
Although the A-type liquid crystal display device has been described, the present invention can also be applied to an IPS-type liquid crystal display device, a TN-type liquid crystal display device, and the like.

By manufacturing a thin film transistor in a pixel portion of a light-emitting display device using the method for manufacturing a thin film transistor described in Embodiment 1, power consumption due to a change in off-state current of the thin film transistor in each pixel can be reduced.

(Embodiment 7)
The semiconductor device disclosed in this specification can be applied as electronic paper. Electronic paper can be used for electronic equipment in all fields as long as it displays information. For example, electronic paper can be used for electronic books (electronic books), posters, in-vehicle advertisements in vehicles such as trains, and display on various cards such as credit cards. An example of electronic equipment is shown in FIG.

FIG. 25 shows an example of an electronic book 2700. As shown in FIG. For example, the electronic book 2700 is
It consists of two housings, 701 and housing 2703 . Housing 2701 and housing 27
03 are integrated by a shaft portion 2711, and can be opened and closed with the shaft portion 2711 as an axis. With such a configuration, it is possible to operate like a paper book.

A display portion 2705 is incorporated in the housing 2701 and a display portion 2707 is incorporated in the housing 2703 . The display units 2705 and 2707 may be configured to display a continuation screen or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, text can be displayed on the right display portion (the display portion 2705 in FIG. 25) and an image can be displayed on the left display portion (the display portion 2707 in FIG. 25). .

In addition, FIG. 25 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, case 2
701 includes a power source 2721, operation keys 2723, a speaker 2725, and the like. An operation key 2723 can be used to turn pages. Note that a keyboard, a pointing device, and the like may be provided on the same surface of the housing as the display unit. In addition, the housing may be configured to have external connection terminals (earphone terminals, USB terminals, terminals that can be connected to various cables such as AC adapters and USB cables, etc.), a recording medium insertion section, etc. on the back or side of the housing. . Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

Further, the electronic book 2700 may be configured to transmit and receive information wirelessly. wirelessly,
It is also possible to purchase and download desired book data from an electronic book server.

(Embodiment 8)
The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). Examples of electronic devices include television devices (also called televisions or television receivers), monitors for computers, cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (mobile phones, mobile phones (also referred to as a device), portable game machines, personal digital assistants, sound reproduction devices, and large game machines such as pachinko machines.

FIG. 26A shows an example of a television device 9600. FIG. Television device 96
00, a display portion 9603 is incorporated in a housing 9601 . Images can be displayed on the display portion 9603 . Further, here, the housing 9601 is supported by a stand 9605.
shows a configuration that supports

The television set 9600 can be operated using operation switches provided in the housing 9601 or a separate remote controller 9610 . Channels and volume can be operated with operation keys 9609 included in the remote controller 9610, and images displayed on the display portion 9603 can be operated. Further, the remote controller 9610 may be provided with a display portion 9607 for displaying information output from the remote controller 9610 .

Note that the television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via a modem, it can be unidirectional (from the sender to the receiver) or bidirectional (from the sender to the receiver). It is also possible to communicate information between recipients, or between recipients, etc.).

FIG. 26B shows an example of a digital photo frame 9700. FIG. For example, a digital photo frame 9700 has a display portion 9703 incorporated in a housing 9701 . The display portion 9703 can display various images. For example, by displaying image data captured by a digital camera or the like, the display portion 9703 can function like a normal photo frame.

The digital photo frame 9700 includes an operation unit, external connection terminals (USB terminal, US
terminal connectable to various cables such as B cable), a recording medium insertion part, and the like. These structures may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory in which image data captured by a digital camera is stored can be inserted into a recording medium insertion portion of a digital photo frame, image data can be captured, and the captured image data can be displayed on the display portion 9703 .

Further, the digital photo frame 9700 may be configured to transmit and receive information wirelessly. Desired image data may be captured wirelessly and displayed.

FIG. 27A shows a portable game machine, which includes two housings, a housing 9881 and a housing 9891, which are connected by a connecting portion 9893 so as to be openable and closable. A display portion 9882 is incorporated in the housing 9881 and a display portion 9883 is incorporated in the housing 9891 . In addition, the portable game machine shown in FIG.
6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9
888 (force, displacement, position, velocity, acceleration, angular velocity, number of revolutions, distance, light, liquid, magnetism, temperature,
including functions to measure chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared rays), microphone 9889), etc. Of course, the configuration of the portable game machine is not limited to the one described above, and may be configured to include at least the semiconductor device disclosed in this specification, and may be configured to include other accessory equipment as appropriate. The portable game machine shown in FIG. 27A has a function of reading out a program or data recorded in a recording medium and displaying it on a display unit, and performing wireless communication with other portable game machines to share information. have a function. Note that the functions of the portable game machine shown in FIG. 27A are not limited to this, and can have various functions.

FIG. 27B shows an example of a slot machine 9900, which is a large game machine. A slot machine 9900 has a display unit 9903 incorporated in a housing 9901 . In addition, the slot machine 9900 also includes operating means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Of course, the configuration of the slot machine 9900 is not limited to the one described above, and may be configured to include at least the semiconductor device disclosed in this specification, and may be configured to include other accessory equipment as appropriate.

FIG. 28A is a perspective view showing an example of a portable computer.

The portable computer in FIG. 28A has an upper housing 9301 having a display portion 9303 and a lower housing 9302 having a keyboard 9304 when a hinge unit connecting the upper housing 9301 and the lower housing 9302 is closed. can be placed on top of each other, it is convenient to carry, and when the user performs keyboard input, the hinge unit can be opened and the input operation can be performed while looking at the display portion 9303 .

In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing input operations. Further, when the display portion 9303 is a touch input panel, an input operation can be performed by touching part of the display portion. In addition, the lower housing 9302 has an arithmetic function unit such as a CPU and a hard disk. In addition, the lower housing 9302 can be used for other devices such as U
It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted.

The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301 .
07, and a wide display screen can be realized. In addition, the stowable display unit 93
The orientation of the 07 screen can be adjusted by the user. Further, when a touch input panel is used as the retractable display portion 9307, an input operation can be performed by touching part of the retractable display portion.

As the display portion 9303 or the retractable display portion 9307, an image display device such as a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element is used.

In addition, the portable computer in FIG. 28A can receive television broadcast and display an image on a display portion or a display portion by including a receiver or the like. Also, the upper housing 93
01 and the lower housing 9302 is closed, the display unit 930
By sliding 7 to expose the entire screen and adjusting the screen angle, the user can watch TV broadcasts. In this case, the hinge unit is opened and the display portion 9303 is not displayed, and only the circuit for displaying the television broadcast is activated, so power consumption can be minimized and the battery capacity is limited. It is useful in portable computers that are

Also, FIG. 28B is a perspective view showing an example of a mobile phone that can be worn on the user's arm like a wristwatch.

This mobile phone includes a main body having at least a communication device having a telephone function and a battery, a band portion for wearing the main body on the arm, and an adjusting portion 92 for adjusting the fixing state of the band portion to the arm.
05, a display unit 9201, a speaker 9207, and a microphone 9208.

In addition, the main body has an operation switch 9203, and in addition to a power input switch, a display switching switch, and an imaging start instruction switch, for example, when a button is pressed, a program for the Internet is started.

An input operation of this mobile phone is performed by touching the display portion 9201 with a finger or an input pen, operating an operation switch 9203 , or inputting voice to a microphone 9208 . Note that FIG. 28B illustrates display buttons 9202 displayed in the display portion 9201, and input can be performed by touching with a finger or the like.

The main body also has a camera section 9206 having an imaging means for converting a subject image formed through a photographing lens into an electronic image signal. Note that the camera section may not be provided.

Further, the mobile phone shown in FIG. 28B has a configuration including a television broadcast receiver and the like, can receive television broadcast and display an image on the display portion 9201, and further includes a storage device such as a memory. , the television broadcast can be recorded in the memory. Also, FIG.
may have a function of collecting location information such as GPS.

For the display portion 9201, an image display device such as a liquid crystal display panel, a light-emitting display panel such as an organic light-emitting element or an inorganic light-emitting element is used. Since the mobile phone shown in FIG. 28B is small and lightweight, battery capacity is limited, and a panel that can be driven with low power consumption is preferably used as the display device for the display portion 9201 .

Note that FIG. 28B illustrates the type of electronic device that is worn on the "arm", but the electronic device is not particularly limited as long as it has a shape that allows it to be carried.

In this example, a thin film transistor is manufactured using the manufacturing method described in Embodiment Mode 1.
Results of evaluation of off-state current of thin film transistor characteristics in an environment of 5° C. to 150° C. are shown.

In this example, a plurality of thin film transistors each having a channel length L of 3 μm were manufactured over a glass substrate, and the off-state current of thin film transistor characteristics was evaluated under an environment of −25° C. to 150° C. inclusive. Note that the channel width W was set to 20 μm. First, a method for manufacturing a thin film transistor is described.

First, a silicon oxynitride film having a thickness of 100 nm is formed as a base film on a glass substrate by a CVD method, and a gate electrode layer having a thickness of 100 nm is formed on the silicon oxynitride film by a sputtering method.
of tungsten film was formed. Here, the tungsten film was selectively etched to form a gate electrode layer.

Next, a 100-nm-thick silicon oxynitride film was formed as a gate insulating layer over the gate electrode layer by a CVD method.

Next, an In—Ga—Zn—O-based oxide semiconductor target (In ₂ O ₃
:Ga ₂ O ₃ :ZnO=1:1:1), and the distance between the substrate and the target is 80 m.
m, pressure 0.4 Pa, direct current (DC) power supply 5 kW, argon and oxygen (argon: oxygen = 5
A film was formed at 200° C. in an atmosphere of 0 sccm:50 sccm to form an oxide semiconductor layer with a thickness of 30 nm. Here, the oxide semiconductor layer was selectively etched to form an island-shaped oxide semiconductor layer.

Next, the oxide semiconductor layer was subjected to first heat treatment at 650° C. for 6 minutes in a nitrogen atmosphere, and then second heat treatment at 450° C. for 1 hour in an air atmosphere.

Next, a titanium film (having a thickness of 100 mm) was formed as a source electrode layer and a drain electrode layer over the oxide semiconductor layer.
nm), an aluminum film (thickness: 300 nm), and a titanium film (thickness: 100 nm) were formed at 100° C. by a sputtering method. Here, the source electrode layer and the drain electrode layer were selectively etched so that the channel length L of the thin film transistor was 3 μm and the channel width W was 20 μm.

Next, an insulating layer having a thickness of 300 nm was formed by a sputtering method so as to be in contact with the oxide semiconductor layer.
A silicon oxide film having a thickness of m was formed at 200°C. Here, the silicon oxide film which is a protective layer was selectively etched to form openings over the gate electrode layer, the source electrode layer, and the drain electrode layer. After that, a third heat treatment was performed at 250° C. for 1 hour in a nitrogen atmosphere.

Through the above steps, a plurality of thin film transistors having a channel length L of 3 μm and a channel width W of 20 μm were manufactured on the glass substrate.

Next, the off current of the thin film transistor was measured. The off current characteristics were measured at a voltage between the source and drain (hereinafter referred to as drain voltage or Vd) of 10 V and a voltage between the source and gate (hereinafter referred to as gate voltage or Vg) of −10 V. . Figure 4 (
B) shows the off current of the thin film transistor at each substrate temperature (operating temperature) when the substrate temperature is changed to −25° C., 0° C., 25° C., 50° C., 100° C., and 150° C. during measurement.
The measurement temperature on the horizontal axis indicates the substrate temperature (operating temperature) at the time of measuring the off current of the thin film transistor on a linear scale, and the vertical axis indicates the off current (Ioff) at each substrate temperature on a log scale.

The thin film transistor manufactured in this example was subjected to the following conditions in an environment of -25°C or higher and 150°C or lower.
It was confirmed that the value of off current was 1×10 ⁻¹² A or less.

10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 28 Transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 transistor 38 transistor 39 transistor 40 transistor 41 transistor 42 transistor 43 transistor 51 power line 52 power line 53 power line 61 period 62 period 100 substrate 101 gate electrode layer 102 gate insulating layer 103 oxide semiconductor layer 107 insulating layer 110 channel protective layer 150 thin film transistor 160 thin film transistor 170 thin film transistor 180 thin film transistor 201 spectrum 202 spectrum 203 spectrum 301 spectrum 302 spectrum 303 spectrum 311 spectrum 312 spectrum 313 spectrum 321 spectrum 322 spectrum 323 spectrum 400 glass substrate 401 oxynitride insulating layer 402 In—Ga—Zn—O-based oxide semiconductor Layer 403 Analysis direction 411 Oxygen ion intensity profile 412 Hydrogen concentration profile 413 Hydrogen concentration profile 451 Spectrum 452 Spectrum 453 Spectrum 461 Spectrum 462 Spectrum 463 Spectrum 581 Thin film transistor 583 Insulating film 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particle 594 Cavity 595 Filling Material 600 Substrate 601 Counter substrate 602 Gate wiring 603 Gate wiring 604 Capacitor wiring 605 Capacitor wiring 606 Gate insulating film 616 Wiring 617 Capacitor wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact hole 624 Pixel electrode 625 Slit 626 Pixel electrode 627 Contact Hall 628 TFT
629 TFT
630 storage capacitor section 631 storage capacitor section 636 colored film 637 planarization film 640 counter electrode 641 slit 644 protrusion 646 alignment film 648 alignment film 650 in nitrogen atmosphere 650 liquid crystal layer 651 liquid crystal element 652 liquid crystal element 690 capacitance wiring 701 gate electrode layer 702 gate Insulating layer 703 Semiconductor layer 704 Source electrode layer 705 Drain electrode layer 801 Glass substrate 802 Gate electrode layer 803 Gate insulating layer 804 Oxide semiconductor layer 805 Source electrode layer 806 Drain electrode layer 105a Source electrode layer 105b Drain electrode layer 2600 TFT substrate 2601 Opposite Substrate 2602 Sealing material 2603 Pixel portion 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit portion 2609 Flexible wiring substrate 2610 Cold cathode tube 2611 Reflector 2612 Circuit substrate 2613 Diffusion plate 2700 Electronic book 2701 Housing 2703 Housing 2705 Display portion 2707 Display portion 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel portion 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 anisotropic conductive film 4020 insulating layer 4020 insulating layer (insulating layer 4021 insulating layer 4030 pixel electrode layer 4031 counter electrode layer 4032 insulating layer 4040 conductive layer 4501 substrate 4502 pixel portion 4505 sealing material 4506 substrate 4507 filler 4509 thin film transistor 4510 thin film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Partition wall 4540 Conductive layer 4541 Insulating layer 4544 Insulating layer 5300 On substrate 5300 Substrate 5301 Pixel portion 5302 Scan line driver circuit 5303 Scan line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit portion 5602 Switching circuit 5603 Thin film transistor 5604 Wiring 5605 Wiring 590a Black region 590b White region 6400 Pixel 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emission element 6405 signal line 6406 scanning line 6407 power supply line 6408 common electrode 7001 TFT
7002 light emitting element 7003 cathode 7004 EL layer 7005 anode 7009 partition 7011 TFT
7012 light-emitting element 7013 cathode 7014 EL layer 7015 anode 7016 shielding film 7017 conductive film 7019 partition wall 7021 TFT
7022 light emitting element 7023 cathode 7024 EL layer 7025 anode 7026 anode 7027 conductive film 7029 partition 7031 oxide insulating layer 7033 color filter layer 7034 overcoat layer 7035 insulating layer 7041 oxide insulating layer 7043 color filter layer 7044 overcoat layer 7045 insulating layer 704a Drain electrode layer 704b Source electrode layer 7051 Oxide insulating layer 7052 Insulating layer 7053 Flattening insulating layer 7055 Insulating layer 9201 Display portion 9202 Display button 9203 Operation switch 9205 Control portion 9206 Camera portion 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display unit 9304 Keyboard 9305 External connection port 9306 Pointing device 9307 Display unit 9600 Television device 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation keys 9610 Remote controller 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Housing 9882 display unit 9883 display unit 9884 speaker unit 9885 input means (operation keys 9886 recording medium insertion unit 9887 connection terminal 9888 sensor 9889 microphone 9890 LED lamp 9891 housing 9893 connecting unit 9900 slot machine 9901 housing 9903 display unit 4503a signal line driving circuit 4504a Scanning line drive circuit 4518a FPC

Claims (2)

a transistor including a first conductive layer, an oxide semiconductor layer, a second conductive layer, and a third conductive layer; a first insulating layer above the oxide semiconductor layer; a fourth conductive layer over an insulating layer, a layer containing an organic compound over the fourth conductive layer, and a fifth conductive layer over the layer containing an organic compound;
The oxide semiconductor layer has a region overlapping with the first conductive layer,
the oxide semiconductor layer has a region in contact with the second conductive layer and the third conductive layer;
The first insulating layer has an opening,
electrically connecting the fourth conductive layer and the second conductive layer or the third conductive layer through the opening;
The oxide semiconductor layer has microcrystals,
the transistor has a channel length of 1.5 μm or more and 100 μm or less;
The display device, wherein the transistor has an off-state current value of 1×10 ⁻¹² A or less per 1 μm of channel width in a temperature range of −25° C. or more and 150° C. or less. a transistor including a first conductive layer, an oxide semiconductor layer, a second conductive layer, and a third conductive layer; a first insulating layer above the oxide semiconductor layer; a fourth conductive layer over an insulating layer, a layer containing an organic compound over the fourth conductive layer, and a fifth conductive layer over the layer containing an organic compound;
The oxide semiconductor layer has a region overlapping with the first conductive layer,
the oxide semiconductor layer has a region in contact with the second conductive layer and the third conductive layer;
The first insulating layer has an opening,
electrically connecting the fourth conductive layer and the second conductive layer or the third conductive layer through the opening;
The oxide semiconductor layer has microcrystals,
the transistor has a channel length of 3 μm or more and 100 μm or less;
The display device, wherein the transistor has an off-state current value of 1×10 ⁻¹² A or less per 1 μm of channel width in a temperature range of −25° C. or more and 150° C. or less.

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