JP6902062B2 - 適応層を形成するのに用いる装置及びそれを用いた方法 - Google Patents
適応層を形成するのに用いる装置及びそれを用いた方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 43
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
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- G—PHYSICS
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Shaping Of Tube Ends By Bending Or Straightening (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
ここで、
Δx=平面曲げに起因するX方向におけるディストーション
Δy=平面曲げに起因するY方向におけるディストーション
z=曲げに起因する、平板の形状の変化z(x,y)
t=平板の有効厚さ
上述した式は、状況に適する小さな変形を備える薄い平板に対して導き出される。
Claims (10)
- 論理素子を有する装置であって、
前記論理素子は、
第1基板上の第1パターン層と第2パターン層との間のローオーバーレイ誤差を取得し、前記第1パターン層は、第1基板チャックを用いてパターン化され、前記第2パターン層は、第2基板チャックを用いてパターン化されており、
前記第1基板チャック及び前記第2基板チャックに関連する平坦度プロファイルの差を決定し、前記平坦度プロファイルの差は、少なくとも部分的に、前記第1パターン層と前記第2パターン層との間の前記ローオーバーレイ誤差に基づいており、
前記第1基板チャック及び前記第2基板チャックに関連する前記平坦度プロファイルの差に応じて、第2基板上であって、成形可能な材料の下に形成すべき、異なる基板チャックの間の平坦度プロファイルの差に対抗するための適応層の高さに関連する情報を生成し、
前記第1パターン層を形成するのに用いた第1テンプレート、前記第2パターン層を形成するのに用いた第2テンプレート又は前記第1及び第2テンプレートにおける前記平坦度プロファイルの前記差に関連するディストーションに対応するディストーション寄与を除去することを特徴とする装置。 - 前記論理素子は、更に、前記第1パターン層と前記第2パターン層との間の位置ずれであるアライメント寄与を除去することを特徴とする請求項1に記載の装置。
- 前記論理素子は、前記ディストーション寄与を除去した後、更に、前記第1及び第2パターン層に関連する平均場シグネチャを除去し、前記平均場シグネチャは、全てのフィールドにわたって平均化された反復誤差に対応することを特徴とする請求項1に記載の装置。
- 前記適応層に対応する情報は、前記適応層を形成するための液体ドロップレットパターンを含むことを特徴とする請求項1に記載の装置。
- 論理素子を有する装置であって、
前記論理素子は、
第1基板上の第1パターン層と第2パターン層との間のローオーバーレイ誤差を取得し、前記第1パターン層は、第1基板チャックを用いてパターン化され、前記第2パターン層は、第2基板チャックを用いてパターン化されており、
前記第1基板チャック及び前記第2基板チャックに関連する平坦度プロファイルの差に少なくとも部分的に基づいて、第2基板上であって、成形可能な材料の下に形成すべき、異なる基板チャックの間の平坦度プロファイルの差に対抗するための適応層の高さに関連する情報を生成し、
前記第1及び第2パターン層の間の位置ずれに対応するアライメント寄与を除去し、
前記第1パターン層を形成するのに用いた第1テンプレート、前記第2パターン層を形成するのに用いた第2テンプレート又は前記第1及び第2テンプレートにおける前記平坦度プロファイルの前記差に関連するディストーションに対応するディストーション寄与を除去することを特徴とする装置。 - 前記論理素子は、前記ディストーション寄与を除去した後、更に、前記第1及び第2パターン層に関連する平均場シグネチャを除去し、前記平均場シグネチャは、全てのフィールドにわたって平均化された反復誤差に対応することを特徴とする請求項5に記載の装置。
- 方法であって、
第1基板チャック及び第2基板チャックに関連する平坦度プロファイルの差を決定することと、
第1基板上であって、成形可能な材料の下に、異なる基板チャックの間の平坦度プロファイルの差に対抗するための適応層を形成することであって、前記適応層は、前記第1基板チャックの平坦度を基準としたときの、前記第2基板チャックの平坦度の差に対抗するように、当該平坦度の差をキャンセルする厚さプロファイルを有することと、を有し、
前記平坦度プロファイルの差を決定することは、
第2基板上の第1パターン層と第2パターン層との間のオーバーレイ誤差を計測することであって、前記第1パターン層は、第1基板チャックを用いてパターン化され、前記第2パターン層は、第2基板チャックを用いてパターン化されていることと、
前記第1及び第2パターン層の間の位置ずれであるアライメント寄与を除去することと、
前記第1パターン層を形成するのに用いた第1テンプレート、前記第2パターン層を形成するのに用いた第2テンプレート又は前記第1及び第2テンプレートに関連するディストーションに対応するディストーション寄与を除去することと、
前記第1及び第2基板チャックの平坦度プロファイルの差に起因するディストーションを推定することと、
を有することを特徴とする方法。 - 前記平坦度プロファイルの差を決定することは、前記ディストーション寄与を除去した後、更に、前記第1及び第2パターン層に関連する平均場シグネチャを除去することを有し、前記平均場シグネチャは、全てのフィールドにわたって平均化された反復誤差に対応することを特徴とする請求項7に記載の方法。
- 前記平坦度プロファイルの差を決定することは、更に、前記第1パターン層を形成するのに用いた第1テンプレート、前記第2パターン層を形成するのに用いた第2テンプレート又は前記第1及び第2テンプレートに関連する前記平均場シグネチャを決定することを有することを特徴とする請求項8に記載の方法。
- 前記適応層上に前記成形可能な材料を形成すること、
を更に有することを特徴とする請求項7に記載の方法。
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US15/938,958 US10553501B2 (en) | 2018-03-28 | 2018-03-28 | Apparatus for use in forming an adaptive layer and a method of using the same |
US15/938,958 | 2018-03-28 |
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US11567401B2 (en) * | 2019-12-20 | 2023-01-31 | Canon Kabushiki Kaisha | Nanofabrication method with correction of distortion within an imprint system |
US11262652B2 (en) * | 2020-06-25 | 2022-03-01 | Canon Kabushiki Kaisha | Nanofabrication method with correction of distortion within an imprint system |
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JP3251362B2 (ja) * | 1993-01-11 | 2002-01-28 | 三菱電機株式会社 | 露光装置及び露光方法 |
US6890795B1 (en) * | 2003-12-30 | 2005-05-10 | Agency For Science, Technology And Research | Wafer level super stretch solder |
US8850980B2 (en) * | 2006-04-03 | 2014-10-07 | Canon Nanotechnologies, Inc. | Tessellated patterns in imprint lithography |
US8175831B2 (en) * | 2007-04-23 | 2012-05-08 | Kla-Tencor Corp. | Methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers |
JP5349588B2 (ja) * | 2008-06-09 | 2013-11-20 | ボード・オブ・リージエンツ,ザ・ユニバーシテイ・オブ・テキサス・システム | 適応ナノトポグラフィ・スカルプティング |
JP6243898B2 (ja) * | 2012-04-19 | 2017-12-06 | インテヴァック インコーポレイテッド | 太陽電池製造のための2重マスク装置 |
US8956789B2 (en) * | 2013-03-15 | 2015-02-17 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits including multi-patterning of masks for extreme ultraviolet lithography |
MY175436A (en) | 2013-08-19 | 2020-06-26 | Univ Texas | Programmable deposition of thin films of a user-defined profile with nanometer scale accuracy |
US10509329B2 (en) * | 2014-09-03 | 2019-12-17 | Kla-Tencor Corporation | Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control |
US10067898B2 (en) * | 2015-02-25 | 2018-09-04 | Qualcomm Incorporated | Protocol adaptation layer data flow control for universal serial bus |
CN108885414B (zh) * | 2016-02-18 | 2021-07-06 | Asml荷兰有限公司 | 光刻装置、器件制造方法以及相关的数据处理装置和计算机程序产品 |
US9993962B2 (en) * | 2016-05-23 | 2018-06-12 | Canon Kabushiki Kaisha | Method of imprinting to correct for a distortion within an imprint system |
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TWI724383B (zh) | 2021-04-11 |
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US10553501B2 (en) | 2020-02-04 |
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CN110320741B (zh) | 2024-04-26 |
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