JP6897890B2 - 樹脂多層基板、および樹脂多層基板の製造方法 - Google Patents
樹脂多層基板、および樹脂多層基板の製造方法 Download PDFInfo
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- JP6897890B2 JP6897890B2 JP2020559300A JP2020559300A JP6897890B2 JP 6897890 B2 JP6897890 B2 JP 6897890B2 JP 2020559300 A JP2020559300 A JP 2020559300A JP 2020559300 A JP2020559300 A JP 2020559300A JP 6897890 B2 JP6897890 B2 JP 6897890B2
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- resin
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- H—ELECTRICITY
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/091—Locally and permanently deformed areas including dielectric material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0235—Laminating followed by cutting or slicing perpendicular to plane of the laminate; Embedding wires in an object and cutting or slicing the object perpendicular to direction of the wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0014—Shaping of the substrate, e.g. by moulding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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Description
第1樹脂層および第2樹脂層を含んだ複数の樹脂層を積層してなる積層体と、
前記第1樹脂層に形成されるビア導体と、
少なくとも一部が前記第2樹脂層に形成され、且つ、前記ビア導体に接合される接合部と、
前記積層体に形成され、前記接合部を介して前記ビア導体に接続される導体と、
を備え、
前記接合部は前記ビア導体よりも脆く、
前記第2樹脂層の線膨張係数は、前記ビア導体の線膨張係数および前記接合部の線膨張係数よりも大きく、前記第1樹脂層の線膨張係数よりも小さいことを特徴とする。
第1樹脂層に、前記第1樹脂層よりも線膨張係数が小さい第2樹脂層を貼り付ける、貼り合せ工程と、
前記貼り合わせ工程の後、貼り合わせた前記第1樹脂層および前記第2樹脂層を貫通する貫通孔を設け、前記貫通孔のうち少なくとも前記第1樹脂層側に、金属材料を充填してビア導体を形成する、ビア導体形成工程と、
前記ビア導体形成工程の後、前記ビア導体よりも脆い接合部を、前記ビア導体に接するように、前記貫通孔のうち少なくとも前記第2樹脂層側に配設する、接合部形成工程と、
前記接合部形成工程の後、他の樹脂層に形成される導体と前記接合部とが当接するように、貼り合わせた前記第1樹脂層および前記第2樹脂層を含む複数の樹脂層を積層し、加熱プレスすることにより積層体を形成し、且つ、前記接合部を介して前記ビア導体と前記導体とを接合する、積層体形成工程と、
を備えることを特徴とする。
図1は第1の実施形態に係る樹脂多層基板101の外観斜視図である。図2は、樹脂多層基板101の分解平面図である。図3(A)は図1におけるA−A断面図であり、図3(B)は図1におけるB−B断面図である。
S:くぼみの表面積(mm2)
ビッカース硬さ(HV)は、例えばマイクロビッカース硬さ試験(JIS Z 2244)で測定される。
上述したように、接合部は有機物を含むため、接合部の炭素含有率は高い。そのため、例えば、図4(A)に示す最小値(MP)から炭素含有率が上昇し始める点a1から、最大値(PP)に達する点a2までのZ軸方向の距離(L=a2−a1)の中間の位置(BP1)を、ビア導体と接合部との界面と定める(BP1=a1+(a2−a1)/2)。
上述したように、接合部の単位平断面積当たりの空隙率(PR1)は、ビア導体の単位平断面積当たりの空隙率(PR2)よりも高い(PR1>PR2)。そのため、例えば、図4(B)に示すように、単位平断面積当たりの空隙率の最大値を100%とし、+Z方向に移動していって単位平断面積当たりの空隙率が上記最大値の5%を超えた位置(BP2)を、ビア導体と接合部との界面と定める。
第2の実施形態では、第1の実施形態とはビア導体の構成が異なる樹脂多層基板の例を示す。
第3の実施形態では、第1樹脂層の厚みと、第2樹脂層の厚みとが異なる樹脂多層基板の例を示す。
以上に示した各実施形態では、樹脂多層基板が、二つの回路基板同士を接続するケーブルである例を示したが、本発明の樹脂多層基板はこれに限定されるものではない。本発明の樹脂多層基板は、回路基板に面実装される電子部品でもよく、二つの部材間を接続するケーブル、または回路基板と他の部品との間を接続するケーブルでもよい。また、樹脂多層基板の接続部には必要に応じてコネクタが設けられていてもよい。
CN1…第1接続部
CN2…第2接続部
SL…線路部
EP1,EP2,EP3,EP4,EG1,EG2…外部電極
OP1,OP2,OP10,OP20…開口
P1,P2…実装電極
PG1,PG2…グランド電極
S1…回路基板の第1面
S2…回路基板の第2面
V1,V2,V3,V11,V11A,V12,V12A,V13,V13A…ビア導体
VS1…積層体の第1主面
VS2…積層体の第2主面
1,2…保護層
3…上部金型
4…下部金型
6…導電性接合材
11,11a,12,12a,13,13a…第1樹脂層
21,21a,22,22a,23,23a…第2樹脂層
30,30A,30P…積層体
41…信号導体
51,52,53…グランド導体
61,62,71,71P,72,72P…接合部
81…部品
101,101A,102,103…樹脂多層基板
201,202…回路基板
301…電子機器
Claims (15)
- 第1樹脂層および第2樹脂層を含んだ複数の樹脂層を積層してなる積層体と、
前記第1樹脂層に形成されるビア導体と、
少なくとも一部が前記第2樹脂層に形成され、且つ、前記ビア導体に接合される接合部と、
前記積層体に形成され、前記接合部を介して前記ビア導体に接続される導体と、
を備え、
前記接合部は前記ビア導体よりも脆く、
前記第2樹脂層の線膨張係数は、前記ビア導体の線膨張係数および前記接合部の線膨張係数よりも大きく、前記第1樹脂層の線膨張係数よりも小さい、樹脂多層基板。 - 前記接合部のビッカース硬さは前記ビア導体のビッカース硬さよりも低く、
前記接合部は、前記ビア導体よりも脆い、
請求項1に記載の、樹脂多層基板。 - 前記積層体に形成される平面導体をさらに備え、
前記ビア導体は、面積の小さな一方面と、面積の大きな他方面とを有する錐台形であり、
前記ビア導体は、前記一方面が前記平面導体に接続され、前記他方面が前記接合部に接合され、
前記平面導体は、前記ビア導体と同材料である、
請求項1または請求項2に記載の樹脂多層基板。 - 前記ビア導体の数および前記第2樹脂層の数は、それぞれ複数であり、
複数の前記第2樹脂層のうち、2つの第2樹脂層は隣接し、
複数のビア導体のうち、前記2つの第2樹脂層にそれぞれ形成される2つビア導体は、他方面同士が、前記第2樹脂層のみに接する前記接合部を介して接続される、
請求項3に記載の樹脂多層基板。 - 前記接合部は、前記第1樹脂層には接触しない、
請求項1乃至請求項3のいずれかに記載の樹脂多層基板。 - 前記ビア導体と前記接合部との界面は、前記第2樹脂層内に位置する、
請求項1乃至請求項5のいずれかに記載の樹脂多層基板。 - 前記第1樹脂層の比誘電率は前記第2樹脂層の比誘電率よりも低く、
前記第1樹脂層の厚みは前記第2樹脂層の厚みよりも厚い、
請求項1乃至請求項6のいずれかに記載の樹脂多層基板。 - 前記第1樹脂層はフッ素樹脂を主成分とする層であり、
前記第2樹脂層は液晶ポリマーを主成分とする層である、
請求項7に記載の樹脂多層基板。 - 前記複数の樹脂層は熱可塑性樹脂からなる、
請求項1乃至請求項8のいずれかに記載の樹脂多層基板。 - 前記積層体は曲げ部を有する、
請求項1乃至請求項9のいずれかに記載の樹脂多層基板。 - 第1樹脂層に、前記第1樹脂層よりも線膨張係数が小さい第2樹脂層を貼り付ける、貼り合わせ工程と、
前記貼り合わせ工程の後、貼り合わせた前記第1樹脂層および前記第2樹脂層を貫通する貫通孔を設け、前記貫通孔のうち少なくとも前記第1樹脂層側に、金属材料を充填してビア導体を形成する、ビア導体形成工程と、
前記ビア導体形成工程の後、前記ビア導体よりも脆い接合部を、前記ビア導体に接するように、前記貫通孔のうち少なくとも前記第2樹脂層側に配設する、接合部形成工程と、
前記接合部形成工程の後、他の樹脂層に形成される導体と前記接合部とが当接するように、貼り合わせた前記第1樹脂層および前記第2樹脂層を含む複数の樹脂層を積層し、加熱プレスすることにより積層体を形成し、且つ、前記接合部を介して前記ビア導体と前記導体とを接合する、積層体形成工程と、
を備える、樹脂多層基板の製造方法。 - 前記ビア導体形成工程は、前記貫通孔にめっき膜を形成する工程を含む、
請求項11に記載の樹脂多層基板の製造方法。 - 前記接合部形成工程は、前記ビア導体の表面に導電性ペーストを配設する工程を含み、
前記積層体形成工程は、加熱プレスによって前記導電性ペーストを固化させる工程を含む、
請求項11または請求項12に記載の樹脂多層基板の製造方法。 - 前記接合部形成工程は、前記ビア導体の表面に導電性接合材を配設する工程を含む、
請求項11または請求項12に記載の樹脂多層基板の製造方法。 - 前記積層体形成工程は、熱可塑性樹脂からなる前記複数の樹脂層を積層して加熱プレスする工程を含む、
請求項11乃至請求項14のいずれかに記載の樹脂多層基板の製造方法。
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