JP6841876B2 - プロセッサモジュールのフレキシブル接続 - Google Patents
プロセッサモジュールのフレキシブル接続 Download PDFInfo
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- JP6841876B2 JP6841876B2 JP2019149122A JP2019149122A JP6841876B2 JP 6841876 B2 JP6841876 B2 JP 6841876B2 JP 2019149122 A JP2019149122 A JP 2019149122A JP 2019149122 A JP2019149122 A JP 2019149122A JP 6841876 B2 JP6841876 B2 JP 6841876B2
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- 238000004891 communication Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
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- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000802 evaporation-induced self-assembly Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8038—Associative processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
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- Software Systems (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Multi Processors (AREA)
Description
111〜114,211〜218,311〜318,504…プロセッサ
121〜124,221〜224…マザーボードチップセット
131〜134…周辺コンポーネント相互接続高速アップリンク接続(PCIe接続)
140,240,380…UPIリンク
151〜154,251〜258…メモリモジュール
231,232,237,238…PCIeリンク
361…第1サーバシャーシ
362…第2サーバシャーシ
371…第1固定4方向相互接続
372…第2固定4方向相互接続
385…接続レーン
391〜398…ケーブル接続ポート
500…サーバシステム
502…PSU
503…BMC
505…BIOS
506…ノースブリッジ(NB)ロジック
507…PCIバス
508…サウスブリッジ(SB)ロジック
509…ストレージデバイス
511…メモリ
550〜551…ISAスロット
560…PCIeスロット
570〜571…PCIスロット
Claims (7)
- コンピューティングデバイスであって、
複数のプロセッサと、前記複数のプロセッサの各々に関連する複数のモジュール出力ポートと、を有するプロセッサモジュールを備え、
前記複数のプロセッサの各々は、複数のチップ通信チャネル(CCC)を含み、前記複数のCCCのうち何れかのCCCは、前記複数のプロセッサのうち何れかのプロセッサに関連する前記複数のモジュール出力ポートのうち何れかのモジュール出力ポートに接続されており、前記複数のCCCのうち残りのCCCは、前記複数のプロセッサのうち前記何れかのプロセッサ以外のプロセッサに接続されており、
前記複数のモジュール出力ポートの接続状態を監視し、少なくとも前記接続状態に基づいて、ローカルモード又は協調モードの何れかで動作するように前記プロセッサモジュールを構成するように構成されたコントローラをさらに備え、
前記コントローラは前記複数のモジュール出力ポートのうち非アクティブな少なくとも1つのモジュール出力ポートに対して代替接続パスが利用可能であるかどうかを検出し、代替接続パスが利用可能であることを検出したことに応じて、前記複数のモジュール出力ポートのうち非アクティブな少なくとも1つのモジュール出力ポートを前記代替接続パスに接続し、前記プロセッサモジュールを、前記協調モードで動作するように構成する、ことを特徴とするコンピューティングデバイス。 - 前記複数のCCCの各々は、ポイントツーポイント(PTP)プロセッサ相互接続チャネルを含む、ことを特徴とする請求項1に記載のコンピューティングデバイス。
- 前記複数のCCCのうち残りのCCCは、クロスバー構成で前記複数のプロセッサを接続するように配置されている、ことを特徴とする請求項1に記載のコンピューティングデバイス。
- 前記複数のCCCのうち残りのCCCは、リング構成で前記複数のプロセッサを接続するように配置されている、ことを特徴とする請求項1に記載のコンピューティングデバイス。
- 前記複数のモジュール出力ポートの各々は、ケーブル接続ポートである、ことを特徴とする請求項1に記載のコンピューティングデバイス。
- 前記プロセッサモジュールは、前記接続状態が、前記複数のモジュール出力ポートのうち少なくとも1つのモジュール出力ポートが非アクティブであることを示す場合に、前記ローカルモードで動作するように構成されている、ことを特徴とする請求項1に記載のコンピューティングデバイス。
- 前記プロセッサモジュールは、前記接続状態が、前記複数のモジュール出力ポートの各々がアクティブであることを示す場合に、前記協調モードで動作するように構成されている、ことを特徴とする請求項1に記載のコンピューティングデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/142,719 | 2018-09-26 | ||
US16/142,719 US10803008B2 (en) | 2018-09-26 | 2018-09-26 | Flexible coupling of processor modules |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020053030A JP2020053030A (ja) | 2020-04-02 |
JP6841876B2 true JP6841876B2 (ja) | 2021-03-10 |
Family
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019149122A Active JP6841876B2 (ja) | 2018-09-26 | 2019-08-15 | プロセッサモジュールのフレキシブル接続 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10803008B2 (ja) |
EP (1) | EP3629188A1 (ja) |
JP (1) | JP6841876B2 (ja) |
CN (1) | CN110955629B (ja) |
TW (1) | TWI706258B (ja) |
Family Cites Families (24)
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US20050196124A1 (en) * | 2004-02-12 | 2005-09-08 | International Business Machines Corporation | Automated topology detection in a data processing system |
US7148428B2 (en) * | 2004-09-27 | 2006-12-12 | Intel Corporation | Flexible cable for high-speed interconnect |
US7596653B2 (en) * | 2004-11-08 | 2009-09-29 | Intel Corporation | Technique for broadcasting messages on a point-to-point interconnect |
JP4484757B2 (ja) * | 2004-12-09 | 2010-06-16 | 株式会社日立製作所 | 情報処理装置 |
US7325086B2 (en) * | 2005-12-15 | 2008-01-29 | Via Technologies, Inc. | Method and system for multiple GPU support |
KR100738554B1 (ko) * | 2006-01-26 | 2007-07-11 | 삼성전자주식회사 | 듀얼모드 단말에서의 호 처리 장치 및 방법 |
CN101118522B (zh) * | 2006-08-04 | 2010-08-25 | 欧姆龙株式会社 | 微型计算机装置 |
CN101504449B (zh) * | 2009-03-13 | 2011-07-20 | 江苏省电力公司常州供电公司 | 备自投装置的试验测试仪 |
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TWM412423U (en) * | 2010-08-13 | 2011-09-21 | Micro Star Int Co Ltd | Computer motherboard for reducing power consumption during sleep mode |
US8954808B1 (en) | 2010-11-30 | 2015-02-10 | Symantec Corporation | Systems and methods for performing input/output path failovers |
US9383411B2 (en) * | 2013-06-26 | 2016-07-05 | International Business Machines Corporation | Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers |
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JP6373620B2 (ja) * | 2014-04-01 | 2018-08-15 | 株式会社ソニー・インタラクティブエンタテインメント | ゲーム提供システム |
CN104125172B (zh) * | 2014-07-22 | 2017-05-24 | 福建星网锐捷网络有限公司 | 一种接口模式自动匹配的交换设备 |
US9898607B2 (en) * | 2015-06-02 | 2018-02-20 | Rockwell Automation Technologies, Inc. | Rapid configuration security system for industrial control infrastructure |
US10237169B2 (en) * | 2016-04-01 | 2019-03-19 | Intel Corporation | Technologies for quality of service based throttling in fabric architectures |
US10491701B2 (en) * | 2016-07-14 | 2019-11-26 | Cisco Technology, Inc. | Interconnect method for implementing scale-up servers |
CN106776459B (zh) | 2016-12-14 | 2020-06-26 | 华为技术有限公司 | 信号处理方法、节点控制器芯片与多处理器系统 |
CN206649376U (zh) | 2017-02-10 | 2017-11-17 | 郑州云海信息技术有限公司 | 一种应用在purley平台八路服务器PCH配置结构 |
CN107396586A (zh) | 2017-07-27 | 2017-11-24 | 郑州云海信息技术有限公司 | 一种减少背板层叠的upi互连系统 |
CN107766282B (zh) * | 2017-10-27 | 2021-04-27 | 郑州云海信息技术有限公司 | 一种八路服务器背板与双扣板互联系统的设计方法 |
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2018
- 2018-09-26 US US16/142,719 patent/US10803008B2/en active Active
-
2019
- 2019-01-03 TW TW108100129A patent/TWI706258B/zh active
- 2019-01-21 CN CN201910052374.0A patent/CN110955629B/zh active Active
- 2019-02-27 EP EP19159790.5A patent/EP3629188A1/en not_active Withdrawn
- 2019-08-15 JP JP2019149122A patent/JP6841876B2/ja active Active
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Publication number | Publication date |
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EP3629188A1 (en) | 2020-04-01 |
CN110955629A (zh) | 2020-04-03 |
US20200097441A1 (en) | 2020-03-26 |
TW202013205A (zh) | 2020-04-01 |
JP2020053030A (ja) | 2020-04-02 |
TWI706258B (zh) | 2020-10-01 |
CN110955629B (zh) | 2022-11-08 |
US10803008B2 (en) | 2020-10-13 |
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