JP6818834B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device including a transformer.

For example, in the field of power electronics, transformers having a pair of coils arranged opposite to each other are being developed.
Patent Document 1 discloses a transformer having a pair of inductors. One inductor is rotated 180 ° around the central axis as a rotation axis and is arranged to face the other inductor.

Japanese Unexamined Patent Publication No. 2013-115131

Generally, the withstand voltage countermeasure point of the transformer is an insulating film between a pair of coils. This is because a large voltage is applied between the coils of the transformer to the insulating film, and a thin insulating film cannot withstand the voltage.
On the other hand, a low voltage region (for example, a region in which wiring for a low voltage coil is formed) may be provided in a region separated from the transformer in the in-plane direction (lateral direction) of the insulating film. Normally, the distance between the low voltage region and the transformer is set to be several tens of times or more the distance between the coils of the transformer. Therefore, little consideration has been given to the occurrence of dielectric breakdown in the low voltage region-transition region.

However, as a result of diligent studies by the inventors of this application, when a surge fracture test is performed between the coils of a transformer, the insulating film may fracture along the lateral direction even if there is no fracture between the coils. I understand.

The semiconductor device according to the embodiment of the present invention includes a first die pad, a second die pad separated from the first die pad by a predetermined distance in the first direction in a plan view, and a first semiconductor supported by the first die pad. A pair of first sides supported by the first die pad so as to be arranged between the chip, the second semiconductor chip supported by the second die pad, and the first semiconductor chip and the second semiconductor chip. And at least one pair of coils formed in a quadrangular shape having a pair of second sides and composed of a plurality of laminated insulating layers and arranged at intervals above and below the insulating layer laminated structure. The transformer chip , the first wire connecting the first semiconductor chip and the transformer chip , the second wire connecting the transformer chip and the second semiconductor chip, and the pair of first wires of the transformer chip . A plurality of first pads arranged along one of the sides and a second pad arranged in an area surrounded by the pair of coils, said coil having an inner coil end and an outer coil end. The first pad is a first group including an inner coil end pad connected to the inner coil end via a first lead wire extending across the coil in plan view and the coil in plan view. It is divided into a second group including an outer coil end pad connected to the outer coil end via a second lead-out wiring formed in the outer region of the first group and each of the first group and the second group. has at least two of said first pad, the distance between the front Symbol first group and said second group is longer than the distance between the first pad in said first group, before Symbol first wire Is connected to one of the plurality of first pads, and at least a part of the first lead-out wiring is arranged below the coil.

FIG. 1 is a schematic plan view of a semiconductor module showing an embodiment of the present invention. FIG. 2 is a diagram showing a connection form of the semiconductor module and the potential of each part. FIG. 3 is a schematic view for explaining the planar structure of the transformer chip. FIG. 4 is a schematic view for explaining the planar structure of the lower coil of the transformer chip. FIG. 5 is a schematic view for explaining the planar structure of the upper coil of the transformer chip. FIG. 6 is a cross-sectional view of the transchip (VI-VI line cross-sectional view of FIG. 3). FIG. 7 is an enlarged view of a main part of the transformer chip of FIG. FIG. 8 is a diagram showing the relationship between the thickness of the interlayer film and the breakdown voltage in a semiconductor chip including a transformer. FIG. 9 shows a modified example of the pattern of the capacitor in the transformer chip. FIG. 10 shows a modified example of the pattern of the capacitor in the transformer chip. FIG. 11 shows a modified example of the pattern of the capacitor in the transformer chip. FIG. 12 shows a modified example of the pattern of the capacitor in the transformer chip. FIG. 13 shows a modified example of the pattern of the capacitor in the transformer chip. FIG. 14 is a diagram for explaining a structure of an electrode plate as an example of an electric field shield portion instead of the capacitor. FIG. 15 shows a modified example of the pattern of the electrode plate. FIG. 16 shows a modified example of the pattern of the electrode plate. FIG. 17 shows a modified example of the connection state of the substrate of the transformer chip. FIG. 18 shows a modified example of the connection state of the substrate of the transformer chip. FIG. 19 shows a modified example of the connection state of the substrate of the transformer chip. FIG. 20 is a schematic plan view of the transchip according to another embodiment 1 of the present invention. FIG. 21 is a schematic plan view of a layer in which a lower coil according to another embodiment 1 of the present invention is arranged. FIG. 22 is a schematic plan view of a layer in which the upper coil is arranged according to another embodiment 1 of the present invention. FIG. 23 is a cross-sectional view that appears when the transchip is cut along the cutting line XXIII-XXIII of FIG. FIG. 24 is an enlarged view of the upper coil and its periphery in FIG. 23. FIG. 25 is a schematic plan view of the transchip according to another second embodiment of the present invention. FIG. 26 is a schematic plan view of a layer in which a lower coil according to another second embodiment of the present invention is arranged. FIG. 27 is a schematic plan view of a layer in which an upper coil is arranged according to another second embodiment of the present invention. FIG. 28 is a cross-sectional view that appears when the transchip is cut along the cutting line XXVIII-XXVIII of FIG. FIG. 29 is an enlarged view of the upper coil and its periphery in FIG. 28. FIG. 30A is a cross-sectional view for explaining a process related to the formation of the same type of interface structure. FIG. 30B is a diagram showing the next step of FIG. 30A. FIG. 30C is a diagram showing the next step of FIG. 30B. FIG. 30D is a diagram showing the next step of FIG. 30C. FIG. 30E is a diagram showing the next step of FIG. 30D. FIG. 30F is a diagram showing the next step of FIG. 30E. FIG. 30G is a diagram showing the next step of FIG. 30F. FIG. 30H is a diagram showing the next step of FIG. 30G. FIG. 31 is a diagram showing a modified example of the same type interface structure. FIG. 32 is a diagram showing a modified example of the same type interface structure. FIG. 33 is a diagram showing a modified example of the same type interface structure. FIG. 34 is a diagram showing a modified example of the same type interface structure.

Hereinafter, embodiments and reference examples of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor module 1 showing an embodiment of the present invention. In FIG. 1, the central portion of the module 1 is seen through to clarify the internal structure of the semiconductor module 1.

The semiconductor module 1 is a module in which a plurality of chips are packaged in one package, and includes a resin package 2, a plurality of leads 3, and a plurality of chips 4.
The resin package 2 is formed in the shape of a square plate using, for example, an epoxy resin.
In this embodiment, the plurality of leads 3 are provided so as to straddle the inside and outside of the resin package 2 via a pair of end faces of the resin package 2 facing each other. As a result, the package type of the semiconductor module 1 is SOP (Small Outline Package). The semiconductor module 1 is not limited to SOP, and various types of packages such as QFP (Quad Flat Package) and SOJ (Small Outline J-lead Package) can be adopted.

The plurality of chips 4 include a controller chip 5 (controller IC) as an example of the low-voltage element of the present invention, a transformer chip 6 as an example of the semiconductor device of the present invention, and an example of the high-voltage element of the present invention. Includes a driver chip 7 (driver IC).
The transformer chip 6 is arranged substantially in the center of the resin package 2, and the controller chip 5 and the driver chip 7 are arranged on one lead 3 side and the opposite lead 3 side with respect to the transformer chip 6, respectively. That is, the controller chip 5 and the driver chip 7 are arranged so as to sandwich the transformer chip 6 between them, and are adjacent to each of the plurality of leads 3.

Each of the chips 5 to 7 is formed in a square (rectangular) plate shape, and in this embodiment, the transformer chip 6 is formed smaller than the controller chip 5 and the driver chip 7 having substantially the same size as each other. .. Further, the controller chip 5 and the transformer chip 6 are arranged on a common first die pad 8, and the driver chip 7 is arranged on a second die pad 9 provided at a distance from the first die pad 8.

A plurality of pads 10 and 11 are formed on the surface of the controller chip 5. The plurality of pads 10 are arranged along the long side of the controller chip 5 near the reed 3 and are connected to the reed 3 by the bonding wire 12. The plurality of pads 11 are arranged along the long side of the controller chip 5 on the opposite side (the side closer to the transformer chip 6) of the reed 3.

A plurality of low-voltage pads 13 and high-voltage pads 14 are formed on the surface of the transformer chip 6. The plurality of low-voltage pads 13 are arranged along the long side of the transformer chip 6 near the controller chip 5, and are connected to the pad 11 of the controller chip 5 by a bonding wire 15. That is, in this embodiment, the pad 11 of the controller chip 5 is connected to the primary side of the transformer chip 6. The plurality of high voltage pads 14 are arranged along the long side of the transformer chip 6 at the center in the width direction of the transformer chip 6.

A plurality of pads 16 and 17 are formed on the surface of the driver chip 7. The plurality of pads 16 are arranged along the long side of the driver chip 7 near the transformer chip 6, and are connected to the high voltage pad 14 of the transformer chip 6 by a bonding wire 18. That is, in this embodiment, the pad 16 of the driver chip 7 is connected to the secondary side of the transformer chip 6. The plurality of pads 17 are arranged along the long side of the driver chip 7 on the opposite side (the side closer to the reed 3) of the transformer chip 6, and are connected to the reed 3 by the bonding wire 19.

The arrangement form of the pads of the chips 5 to 7 shown in FIG. 1 is only an example, and can be appropriately changed according to the package type and the arrangement form of the chips 4.
FIG. 2 is a diagram showing the connection form of the semiconductor module 1 of FIG. 1 and the potential of each part.
As shown in FIG. 2, in the transformer chip 6, in the semiconductor module 1, the lower coil 20 on the primary side (low voltage side) as an example of the low voltage coil of the present invention and the secondary coil 20 as an example of the high voltage coil of the present invention. The upper coil 21 on the side (high voltage side) faces each other with a vertical interval. The lower coil 20 and the upper coil 21 are each formed in a spiral shape.

The low voltage wiring 24 and the low voltage wiring 93 are connected to the inner coil end 22 (inner end of the spiral) and the outer coil end 92 (outer end of the spiral) of the lower coil 20, respectively. The ends of the low voltage wirings 24 and 93 are exposed as the low voltage pads 13.
A high voltage wiring 25 (inner coil end wiring) and a high voltage wiring 95 (outer coil end wiring) are connected to the inner coil end 23 and the outer coil end 94 of the upper coil 21, respectively. The ends of the high voltage wirings 25 and 95 are exposed as high voltage pads 14.

The controller chip 5 is provided with a transistor Tr1 in the middle of the wiring 90 that connects a certain pad 10 and a certain pad 11. Further, a transistor Tr2 is provided in the middle of the wiring 91 that connects the other pad 10 and the other pad 11. The transistors Tr1 and Tr2 are switching elements that conduct and cut off the wiring 90 and 91, respectively. The pads 10 and 11 on the wiring 90 side are connected to the input voltage and the low voltage pad 13 on the outer coil end 92 side through the bonding wires 12 and 15, respectively. The pads 10 and 11 on the wiring 91 side are connected to the ground voltage and the low voltage pad 13 on the inner coil end 22 side through the bonding wires 12 and 15, respectively.

The lower coil 20 of the transformer chip 6 is controlled by controlling the controller chip 5 so that the first applied state (Tr1: ON, Tr2: OFF) and the second applied state (Tr1: OFF, Tr2: ON) are alternately repeated. A periodic pulse voltage is generated in. For example, in FIG. 2, a pulse voltage of 5 V is generated in the lower coil 20 with respect to the reference voltage = 0 V (ground voltage).
In the transformer chip 6, while the DC signal is cut off between the lower coil 20 and the upper coil 21, only the AC signal based on the pulse voltage generated in the lower coil 20 by electromagnetic induction is selectively on the high pressure side (upper coil 21). ) Is transmitted. The transmitted AC signal is boosted according to the transformation ratio between the lower coil 20 and the upper coil 21, and is taken out to the driver chip 7 through the bonding wire 18. For example, in FIG. 2, a pulse voltage of 5 V is taken out to the driver chip 7 as a pulse voltage of 15 V with respect to a reference voltage of 1200 V. The driver chip 7 performs a switching operation of the MOSFET by applying an input pulse voltage of 15 V to a gate electrode (not shown) of a SiC power MOSFET (for example, source-drain voltage = 1200 V).

The specific voltage value shown in FIG. 2 is only an example used to explain the operation of the semiconductor module 1. The reference voltage of the driver chip 7 (HV region) may be a value exceeding 1200V (for example, 3750V or the like).
FIG. 3 is a schematic view for explaining the planar structure of the transformer chip 6 of FIG. FIG. 4 is a schematic view for explaining the planar structure of the layer on which the lower coil 20 of the transformer chip 6 is arranged. FIG. 5 is a schematic view for explaining the planar structure of the layer on which the upper coil 21 of the transformer chip 6 is arranged. FIG. 6 is a cross-sectional view of the transformer chip 6 (VI-VI line cross-sectional view of FIG. 3). FIG. 7 is an enlarged view of the upper coil 21 and its periphery in FIG. In FIG. 6, only the metal parts are hatched for clarity.

Next, the internal structure of the transformer chip 6 will be described more specifically.
As shown in FIG. 6, the transformer chip 6 includes a semiconductor substrate 26 and an insulating layer laminated structure 27 formed on the semiconductor substrate 26. As the semiconductor substrate 26, a Si (silicon) substrate, a SiC (silicon carbide) substrate, or the like can be applied.
The insulating layer laminated structure 27 is composed of a plurality of (12 layers in FIG. 6) insulating layers 28 that are laminated in order from the surface of the semiconductor substrate 26. Each of the plurality of insulating layers 28 has a laminated structure of an etching stopper film 29 of a lower layer and an interlayer insulating film 30 of an upper layer, except for the insulating layer 28 of the lowermost layer which is in contact with the surface of the semiconductor substrate 26. The bottom insulating layer 28 is composed of only the interlayer insulating film 30. As the etching stopper film 29, for example, a SiC film, a SiC film, a SiCN film or the like can be used, and as the interlayer insulating film 30, for example, a SiO ₂ film can be used.

The lower coil 20 and the upper coil 21 are formed in different insulating layers 28 in the insulating layer laminated structure 27, and face each other with the insulating layer 28 of one or more layers interposed therebetween. In this embodiment, the lower coil 20 is formed on the insulating layer 28 of the fourth layer from the semiconductor substrate 26, and the upper coil 21 sandwiches the six insulating layers 28 with the lower coil 20 and is the eleventh layer. It is formed on the insulating layer 28.

As shown in FIGS. 3 to 5, the lower coil 20 and the upper coil 21 are around the inner regions 31 and 32 so that the inner regions 31 and 32 having an elliptical plan view are partitioned in the center, respectively. It is formed in an elliptical annular region surrounding the.
The structure of the lower coil 20 and the upper coil 21 in the region surrounding the inner regions 31 and 32 can be described with reference to the upper coil 21 shown in FIG. That is, as shown in FIG. 7, an elliptical spiral coil groove 33 is formed in the insulating layer 28 in the region surrounding the inner region 32. The coil groove 33 is formed so as to penetrate the interlayer insulating film 30 and the etching stopper film 29 below the interlayer insulating film 30. As a result, the upper end and the lower end of the coil groove 33 are surfaces opened to the etching stopper film 29 of the upper insulating layer 28 and the interlayer insulating film 30 of the lower insulating layer 28, respectively.

A barrier metal 34 is formed on the inner surface (side surface and bottom surface) of the coil groove 33. The barrier metal 34 is formed in a film shape following the side surface and the bottom surface so that a space open upward is formed in the coil groove 33. In this embodiment, the barrier metal 34 is formed by laminating a Ta (tantalum) film, a TaN (tantalum nitride) film, and a Ta film in this order from the side closer to the inner surface of the coil groove 33. Then, by embedding the Cu (copper) wiring material 35 inside the barrier metal 34 in the coil groove 33, the upper coil 21 as an example of the embedded coil made of the barrier metal 34 and the Cu wiring material 35 is formed.

The upper coil 21 is formed so that its upper surface is flush with the upper surface of the insulating layer 28. As a result, the upper coil 21 is in contact with different insulating layers 28 on the side surface, the upper surface, and the lower surface. Specifically, in the insulating layer 28 in which the upper coil 21 is embedded, the etching stopper film 29 and the interlayer insulating film 30 are in contact with the side surface of the upper coil 21, and the insulating layer 28 formed on the upper side of the insulating layer 28. Is, only the etching stopper film 29 of the lower layer is in contact with the upper surface of the upper coil 21. Further, in the lower insulating layer 28, only the upper interlayer insulating film 30 is in contact with the lower surface of the upper coil 21.

Although description is omitted here, the lower coil 20 is also formed by embedding a barrier metal and a Cu wiring material in the coil groove, similarly to the upper coil 21.
As shown in FIGS. 3, 6 and 7, the high voltage pad 14 is formed on the surface of the insulating layer laminated structure 27 (on the interlayer insulating film 30 of the uppermost insulating layer 28). The high voltage pad 14 is arranged in the central high voltage region (HV region) 36 in which the upper coil 21 is arranged in a plan view of the transformer chip 6 viewed from above along the stacking direction of the insulating layer laminated structure 27. There is.

Here, the high voltage region 36 includes a region in the insulating layer 28 in which the upper coil 21 is embedded, in which wiring having the same potential as the upper coil 21 and the upper coil 21 is formed, and a peripheral portion of the formed region. In this embodiment, as shown in FIG. 5, a total of four upper coils 21 are formed in pairs of two at intervals in the longitudinal direction of the transformer chip 6. An inner coil end wiring 37 and an outer coil end wiring 96 are formed between the inner region 32 of the upper coil 21 of each pair and the adjacent upper coils 21, respectively. Thereby, in each pair, one upper coil 21 and the other upper coil 21 are electrically connected to each other by a common outer coil end wiring 96 between them, both of these upper coils 21 and the outer coil between them. The end wiring 96 and the inner coil end wiring 37 in each upper coil 21 all have the same potential. Therefore, in the insulating layer 28, the inner region 32 of each upper coil 21 and the region between the upper coils 21 in each pair are also within the range covered by the electric field from the upper coil 21, the inner coil end wiring 37, or the outer coil end wiring 96. Inside, it is included in the high voltage region 36. The region where the lower coil 21 (low voltage coil) is arranged corresponds to the high voltage region 36 in a plan view, but is separated from the high voltage coil 21 by a plurality of insulating layers 28, and is separated from the upper coil 21. Since it is hardly affected by the electric field, it is not included in the high voltage region 36 referred to in this embodiment.

Then, as shown in FIG. 3, one high voltage pad 14 is provided above the inner region 32 of each upper coil 21 and above the region between the upper coils 21 in each pair, for a total of six. Individually arranged.
For example, as shown in FIGS. 6 and 7, a high voltage pad 14 is connected to an inner coil end wire 37 embedded in the same insulating layer 28 as the upper coil 21 via a via 38. Although not shown, the other high-voltage pads 14 are connected to the outer coil end wiring 96 embedded in the same insulating layer 28 as the upper coil 21 via vias by the same structure. As a result, the AC signal transmitted to the upper coil 21 can be output from the high voltage pad 14 via the inner coil end wiring 37 and via 38, and the outer coil end wiring 96 and via (not shown). .. That is, the inner coil end wiring 37 and the via 38 connected to the inner coil end wiring 37, and the outer coil end wiring 96 and the via connected to the outer coil end wiring 96 are combined to form the high voltage wiring 25 and the high voltage wiring 95 of FIG. 2, respectively.

The inner coil end wiring 37 and the via 38 are formed by embedding the barrier metals 41, 42 and the Cu wiring materials 43, 44 in the wiring grooves 39, 40, respectively, as shown in FIG. 7, similarly to the upper coil 21. (The same applies to the outer coil end wiring 96 and the via connected to it). The same material as the barrier metal 34 described above can be applied to the barrier metals 41 and 42.

On the other hand, the insulating layer laminated structure 27 has a low voltage region 46 (FIGS. 4 and 6) and an outer low voltage region 47 (FIGS. 4 and 6) as a low potential region (LV region) electrically separated from the high voltage region 36. FIGS. 3 to 7) and an intermediate region 48 (FIGS. 3 to 7) are set.
The low voltage region 46 includes a region in the insulating layer 28 in which the lower coil 20 is embedded, in which wiring having the same potential as the lower coil 20 and the lower coil 20 is formed, and a peripheral portion of the formed region. The low voltage region 46 faces the high voltage region 36 with one or more insulating layers 28 interposed therebetween, similar to the relationship between the lower coil 20 and the upper coil 21. In this embodiment, as shown in FIG. 4, the lower coil 20 is formed in pairs of two at a position facing the upper coil 21, that is, in the longitudinal direction of the transformer chip 6, for a total of four. An inner coil end wiring 49 and an outer coil end wiring 97 are formed between the inner region 31 of each pair of lower coils 20 and the adjacent lower coils 20, respectively. Thereby, in each pair, one lower coil 20 and the other lower coil 20 are electrically connected to each other by a common outer coil end wiring 97 between them, both of these lower coils 20 and the outer coil in between. The end wiring 97 and the inner coil end wiring 49 in each lower coil 20 all have the same potential. Therefore, in the insulating layer 28, the inner region 31 of each lower coil 20 and the region between the lower coils 20 in each pair are also within the range covered by the electric field from the lower coil 20, the inner coil end wiring 49, or the outer coil end wiring 97. Inside, it is included in the low voltage region 46. As shown in FIG. 5, the inner coil end wiring 49 is arranged at a position deviated from the inner coil end wiring 37 on the high voltage side in a plan view.

The outer low voltage region 47 is set to surround the high voltage region 36 and the low voltage region 46 as shown in FIGS. 3 to 5, and the intermediate region 48 is set to surround the high voltage region 36 and the low voltage region 46 and the outer low voltage region 46. It is set between the voltage region 47 and the voltage region 47.
As shown in FIGS. 3, 6 and 7, the low voltage pad 13 is formed on the surface of the insulating layer laminated structure 27 (on the interlayer insulating film 30 of the uppermost insulating layer 28) in the outer low voltage region 47. There is. In this embodiment, a total of six low-voltage pads 13 are arranged, one on each side of the six high-voltage pads 14 provided at intervals in the longitudinal direction of the transformer chip 6. Each low-voltage pad 13 is connected to the lower coil 20 by low-voltage wirings 24 and 93 routed in the insulating layer laminated structure 27.

The low-voltage wiring 24 includes a through wiring 51 and a lead-out wiring 52.
The through wiring 51 is formed in a columnar shape that penetrates the insulating layer 28 in which at least the lower coil 20 is formed from each low voltage pad 13 in the outer low voltage region 47 and reaches the insulating layer 28 below the lower coil 20. There is. More specifically, the through wiring 51 is connected to the island-shaped (square) low-voltage layer wirings 53 and 54 embedded in the same insulating layer 28 as the upper coil 21 and the lower coil 20, respectively, and between them. It includes a plurality of vias 55 to be connected, a via 56 for connecting the upper low voltage layer wiring 53 and the low voltage pad 13, and a via 57 for connecting the lower low voltage layer wiring 54 and the lead wiring 52.

The lead-out wiring 52 is formed in a linear shape drawn from the low-voltage region 46 to the outer low-voltage region 47 via an insulating layer 28 below the lower coil 20. More specifically, the lead-out wiring 52 is embedded in the inner coil end wiring 49 described above, the insulating layer 28 below the lower coil 20, and the linear lead-out layer wiring 58 that crosses the lower coil 20 below. It includes a via 59 that connects the lead-out layer wiring 58 and the inner coil end wiring 49. The lead-out layer wiring 58 is connected to the semiconductor substrate 26 via the via 86. As a result, the low voltage wiring 24 is fixed to the substrate voltage (for example, the ground voltage).

The wirings 49, 53, 54, 58 and vias 55 to 57, 59 are formed by embedding a barrier metal and a Cu wiring material in the wiring grooves, respectively, like the upper coil 21. As an example, as shown in FIG. 7, the low voltage layer wiring 53 and the vias 55 and 56 are formed by embedding barrier metals 63 to 65 and Cu wiring materials 66 to 68 in wiring grooves 60 to 62, respectively. .. The same material as the barrier metal 34 described above can be applied to the barrier metals 63 to 65.

Although details are omitted, the low-voltage wiring 93 is also composed of wiring including a through wiring (not shown) and a lead-out wiring 98 (FIGS. 3 to 5) like the low-voltage wiring 24. ..
With the above configuration, a certain low voltage pad 13 is connected to the inner coil end wiring 49 of the lower coil 20 via the through wiring 51 and the lead wiring 52 as shown in FIGS. 3 to 6. Further, as shown in FIGS. 3 to 6, the other low-voltage pad 13 is connected to the outer coil end wiring 96 of the lower coil 20 via the through wiring and the lead-out wiring 98. As a result, the signal input to the low voltage pad 13 can be transmitted to the lower coil 21 via the through wiring 51 and the lead wiring 52.

In the insulating layer laminated structure 27, a shield layer 69 is formed further outside the low voltage wiring 24. The shield layer 69 prevents moisture from entering the device from the outside and cracks on the end face from spreading inside.
As shown in FIGS. 3 to 6, the shield layer 69 is formed in a wall shape along the end surface of the transformer chip 6, and is connected to the semiconductor substrate 26 at the bottom thereof. As a result, the shield layer 69 is fixed to the substrate voltage (for example, the ground voltage). More specifically, as shown in FIG. 6, the shield layer 69 includes shield layer wirings 70 to 72 embedded in the same insulating layer 28 as the upper coil 21, lower coil 20, and lead-out layer wiring 58, respectively. It includes a plurality of vias 73 connecting between them, and vias 74 connecting the lowermost shield layer wiring 72 and the semiconductor substrate 26. The shield layer wirings 70 to 72 and the vias 73 and 74 are formed by embedding a barrier metal and a Cu wiring material in the wiring grooves, respectively, like the upper coil 21.

Further, the protective film 75 and the passivation film 76 are sequentially laminated on the entire surface of the insulating layer laminated structure 27 on the insulating layer laminated structure 27. On the passivation film 76, an elliptical annular coil protective film 77 that selectively covers the region directly above the upper coil 21 is formed. The films 75 to 77 are formed with pad openings 78 and 79 for exposing the low voltage pad 13 and the high voltage pad 14, respectively.

The protective film 75 is made of, for example, SiO ₂ and has a thickness of about 150 nm. The passivation film 76 is made of, for example, SiN and has a thickness of about 1000 nm. The coil protective film 77 is made of polyimide, for example, and has a thickness of about 4000 nm.
Next, the details of each part of the transformer chip 6 will be described below.

As described with reference to FIG. 2, a large potential difference (for example, about 1200 V) is generated between the lower coil 20 and the upper coil 21 of the transformer chip 6. Therefore, the insulating layer 28 arranged between the lower coil 20 and the upper coil 21 must have a thickness capable of achieving a withstand voltage that does not cause dielectric breakdown due to the potential difference.
Therefore, in this embodiment, as shown in FIG. 6, a plurality of layers (for example, 6 layers) are interposed between the coils with an insulating layer 28 having a laminated structure of an etching stopper film 29 of about 300 nm and an interlayer insulating film 30 of about 2100 nm. By setting the total thickness L2 of the insulating layer 28 to 12.0 μm to 16.8 μm, DC insulation in the vertical direction between the lower coil 20 and the upper coil 21 is realized.

However, when the inventors of this application experimented with the relationship between the thickness of the interlayer film and the surge breakdown voltage in a semiconductor chip provided with a transformer, the results shown in FIG. 8 were obtained. In FIG. 8, the interlayer film is a film having the same structure as the insulating layer 28 in this embodiment. According to FIG. 8, as the number of layers of the interlayer film between the coils is increased and the film thickness is increased, for example, the upper coil 21 and the lower voltage are obtained even though the DC insulation in the vertical direction is better realized. It can be seen that lateral destruction such as between the pad 13 (between the coil and the pad) and between the upper coil 21 and the shield layer 26 (between the coil and the shield) is dominant.

Normally, the distance L0 between the upper coil 21 and the outer low voltage region 47 is compared with the total thickness L2 of the insulating layer 28 between the lower coil 20 and the upper coil 21 (in this embodiment, the width of the intermediate region 48). Is larger. For example, the distance L0 is generally 100 μm to 450 μm, and when expressed as a ratio to the above-mentioned thickness L2 (distance L0 / thickness L2), it is 6/1 to 40/1. Therefore, for example, a potential difference equivalent to the potential difference between the lower coil 20 and the upper coil 21 (between the high voltage region 36 and the low voltage region 46) occurs between the high voltage region 36 and the outer low voltage region 47. However, considering only the distances between these regions, in theory, the distance L0> the thickness L2, so dielectric breakdown does not occur. However, as evidenced in FIG. 8, if the interlayer film between the coils becomes thicker, lateral fracture becomes dominant. In FIG. 6, the thickness L2 is shown to be larger than the distance L0, but in reality, the distance L0 >> thickness L2 is related.

In this regard, the inventors of this application can provide a shield made of an electrically floating metal member between the high voltage region 36 and the outer low voltage region 47 to provide a specific portion of the outer low voltage region 47. It was found that the electric field concentration with respect to the electric field can be alleviated to prevent lateral fracture.
Therefore, in this embodiment, as shown in FIGS. 3 and 5, a capacitor 80 surrounding the high voltage region 36 in a plan view is provided in the intermediate region 48. In FIGS. 3 and 5, a plurality of high voltage regions 36 are surrounded by a common capacitor 80, but each high voltage region 36 may be individually surrounded.

The cross-sectional structure of the capacitor 80 is shown in FIGS. 6 and 7. That is, the capacitor 80 is embedded in the insulating layer 28 in which the upper coil 21 is embedded, the insulating layer 28 in which the lower coil 20 is embedded, and the insulating layer 28 between them, and the coil of the insulating layer 28 as a whole is embedded. It is formed in the shape of a wall surrounding the formation area.
Each capacitor 80 is composed of a plurality of electrode plates 87 embedded in each insulating layer 28. The plurality of electrode plates 87 are provided at three or more at equal intervals (five in FIGS. 6 and 7), and each of them is electrically floated. Further, the electrode plates 87 embedded in each insulating layer 28 are arranged vertically in a row. That is, when the insulating layer laminated structure 27 is viewed in cross section, the electrode plates 87 constituting a certain capacitor 80 overlap with the electrode plates 87 above and below the electrode plates 87. As a result, the plurality of electrode plates 87 embedded in the insulating layers 28 that are different from each other form a shield plate having no gap along the stacking direction of the insulating layer laminated structure 27.

Like the upper coil 21, each electrode plate 87 is formed by embedding a barrier metal 82 and a Cu wiring material 83 in the wiring groove 81, as shown in FIG. The same material as the barrier metal 34 described above can be applied to the barrier metal 82.
Further, the lateral distance L1 between the upper coil 21 and the capacitor 80 is larger than the total thickness L2 of the insulating layer 28 between the upper coil 21 and the lower coil 20. For example, the distance L1 is 25 μm to 400 μm. In FIG. 6, the thickness L2 is shown to be larger than the distance L1, but in reality, there is a relationship of distance L1 >> thickness L2.

When a high voltage is applied between the upper coil 21 and the lower coil 20 by the capacitor 80, a low-potential conductive portion (for example, a low voltage pad 13, a low voltage layer wiring 53, etc.) arranged in the outer low voltage region 47, It is possible to alleviate the concentration of the electric field on the via 55, the low voltage layer wiring 54, the shield layer 69, etc.). In particular, in the rectangular low-voltage pad 13 and the low-voltage layer wiring 53 arranged in the same layer as the upper coil 21 (high-voltage coil) and the layer in the vicinity thereof, the electric field is concentrated at the corners thereof and surge failure occurs. It is easy to happen. However, by arranging the capacitor 80, such surge failure can be effectively prevented. Moreover, in this embodiment, since the capacitor 80 surrounds the high voltage region 36, the electric field emitted from the upper coil 21 is relaxed regardless of the direction thereof. As a result, the withstand voltage between the high voltage region 36 and the outer low voltage region 37 can be improved.

Further, since the electrode plate 87 constituting the capacitor 80 is embedded in the same insulating layer 28 as the element constituting the shield layer 69, the capacitor 80 and the shield layer 69 can be formed in the same process.
<Modification example>
(1) Deformed example of the pattern of the capacitor 80 FIGS. 9 to 13 show a modified example of the pattern of the capacitor 80.

In the configuration of FIG. 9, three or more electrode plates 87 constituting each capacitor 80 are provided at non-equal intervals. For example, a plurality of electrode plates 87 are arranged so as to increase the distance from the high voltage region 36.
In the configuration of FIG. 10, the electrode plates 87 embedded in each insulating layer 28 are arranged intermittently along the stacking direction of the insulating layer laminated structure 27. That is, when the insulating layer laminated structure 27 is viewed in cross section, the electrode plates 87 constituting a certain capacitor 80 do not overlap with the upper and lower electrode plates 87. For example, as shown in FIG. 10, the electrode plates 87 constituting a certain capacitor 80 may be arranged in a region of a gap between a plurality of electrode plates 87 forming the capacitors 80 above and below the electrode plates 87.

In the configuration of FIG. 11, the capacitor 80 is selectively embedded in the insulating layer 28 for the upper coil 21 and the insulating layer 28 for the lower coil 20. That is, the capacitor 80 may be embedded only in the insulating layer 28 for the upper coil 21 and the lower coil 20, and may not be embedded in the insulating layer 28 between them.
In the configuration of FIG. 12, the capacitor 80 is selectively formed in the intermediate region 48 between the high voltage region 36 and the region (pad region) in which the low voltage pad 13 is arranged, and is a region opposite to the pad region. Is not formed in. On the other hand, the configuration of FIG. 13 is the opposite, and the capacitor 80 is selectively formed in the region opposite to the pad region and is not formed on the pad region side.
(2) Deformation Example Showing a Structure Alternative to Capacitor 80 FIGS. 14 to 16 are a modification showing a structure alternative to the capacitor 80. Specifically, the case where the electrode plates 87 are independently provided in the same insulating layer 28 so as not to overlap in the lateral direction, and the capacitor structure is not provided in each insulating layer 28 is shown.

In the configuration of FIG. 14, the electrode plates 87 embedded in each insulating layer 28 are arranged vertically in a row. On the other hand, in the configuration of FIG. 15, the electrode plates 87 embedded in each insulating layer 28 are intermittently arranged along the stacking direction of the insulating layer laminated structure 27.
It should be noted that the modification shown in this section shows that the capacitor structure is not formed to the last. Therefore, even if a plurality of electrode plates 87 are provided on the same insulating layer 28, they do not have to overlap in the lateral direction. For example, as shown in FIG. 16, a plurality of electrode plates 87 forming a broken line ellipse 84 surrounding the high voltage region 36 are arranged, and a plurality of electrodes forming the broken line ellipse 84 are arranged in the inner region of the broken line ellipse 84. The electrode plate 87 may be arranged so as to face the region of the gap between the plates 87.
(3) Deformation Example Regarding Connection State of Semiconductor Substrate 26 FIGS. 17 to 19 show a modification regarding the connection state of the semiconductor substrate 26.

In the configuration of FIG. 17, the via 86 of FIG. 6 is omitted, and the low voltage wiring 24 is not fixed to the substrate voltage.
In the configuration of FIG. 18, the via 74 of FIG. 6 is omitted, and the shield layer 69 is not fixed to the substrate voltage.
In the configuration of FIG. 19, both the via 86 and the via 74 of FIG. 6 are omitted, and the low voltage wiring 24 and the shield layer 69 are not fixed to the substrate voltage.

Although one embodiment of the present invention has been described above, the present invention can be modified in various ways within the scope of the matters described in the claims.
For example, in the above embodiment, the case where the high voltage coil is the upper coil 21 and the low voltage coil is the lower coil 20 is shown, but even if the high voltage coil is the lower coil 20 and the low voltage coil is the upper coil 21. Good.

Further, in the above-described embodiment, the conductor (low potential portion) electrically connected to a lower potential than the high voltage coil (upper coil 21) is the upper coil, such as the low voltage wiring 24 and the shield layer 69. Although only the case where the 21 is always formed in the same insulating layer 28 as the embedded insulating layer 28 is taken up, the conductor may not be provided in the same insulating layer 28. For example, the present invention can sufficiently exert the effect of reducing surge fracture in the lateral direction even for conductors formed in several layers above or below the insulating layer 28 in which the upper coil 21 is embedded. ..

In addition, various design changes can be made within the scope of the matters described in the claims.
In addition to the inventions described in the claims, the following features can be extracted from the contents of the above-described embodiment.
The semiconductor device is arranged around the insulating layer, the high-voltage coil and the low-voltage coil arranged at intervals above and below the insulating layer, and the high-voltage region for the high-voltage coil in plan view. It is composed of a low potential portion provided in a low voltage region and connected to a potential lower than that of the high voltage coil, and an electrically floating metal member arranged between the high voltage coil and the low voltage region. Includes an electric potential shield.

Since the electric field shield portion is provided between the high voltage coil and the low voltage region, it is possible to relax the electric field concentration on the low potential portion. Thereby, the withstand voltage between the high voltage coil and the low voltage region can be improved.
In the semiconductor device, the electric field shield portion includes a capacitor composed of a plurality of electrode plates facing each other at lateral intervals. In this case, three or more electrode plates may be provided at equal intervals, or three or more electrode plates may be provided at non-equal intervals.

In the semiconductor device, the low potential portion includes a low voltage wiring connected to the low voltage coil.
In the semiconductor device, the low potential portion includes a low voltage pad exposed on the surface of the insulating layer and connected to the low voltage wiring, and the electric field shield portion includes the high voltage coil and the low voltage pad. It is placed between.

When the low voltage pad has corners, the electric field is concentrated on the corners and surge failure is likely to occur. By arranging the electric field shield portion between the high voltage coil and the low voltage pad, such surge failure can be effectively prevented.
In the semiconductor device, the insulating layer has an insulating film laminated structure including a plurality of insulating films laminated in order, and the high voltage coil and the low voltage coil are embedded in separate insulating films. One or more layers of the insulating film are interposed between the high voltage coil and the low voltage coil, and the electric field shield portion is composed of at least one layer of an electrode plate embedded in the insulating film.

In this case, a plurality of the electrode plates may face the same insulating film at intervals, and the plurality of electrode plates may form a capacitor. Then, three or more electrode plates may be provided at equal intervals, or three or more electrode plates may be provided at non-equal intervals.
Further, the electrode plates may be independently provided in the same insulating film so as not to overlap in the lateral direction.

In the semiconductor device, the electrode plate is embedded in the insulating film for the high voltage coil, the insulating film for the low voltage coil, and the insulating film between them. In this case, the insulating film between the insulating films for the high voltage coil and the low voltage coil may be a plurality of films or a single film. In the case of a plurality of films, the electrode plate may be embedded in all the films, or may be selectively embedded in only a part of the films.

In the semiconductor device, the electrode plates embedded in the insulating films are arranged one above the other.
In the semiconductor device, the electrode plate is selectively embedded in the insulating film for the high voltage coil and the insulating film for the low voltage. That is, the electrode plate is embedded only in the insulating film for the high voltage coil and the low voltage coil, and does not have to be embedded in the insulating film between them.

In the semiconductor device, the low potential portion includes a shield layer embedded in a plurality of the insulating films so as to surround the high voltage region, and the electrode plate is embedded in the same insulating film as the shield layer. ing. In this configuration, the shield layer and the electric field shield portion (electrode plate) can be formed in the same process.
In the semiconductor device, the high-voltage coil is an upper coil arranged relatively close to the surface of the insulating film laminated structure, and the low-voltage coil is a lower coil arranged below the upper coil. The low-potential portion includes a low-voltage wiring that is connected to the lower coil and penetrates the insulating film laminated structure in the laminated direction.

In the semiconductor device, the low potential portion includes a low voltage pad exposed on the surface of the insulating layer laminated structure and connected to the low voltage wiring.
When the low voltage pad has corners, the electric field is concentrated on the corners and surge failure is likely to occur. By arranging the electric field shield portion between the high voltage coil and the low voltage pad, such surge failure can be effectively prevented.

In the semiconductor device, the lateral distance L1 between the high voltage coil and the electric field shield portion is larger than the vertical distance L2 between the high voltage coil and the low voltage coil.
In the semiconductor device, the electric field shield portion surrounds the high voltage coil. As a result, the electric field emitted from the high voltage coil is relaxed regardless of its orientation.
The semiconductor device includes a substrate that supports the insulating layer, and the low voltage coil is connected to the substrate.

The semiconductor module includes the semiconductor device, a low-voltage element electrically connected to the low-voltage coil of the semiconductor device, and a high-voltage element electrically connected to the high-voltage coil of the semiconductor device. It includes a semiconductor device, the low-voltage element, and a resin package that collectively seals the high-voltage element.
Another problem of the present invention is that lateral destruction occurs when a large potential difference (for example, several thousand volts) occurs between the high voltage region 36 and the outer low voltage region 47 (see FIG. 8). It can also be solved by the configuration shown in the first and second embodiments.
(1) Another Embodiment 1 of the present invention
Another embodiment 1 of the present invention is different from the above-described embodiment in that the capacitor 80 is not provided in the intermediate region 48 as shown in FIGS. 20 to 24.

Then, regarding the problem described with reference to FIG. 8, the inventors of this application have found that the cause of the leak current causing lateral fracture is related to the constituent material of the insulating film in contact with the upper coil 21.
Therefore, in another embodiment 1 of the present invention, most of the insulating layer 28 is interlayer-insulated composed of an etching stopper film 29 made of a tensile stress SiN film (Tensile-SiN) and a SiO ₂ film having a compressive stress as an internal stress. Although it is formed by overlapping with the film 30, the insulating layer 28 in which the upper coil 21 is embedded and the insulating layer 28 above the insulating layer 28 are selectively compressed as an etching stopper film 29 having a compressive stress as an internal stress. A stress film is used. Such a compressive stress film preferably has, for example, a compressive stress of 400 MPa to 800 MPa as an internal stress. Specifically, a SiO _x (0 <x <2) film having a larger ratio of Si than SiO ₂ is preferable, and a SiN film (Compressive-SiN) having compressive stress may be used. The SiO _x film can be produced by the same manufacturing method as the SiO ₂ film, except that the flow rate of the raw material gas is adjusted to change the composition ratio of Si. On the other hand, the compressive stress SiN film can be produced by adjusting conditions such as SiH ₄ flow rate and N ₂ flow rate in the manufacturing process of the tensile stress SiN film.

As a result, it is possible to suppress the leakage current from the upper coil 21 to the low voltage wiring 24 and the shield layer 69 along the surface direction (lateral direction) of the insulating layer 28. As a result, even if a large potential difference occurs between the upper coil 21, the low voltage wiring 24, and the shield layer 69, dielectric breakdown due to the potential difference can be prevented.
Moreover, with respect to the plurality of insulating layers 28 excluding the insulating layer 28 in which the compressive stress film is adopted as the etching stopper film 29, the etching stopper film composed of the interlayer insulating film 30 made of SiO ₂ having compressive stress and the tensile stress SiN film. Since 29 and 29 can be arranged alternately, the insulating layer 28 can be laminated while canceling the stress at the lamination interface of the insulating layer laminated structure 27. As a result, in the manufacturing process of the transformer chip 6, it is possible to prevent the semiconductor wafer, which is the base of the semiconductor substrate 26 that supports the insulating layer laminated structure 27, from being significantly warped and deformed.

As the etching stopper film 29 of the insulating layer 28 excluding the insulating layer 28 in which the upper coil 21 is embedded, for example, a SiC film, a SiCN film, or the like may be used.
Although the other embodiment 1 of the present invention has been described above, various design changes can be made in the other embodiment 1 of the present invention.
In addition to the invention described in the claims, the following features can be extracted from the contents of the other embodiment 1 of the present invention.
[Item 1]
An insulating layer laminated structure consisting of a plurality of insulating layers laminated in order,
A high-voltage coil and a low-voltage coil formed in the insulating layers different from each other in the insulating layer laminated structure and facing each other with the insulating layer of one or more layers interposed therebetween
It includes a conductor formed in the lateral outer region of the high voltage region in which the high voltage coil is arranged and electrically connected to a potential lower than that of the high voltage coil.
A semiconductor device in which the insulating layer in contact with the high-voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high-voltage coil.

According to this configuration, since the portion of the insulating layer in contact with the high voltage coil is formed of the compressive stress film, a leak current is generated from the high voltage coil to the conductor along the surface direction (lateral direction) of the insulating layer. It is possible to suppress the flow. As a result, even if a large potential difference occurs between the high voltage coil and the conductor, dielectric breakdown due to the potential difference can be prevented.
[Item 2]
The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the top surface to the bottom surface of the insulating layer.
The insulating layer in contact with the high voltage coil includes an insulating layer in which the high voltage coil is embedded and an insulating layer arranged above and below the high voltage coil and in contact with the upper surface and the lower surface of the high voltage coil, respectively. The semiconductor device according to 1.
[Item 3]
Item 2. The semiconductor device according to Item 1 or 2, wherein the compressive stress film includes a SiO _x (0 <x <2) film having a larger ratio of Si than SiO ₂ .

According to this configuration, since the compressive stress film is a SiO _x (0 <x <2) film, a good leak current reduction effect can be realized.
[Item 4]
Item 2. The semiconductor device according to Item 1 or 2, wherein the compressive stress film includes a compressive stress SiN film.
[Item 5]
Item 2. The semiconductor device according to any one of Items 1 to 4, wherein the compressive stress film has a compressive stress of 400 MPa to 800 MPa as an internal stress.
[Item 6]
Each of the insulating layers has a laminated structure of a thin film and an interlayer insulating film made of SiO ₂ formed on the thin film.
The thin film of the insulating layer in contact with the high voltage coil is selectively formed of the compressive stress film.
Item 2. The semiconductor according to any one of Items 1 to 5, wherein the thin film of the insulating layer other than the insulating layer in contact with the high voltage coil is formed of a tensile stress film having a tensile stress as an internal stress. apparatus.

According to this configuration, it is only necessary to selectively change the thin film of the insulating layer in contact with the high voltage coil to a compressive stress film. As a result, with respect to the plurality of insulating layers other than the insulating layer, the interlayer insulating film made of SiO ₂ having compressive stress and the thin film made of tensile stress film can be alternately arranged, so that the stress can be canceled at the laminated interface. Insulating layers can be laminated. As a result, when the insulating layer laminated structure is formed on the semiconductor substrate (wafer), it is possible to prevent the semiconductor substrate from being significantly warped and deformed.
[Item 7]
Item 6. The semiconductor device according to any one of Items 1 to 6, wherein the conductor includes a conductor layer formed in the same insulating layer as the high voltage coil.
[Item 8]
A high voltage pad formed on the surface of the insulating layer laminated structure in the high voltage region,
Further including a low voltage pad formed on the surface of the insulating layer laminated structure in the outer region.
The high-voltage coil is an upper coil arranged relatively close to the surface of the insulating layer laminated structure, and the low-voltage coil is a lower coil arranged below the upper coil.
Item 2. The item 1 to 7, wherein the conductor includes a low-voltage wiring that penetrates a plurality of the insulating layers downward from the low-voltage pad and is electrically connected to the lower coil. The semiconductor device described.

According to this configuration, since the above-mentioned withstand voltage structure (dielectric breakdown prevention structure) is formed, low-voltage wiring for contact with the lower coil can be formed through the insulating layer laminated structure. As a result, both the high-voltage pad and the low-voltage pad can be formed on the surface of the insulating layer laminated structure, and wire bonding to the pads can be easily performed.
[Item 9]
Item 8. The semiconductor device according to Item 8, wherein the low-voltage wiring includes a lead-out wiring drawn from a coil end inside the lower coil to the outer region via the insulating layer below the lower coil.
[Item 10]
The high voltage pad is arranged above the central portion of the upper coil.
Item 8. The semiconductor device according to Item 8 or 9, further comprising a high-voltage wiring that penetrates the insulating layer upward in the thickness direction from a coil end inside the upper coil and is connected to the high-voltage pad.
[Item 11]
Item 8-10, wherein the conductor includes a shield layer formed by penetrating a plurality of the insulating layers downward in the thickness direction so as to surround the high voltage region further outside the low voltage wiring. The semiconductor device according to any one item.
[Item 12]
Any of Items 1 to 11, wherein the distance L0 between the high voltage coil and the conductor is larger than the thickness L2 of the insulating layer between the high voltage coil and the low voltage coil. The semiconductor device according to paragraph 1.
[Item 13]
Item 12. The semiconductor device according to Item 12, wherein the ratio of the thickness L2 to the distance L0 (distance L0 / thickness L2) is 6/1 to 40/1.
[Item 14]
Item 12. The semiconductor device according to Item 12 or 13, wherein the thickness L2 is 12.0 μm to 16.8 μm, and the distance L0 is 100 μm to 450 μm.
[Item 15]
The semiconductor device according to any one of Items 1 to 14 and
A low-voltage element electrically connected to the low-voltage coil of the semiconductor device,
A high-voltage element electrically connected to the high-voltage coil of the semiconductor device,
A semiconductor module including the semiconductor device, the low-voltage element, and a resin package for collectively sealing the high-voltage element.

According to this configuration, since the semiconductor device according to any one of Items 1 to 14 is provided, a highly reliable transformer module in which dielectric breakdown is unlikely to occur can be realized.
(2) Another Embodiment 2 of the present invention
With respect to the subject described in FIG. 8, the inventors of this application have found that the cause of the leak current causing lateral fracture is (1) the formation of different interfaces on the sides of the upper coil 21 due to the contact of different insulating materials. And (2), in the manufacturing process of the insulating layer laminated structure 27, it was found that it is related to the existence of the processing interface damaged by the film formation such as CVD.

Therefore, in another embodiment 2 of the present invention, as shown in FIGS. 25, 27, 28 and 29, the intermediate region 48 in the insulating layer 28 in which the upper coil 21 is embedded and the insulating layer 28 above the insulating layer 28 is embedded. In, the removal region 110 from which the etching stopper film 29 is selectively removed is formed. As shown in FIGS. 25 and 27, the removal region 110 is formed in a single band shape (for example, width of 50 μm to 100 μm) surrounding each high voltage region 36. In particular, as shown in FIGS. 25 and 27, if the shape does not have rounded corners as a whole (substantially elliptical ring in another embodiment 2 of the present invention), it may be difficult for the electric field to concentrate.

Due to the formation of the removal region 110, the interlayer insulating film 30 (SiO ₂ ) above the laminated interface 111 in the intermediate region 48 is provided with the laminated interface 111 in which the upper coil 21 is in contact with the laminated interface of the insulating layer laminated structure 27. However, the same type of interface structure 112 is formed in contact with the lower interlayer insulating film 30 (SiO ₂ ).
As a result, even if a leak current flows from the upper coil 21 to the low voltage wiring 24 or the shield layer 69 along the surface direction (lateral direction) of the insulating layer 28, it can be reduced by the same type interface structure 112. That is, the leakage current can be reduced by eliminating different interfaces due to contact between different insulating materials (contact between SiO ₂ and SiN in another embodiment 2 of the present invention) at least in the intermediate region 48. As a result, even if a large potential difference occurs between the upper coil 21, the low voltage wiring 24, and the shield layer 69, dielectric breakdown due to the potential difference can be prevented.

Moreover, in another embodiment 2 of the present invention, a trench 113 having the same pattern as the removal region 110 is further formed in the interlayer insulating film 30 on the lower side of the laminated interface 111 halfway in the thickness direction of the interlayer insulating film 30. The upper interlayer insulating film 30 is embedded in the trench 113 via the removal region 110. As a result, the distance of the laminated interface 111 from the upper coil 21 to the outer low voltage region 47 can be extended by the depth d of the trench 113. As a result, the path of the leak current can be lengthened, so that the leak current can be satisfactorily reduced even if the processing interface exists at the laminated interface 111.

30A-30H are cross-sectional views for explaining a process related to the formation of the homologous interface structure 112.
In order to form the embedded type interface structure 112 shown in FIG. 29, for example, as shown in FIG. 30A, a via 55 is formed in the insulating layer 28 below the insulating layer 28 in which the upper coil 21 is embedded.

Next, as shown in FIG. 30B, the etching stopper film 29 and the USG film 114 made of SiN are sequentially formed by, for example, a plasma CVD method.
Next, as shown in FIG. 30C, a photoresist (not shown) is formed on the USG film 114, and the USG film 114, the etching stopper film 29, and the interlayer insulating film 30 are etched in this order. As a result, the removal region 110 and the trench 113 are formed at the same time.

Next, as shown in FIG. 30D, the trench 113 is backfilled with SiO ₂ by high-density plasma CVD (HDP), and then SiO ₂ is further deposited by plasma CVD. After that, the surface of SiO ₂ is flattened by CMP. As a result, the insulating layer 28 having the same type of interface structure 112 is formed in the trench 113.
Next, as shown in FIG. 30E, the upper coil 21, the low voltage layer wiring 53, and the inner coil end wiring 37 are formed on the insulating layer 28 having the same type of interface structure 112 with the lower insulating layer 28.

Next, as shown in FIG. 30F, the etching stopper film 29 and the USG film 115 made of SiN are sequentially formed by, for example, a plasma CVD method.
Next, as shown in FIG. 30G, a photoresist (not shown) is formed on the USG film 115, and the USG film 115, the etching stopper film 29, and the interlayer insulating film 30 are etched in this order. As a result, the removal region 110 and the trench 113 are formed at the same time.

Next, as shown in FIG. 30H, the trench 113 is backfilled with SiO ₂ by high-density plasma CVD (HDP), and then SiO ₂ is further deposited by plasma CVD. After that, the surface of SiO ₂ is flattened by CMP. As a result, the insulating layer 28 having the same type of interface structure 112 is formed in the trench 113.
Although the other embodiment 2 of the present invention has been described above, various design changes can be made in the other embodiment 2 of the present invention.

For example, as shown in FIG. 31, the homologous interface structure 112 may be selectively formed only on the lower laminated interface 111 in contact with the lower surface of the upper coil 21, or as shown in FIG. 32, the upper coil. It may be selectively formed only on the upper laminated interface 111 in contact with the upper surface of 21.
Further, as shown in FIG. 33, the removal regions 110 may be formed in a striped shape at intervals from each other. It is preferable that the trench 30 is also formed in a striped shape in accordance with the striped removal region 110. In this case, the line and space (L / S) of the striped removal region 110 is preferably 1 μm / 1 μm to 10 μm / 10 μm. The striped removal region 110 can be formed by striping the pattern of the photoresist for etching in the steps shown in FIGS. 30C and 30G described above.

Further, as shown in FIG. 34, when the upper coil 21 is formed by patterning an Al (aluminum) film instead of the embedded coil of the Cu wiring material 35, the etching stopper 29 is omitted and the insulating layer 28 is made of SiO. It can be formed only by the interlayer insulating film 30 made of ₂ . In this configuration, the same type of interface structure 112 is formed at all the laminated interfaces of the insulating layer laminated structure 27. Therefore, by forming the trench 113 described above and lengthening the leak current path, the effect of reducing the leak current can be further improved. Can be obtained effectively.

In addition to the invention described in the claims, the following features can be extracted from the contents of the other embodiment 2 of the present invention.
[Item 1]
An insulating layer laminated structure consisting of a plurality of insulating layers laminated in order,
A high-voltage coil and a low-voltage coil formed in the insulating layers different from each other in the insulating layer laminated structure and facing each other with the insulating layer of one or more layers interposed therebetween
It includes a conductor formed in the lateral outer region of the high voltage region in which the high voltage coil is arranged and electrically connected to a potential lower than that of the high voltage coil.
Of the plurality of laminated interfaces of the insulating layer laminated structure, the laminated interface to which the high voltage coil is in contact has the same insulating layer in the intermediate region between the high voltage region and the outer region via the laminated interface. A semiconductor device in which the same type of interface structure is formed by contacting with an insulating material.

According to this configuration, since the same type of interface structure is formed at least in the intermediate region, even if a leak current flows from the high voltage coil toward the conductor, it can be reduced by the same type of interface structure. That is, the leakage current can be reduced by eliminating different interfaces due to contact between different insulating materials at least in the intermediate region. As a result, even if a large potential difference occurs between the high voltage coil and the conductor, dielectric breakdown due to the potential difference can be prevented.
[Item 2]
The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the top surface to the bottom surface of the insulating layer.
The laminated interface in contact with the high-voltage coil is formed of an insulating layer in which the high-voltage coil is embedded and an insulating layer arranged above and below the high-voltage coil and in contact with the upper surface and the lower surface of the high-voltage coil, respectively. Item 2. The semiconductor device according to Item 1, which includes an interface.
[Item 3]
In the same type of interface structure, a trench is formed in a relatively lower insulating layer, and an upper insulating layer in contact with the upper surface of the lower insulating layer is formed so as to be embedded in the trench. The semiconductor device according to 1 or 2.

According to this configuration, the interface distance from the high voltage coil to the outer region can be extended by the depth of the trench. As a result, the leakage current path can be lengthened, so that the leakage current can be further reduced.
[Item 4]
Each insulating layer of the insulating layer laminated structure has a laminated structure of a thin film made of a first insulating material and an interlayer insulating film made of a second insulating material formed on the thin film.
The insulating layer above the laminated interface to which the high voltage coil is in contact has a removal region in which the thin film is selectively removed in the intermediate region.
Item 1 or item 1 or, wherein the interlayer insulating film of the upper insulating layer is in contact with the interlayer insulating film of the lower insulating layer with respect to the laminated interface through the removal region to form the same type of interface structure. 2. The semiconductor device according to 2.
[Item 5]
In the same type of interface structure, a trench having the same pattern as the removal region is formed in the interlayer insulating film of the lower insulating layer, and the interlayer insulating film of the upper insulating layer passes through the removal region. Item 4. The semiconductor device according to Item 4, which is formed so as to be embedded in the trench.

According to this configuration, the interface distance from the high voltage coil to the outer region can be extended by the depth of the trench. As a result, the leakage current path can be lengthened, so that the leakage current can be further reduced.
[Item 6]
Item 4. The semiconductor device according to Item 4 or 5, wherein the removal region is formed in a single band shape.
[Item 7]
Item 6. The semiconductor device according to Item 6, wherein the width of the strip-shaped removal region is 50 μm to 100 μm.
[Item 8]
Item 4. The semiconductor device according to Item 4 or 5, wherein the removal regions are formed in stripes at intervals from each other.

In particular, in Item 8, in the same type of interface structure, a stripe trench having the same pattern as the striped removal region is formed in the interlayer insulating film of the lower insulating layer, and the interlayer of the upper insulating layer is formed. It is preferable that the insulating film is formed so as to be embedded in the stripe trench via the removal region. As a result, the interface distance from the high voltage coil to the outer region can be further extended, so that the leakage current can be further reduced.
[Item 9]
Item 8. The semiconductor device according to Item 8, wherein the line and space (L / S) of the striped removal region is 1 μm / 1 μm to 10 μm / 10 μm.
[Item 10]
Item 6. The semiconductor device according to any one of Items 4 to 9, wherein the thin film is made of a SiN film and the interlayer insulating film is made of a SiO ₂ film.
[Item 11]
Item 2. The semiconductor device according to any one of Items 1 to 10, wherein the conductor includes a conductor layer formed in the same insulating layer as the high voltage coil.
[Item 12]
A high voltage pad formed on the surface of the insulating layer laminated structure in the high voltage region,
Further including a low voltage pad formed on the surface of the insulating layer laminated structure in the outer region.
The high-voltage coil is an upper coil arranged relatively close to the surface of the insulating layer laminated structure, and the low-voltage coil is a lower coil arranged below the upper coil.
Item 1 to any one of Items 1 to 11, wherein the conductor includes a low-voltage wiring that penetrates a plurality of the insulating layers downward in the thickness direction from the low-voltage pad and is electrically connected to the lower coil. The semiconductor device described.

According to this configuration, since the above-mentioned withstand voltage structure (dielectric breakdown prevention structure) is formed, low-voltage wiring for contact with the lower coil can be formed through the insulating layer laminated structure. As a result, both the high-voltage pad and the low-voltage pad can be formed on the surface of the insulating layer laminated structure, and wire bonding to the pads can be easily performed.
[Item 13]
Item 12. The semiconductor device according to Item 12, wherein the low-voltage wiring further includes a lead-out wire drawn from a coil end inside the lower coil to the outer region via the insulating layer below the lower coil.
[Item 14]
The high voltage pad is arranged above the central portion of the upper coil.
Item 12. The semiconductor device according to Item 12 or 13, further comprising a high-voltage wiring that penetrates the insulating layer upward in the thickness direction from a coil end inside the upper coil and is connected to the high-voltage pad.
[Item 15]
Item 12-14, wherein the conductor includes a shield layer formed by penetrating a plurality of the insulating layers downward in the thickness direction so as to surround the high voltage region further outside the low voltage wiring. The semiconductor device according to any one item.
[Item 16]
Any of Items 1 to 15, wherein the distance L0 between the high voltage coil and the conductor is larger than the thickness L2 of the insulating layer between the high voltage coil and the low voltage coil. The semiconductor device according to paragraph 1.
[Item 17]
Item 16. The semiconductor device according to Item 16, wherein the ratio of the thickness L2 to the distance L0 (distance L0 / thickness L2) is 6/1 to 40/1.
[Item 18]
Item 16. The semiconductor device according to Item 16 or 17, wherein the thickness L2 is 12.0 μm to 16.8 μm, and the distance L0 is 100 μm to 450 μm.
[Item 19]
The semiconductor device according to any one of Items 1 to 18 and
A low-voltage element electrically connected to the low-voltage coil of the semiconductor device,
A high-voltage element electrically connected to the high-voltage coil of the semiconductor device,
A semiconductor module including the semiconductor device, the low-voltage element, and a resin package for collectively sealing the high-voltage element.

According to this configuration, since the semiconductor device according to any one of Items 1 to 18 is provided, a highly reliable transformer module in which dielectric breakdown is unlikely to occur can be realized.
As described above, the above-described embodiment 1 and 2 of the present invention include high-voltage regions and low-voltage regions arranged at intervals in the direction (lateral direction) along the surface of the insulating layer. It is common in that the issue is to prevent dielectric breakdown between the two. Each of these forms solves the problem by providing structures A to C for preventing destruction between the high voltage region and the low voltage region.

One embodiment of the present invention is a structure A: an electric field shield portion made of an electrically floating metal member (preferably, the electric field shield portion is a capacitor made of a plurality of electrode plates facing each other at lateral intervals. As an example of), the capacitor 80 is disclosed. In another embodiment 1 of the present invention, as an example of a compressive stress film provided in contact with structure B: a high voltage region and having a compressive stress as an internal stress, SiO _x (which has a larger ratio of Si than SiO ₂ ) The insulating layer 28 made of a 0 <x <2) film and a SiN film having compressive stress is disclosed. Another second embodiment of the present invention discloses a structure C: a homogenous interface structure 112 made of SiO ₂ / SiO ₂ as an example of a homogeneous interface structure formed by contacting insulating layers made of the same insulating material.

These structures A to C may be adopted individually, or can be combined with each other to further increase the pressure resistance. For example, all the structures A to C may be provided between the high voltage region and the low voltage region, or a combination of structures A and B, a combination of structures A and C, and a combination of structures A and C may be provided. You may be. As an example of the combination of the structures A and B, in FIG. 6, the etching stopper film 29 (compressive stress film) which selectively has compressive stress with respect to the insulating layer 28 in which the upper coil 21 is embedded and the insulating layer 28 above the insulating layer 28 is formed. ) Should be adopted. Further, as an example of the combination of the structures A and C, in FIG. 6, if the same type interface structure 112 is provided between the capacitor 80 and the high voltage region 36 or between the outer low voltage region 47 and the capacitor 80. Good.

In addition, the components grasped from the disclosure of each of the above-mentioned figures can be combined with each other even with different figures.

1 Semiconductor module 2 Resin package 5 Controller chip 6 Transformer chip 7 Driver chip 13 Low voltage pad 14 High voltage pad 20 Lower coil 21 Upper coil 22 Inner coil end 23 Inner coil end 24 Low voltage wiring 25 High voltage wiring 26 Semiconductor board 27 Insulation Layer laminated structure 28 Insulation layer 29 Etching stopper film 30 Interlayer insulation film 31 Inner region 32 Inner region 33 Coil groove 35 Cu wiring material 36 High voltage region 37 Inner coil end wiring 46 Low voltage region 47 Outer low voltage region 48 Intermediate region 49 Inner coil end wiring 51 Penetration wiring 52 Drawer wiring 69 Shield layer 80 Capacitor 87 Electrode plate 110 Removal area 111 Laminated interface 112 Homogeneous interface structure 113 Trench

Claims (10)

With the first die pad
A second die pad separated from the first die pad by a predetermined distance in the first direction in a plan view,
The first semiconductor chip supported by the first die pad and
The second semiconductor chip supported by the second die pad and
It is supported by the first die pad so as to be arranged between the first semiconductor chip and the second semiconductor chip, and is formed in a quadrangular shape having a pair of first side and a pair of second sides and laminated. A transformer chip having an insulating layer laminated structure composed of a plurality of insulating layers and at least one pair of coils arranged vertically at intervals in the insulating layer laminated structure .
A first wire connecting the first semiconductor chip and the transformer chip ,
A second wire connecting the transformer chip and the second semiconductor chip,
A plurality of first pads arranged along one of the pair of first sides of the transformer chip , and
Includes a second pad located in an area surrounded by the pair of coils.
The coil has an inner coil end and an outer coil end.
The first pad includes a first group including an inner coil end pad connected to the inner coil end via a first lead-out wire extending across the coil in plan view and a region outside the coil in plan view. It is divided into a second group including an outer coil end pad connected to the outer coil end via a second lead-out wiring formed in.
Each of the first group and the second group has at least two of the first pads .
The distance between the front Symbol first group and said second group is longer than the distance between the first pad in said first group,
Before Symbol first wire is connected to one of said plurality of first pads,
A semiconductor device in which at least a part of the first lead-out wiring is arranged below the coil. The semiconductor device according to claim 1, wherein the first wire is shorter than the second wire. The semiconductor device according to claim 1 or 2, wherein the first wire is connected to the inner coil end pad or the outer coil end pad. The semiconductor device according to any one of claims 1 to 3, wherein the transformer chip is smaller than the first semiconductor chip. The semiconductor device according to any one of claims 1 to 4, wherein the second die pad is smaller than the first die pad. The semiconductor device according to any one of claims 1 to 5, further comprising a resin package covering the first semiconductor chip, the second semiconductor chip, and the transformer chip . The semiconductor device according to claim 6, wherein the resin package is formed of an epoxy resin in a square plate shape. The semiconductor device according to claim 6 or 7, which is a SOP (Small Outline Package) type package type. The semiconductor device according to any one of claims 1 to 8, wherein the first voltage applied to the plurality of first pads is lower than the second voltage applied to the second pads. The second semiconductor chip includes a driver chip that controls a SiC-MOSFET.
The semiconductor device according to any one of claims 1 to 9, wherein the second pad is connected to the driver chip.

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