JP5926003B2 - Signal transmission device and motor driving device using the same - Google Patents

Description

  The present invention relates to a signal transmission device using an insulating element, and a motor driving device using the same.

  FIG. 9 is a block diagram showing a conventional example of a signal transmission device. The signal transmission device 200 of this conventional example transmits various signals through the transformer chip 230 while insulating between the controller chip 210 and the driver chip 220. In particular, FIG. 9 depicts a circuit configuration for the controller chip 210 to recognize whether the driver chip 220 is abnormal.

  FIG. 10A is a timing chart showing a conventional output abnormality transmission operation (when the controller chip 210 can normally recognize whether the driver chip 220 is abnormal). When the driver chip 220 is normal and the abnormality detection signal Sa is at a low level (normal logic level), the abnormal pulse signal Sb from the driver chip 220 to the controller chip 210 is pulsed at a constant pulse period T1. Generated. On the other hand, when the driver chip 220 is abnormal and the abnormality detection signal Sa is at a high level (logical level at the time of abnormality), pulse generation of the abnormal pulse signal Sb is stopped. If the controller chip 210 cannot detect the pulse of the abnormal pulse signal Sb over the abnormality determination period T2 (where T2> T1), the controller chip 210 determines that an abnormality has occurred in the driver chip 220 and sets the abnormality signal Sc to the low level. Switch to (logic level at the time of abnormality).

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2010-246309 A

  However, in the signal transmission device 200 of the conventional example, if the abnormality detection period of the driver chip 220 (the high level period of the abnormality detection signal Sa) is too short, the abnormality generation period is stopped after the pulse generation of the abnormal pulse signal Sb is stopped. The pulse generation of the abnormal pulse signal Sb was restarted before the lapse of T2, and there was a possibility that the controller chip 210 could not recognize the abnormality of the driver chip 220 (see FIG. 10B).

  For example, if the driver chip 210 is equipped with a self-recovery overcurrent protection function, when the driver chip 210 is instantaneously restored from the overcurrent protection, the abnormality occurrence period of the driver chip 220 is shortened. There is a possibility that the abnormality 220 may not be recognized.

  In addition, if the pulse period T1 of the abnormal pulse signal Sb and the abnormality determination period T2 are set short, the above-described problem can be solved. However, such a solution is not the best solution because the current consumption in the transformer chip 230 increases.

  In view of the above problems found by the inventors of the present application, the present invention uses a signal transmission device capable of reliably transmitting one abnormality to the other while insulating the two circuits. An object is to provide a motor drive device.

  In order to achieve the above object, a signal transmission device according to the present invention performs signal transmission while insulating between a first circuit and a second circuit via an insulating element, wherein the first circuit Monitors an abnormal pulse signal transmitted from the second circuit to determine whether the second circuit is abnormal or not, and the second circuit is configured to detect at least the first circuit after an abnormality is detected in the second circuit. Thus, the abnormal pulse signal is held in an abnormal state (first configuration) until it is determined whether or not the second circuit is abnormal.

  In the signal transmission device having the first configuration, the second circuit includes an abnormality detection unit that generates an abnormality detection signal, a latch unit that latches the abnormality detection signal and generates an abnormality detection latch signal, A configuration (second configuration) including an abnormal pulse signal generation unit that allows / prohibits a pulse generation operation of the abnormal pulse signal based on the abnormality detection latch signal.

  Further, in the signal transmission device having the second configuration, the second circuit includes an output unit in which an output signal generation operation is permitted / prohibited based on the abnormality detection latch signal (third configuration). It is good to.

  In the signal transmission device having the second or third configuration, if the first circuit cannot detect a pulse of the abnormal pulse signal over a predetermined abnormality determination period, the second circuit has an abnormality. A configuration (fourth configuration) including an abnormality determination unit that determines that the occurrence has occurred is preferable.

  In the signal transmission device having the fourth configuration, the first circuit includes an abnormal signal output unit that outputs an abnormal signal according to a determination result of the abnormality determination unit to the outside of the signal transmission device. (Fifth configuration) is preferable.

  In the signal transmission device having any one of the second to fifth configurations, the latch unit may be configured to release the latch of the abnormality detection signal according to a latch release signal (sixth configuration).

  In the signal transmission device having the sixth configuration, the latch release signal may be input from the outside of the signal transmission device (seventh configuration).

  In the signal transmission device having the sixth configuration, the second circuit includes a timer unit that generates the latch release signal after a predetermined latch period has elapsed since the latch unit latched the abnormality detection signal. (Eighth configuration).

  Further, in the signal transmission device having the sixth configuration, the second circuit includes a timer unit that generates the latch release signal after a predetermined latch period has elapsed after the abnormality detection unit detects the cancellation of the abnormality. (9th configuration).

  Further, in the signal transmission device having the eighth or ninth configuration, the second circuit includes a clock signal oscillation unit that supplies a clock signal to both the abnormal pulse signal generation unit and the timer unit (first configuration). 10 configurations).

  The signal transmission device having any one of the first to tenth configurations includes a first semiconductor chip in which the first circuit is integrated, a second semiconductor chip in which the second circuit is integrated, A third chip in which insulating elements are integrated may be provided independently, and these may be configured to be sealed in one package (an eleventh configuration).

  Further, the signal transmission device having any one of the first to tenth configurations independently includes a first semiconductor chip in which the first circuit is integrated and a semiconductor chip in which the second circuit is integrated. These are sealed in one package, and the insulating element is preferably built in at least one of the first semiconductor chip and the second semiconductor chip (a twelfth structure).

  In the signal transmission device having any one of the first to twelfth configurations, the insulating element may be a transformer (a thirteenth configuration).

  In addition, a motor drive device according to the present invention outputs a signal transmission device having any one of the first to thirteenth configurations for transmitting a switch control signal while insulating the input and output, and the signal transmission device. And a switch element that performs supply control of the motor drive current in response to the switch control signal (fourteenth configuration).

  According to the present invention, it is possible to provide a signal transmission device capable of reliably transmitting one abnormality to the other while insulating two circuits, and a motor driving device using the signal transmission device.

The figure which shows the example of 1 structure of the motor drive device using the signal transmission apparatus which concerns on this invention. Detailed view of transmission / reception circuit part via transformers 31-34 Schematic diagram showing an example of terminal arrangement and chip arrangement in the package External terminal description table The block diagram which shows 1st Embodiment of the signal transmission apparatus which concerns on this invention. Timing chart showing output abnormality transmission operation of first embodiment The block diagram which shows 2nd Embodiment of the signal transmission apparatus which concerns on this invention. Timing chart showing a first example of output abnormality transmission operation of the second embodiment Timing chart showing a second example of output abnormality transmission operation of the second embodiment Block diagram showing a conventional example of a signal transmission device Timing chart showing conventional output abnormality transmission operation (when abnormality can be recognized) Timing chart showing conventional output abnormality transmission operation (when abnormality cannot be recognized)

  Hereinafter, a motor drive device using the signal transmission device according to the present invention (particularly, a motor drive IC mounted on a hybrid vehicle using a high voltage) will be described in detail as an example.

  FIG. 1 is a block diagram showing a configuration example of a motor drive device using a signal transmission device according to the present invention. The motor drive device of this configuration example includes a high-side switch SWH, a low-side switch SWL, a switch control device 1 that is a control means of the high-side switch SWH, an engine control unit 2 (hereinafter referred to as ECU [Engine Control Unit] 2) DC voltage sources E1 and E2, an npn bipolar transistor Q1, a pnp bipolar transistor Q2, capacitors C1 to C3, resistors R1 to R8, and a diode D1.

  The switch control device 1 is formed by sealing a first semiconductor chip 10, a second semiconductor chip 20, and a third semiconductor chip 30 in one package.

  The first feature regarding the switch control device 1 is that the withstand voltage between input and output is 1200V. The second feature is that a UVLO is incorporated. A third feature is that a watchdog timer function is incorporated. The fourth feature is that an overcurrent protection function (automatic return type) is incorporated. A fifth feature is a built-in soft turn-off function during overcurrent protection operation. The sixth feature is that an external error detection function (ERRIN) is incorporated. The seventh feature is that an abnormal state output function (FLT, OCPOUT) is incorporated. The eighth feature is that an active mirror clamp function is incorporated. The ninth feature is that a short circuit clamp function is incorporated.

  The first semiconductor chip 10 is driven by being supplied with a first power supply voltage VCC1 (5 [V], 3.3 [V], etc. based on GND1) from the DC voltage source E1, and is switch-controlled based on an input signal IN. A controller chip in which a controller that generates signals S1 and S2 is integrated. The main functions of the first semiconductor chip 10 are the generation function or output function of switch control signals S1 and S2, the transformer transmission abnormality monitoring function (input / output logic monitoring function of the input signal IN), the error state output function, the UVLO function, In addition, an external error input signal processing function can be cited. The withstand voltage of the first semiconductor chip 10 may be designed to an appropriate withstand voltage (for example, 7 [V] withstand voltage) in consideration of the first power supply voltage VCC1 (GND1 reference).

  The second semiconductor chip 20 is driven by being supplied with the second power supply voltage VCC2 (10 to 30 [V] based on GND2) from the DC voltage source E2, and is driven from the first semiconductor chip 10 through the third semiconductor chip 30. This is a driver chip in which a driver that controls driving of the high-side switch SWH to which a high voltage VD1 of several hundreds [V] is applied to one end based on input switch control signals S1 and S2 is integrated. The main functions of the second semiconductor chip 20 include a function for generating or outputting an output signal OUT, an overcurrent / overvoltage protection function, and a UVLO function. The withstand voltage of the second semiconductor chip 20 may be designed to an appropriate withstand voltage (for example, 40 [V] withstand voltage) in consideration of the second power supply voltage VCC2 (GND2 reference).

  The third semiconductor chip 30 delivers the switch control signals S1 and S2, the watchdog signal S3, and the fault signal S4 while galvanically insulating the first semiconductor chip 10 and the second semiconductor chip 20. A transformer chip in which a transformer is integrated. Note that the third semiconductor chip 30 may be a chip that does not use a semiconductor substrate.

  As described above, the switch control device 1 of this configuration example includes the third semiconductor on which only the transformer is mounted, apart from the first semiconductor chip 10 in which the controller is integrated and the second semiconductor chip 20 in which the driver is integrated. The chip 30 is provided independently, and these are sealed in one package.

  By adopting such a configuration, the first semiconductor chip 10 and the second semiconductor chip 20 are both produced by a general low withstand voltage process (several [V] withstand voltage to several tens [V] withstand voltage). Therefore, it is not necessary to use a dedicated high withstand voltage process (several hundreds [V] withstand voltage), and the manufacturing cost can be reduced.

  Further, both the first semiconductor chip 10 and the second semiconductor chip 20 can be produced by a proven existing process, and it is not necessary to perform a new reliability test, thereby shortening the development period. And can contribute to the reduction of development costs.

  In addition, when changing the specification, it is possible to easily cope by replacing only the chip (for example, only the second semiconductor chip 20 when changing the specification of the output side). This eliminates the need for redevelopment and contributes to shortening the development period and reducing development costs.

  The ECU 2 is a means for comprehensively performing electric control in engine operation and motor operation, and a microcontroller that exchanges various signals (IN, RST, FLT, OCPOUT) with the switch control device 1. It is.

  The high side switch SWH and the low side switch SWL are respectively between the application end of the first motor drive voltage VD1 and one end of the motor coil, and between the application end of the second motor drive voltage VD2 and one end of the motor coil. It is a means connected between them to perform supply control of the motor drive current according to each on / off control. In the motor drive device of this configuration example, an insulated gate bipolar transistor (IGBT [Insulated Gate Bipolar Transistor]) is used as each of the high side switch SWH and the low side switch SWL. However, the configuration of the present invention is not limited thereto. Instead, a MOS [Metal Oxide Semiconductor] field effect transistor using a SiC [Silicon Carbide] semiconductor or a MOS field effect transistor using a Si semiconductor may be employed. In particular, a MOS field effect transistor using a SiC semiconductor has a higher withstand voltage and a higher heat resistant temperature than a MOS field effect transistor using a Si semiconductor, and thus is suitable for mounting in a hybrid vehicle.

  Next, the internal configuration of the switch control device 1 will be described.

  The first semiconductor chip 10 includes a first transmitter 11, a second transmitter 12, a first receiver 13, a second receiver 14, a logic unit 15, and a first low voltage lockout unit 16 (hereinafter referred to as “the first low voltage lockout unit 16”). The first UVLO [Under Voltage Lock Out] section 16), an external error detection section (external error detection comparator) 17, and N-channel MOS field effect transistors Na and Nb.

  The second semiconductor chip 20 includes a third receiving unit 21, a fourth receiving unit 22, a third transmitting unit 23, a fourth transmitting unit 24, a logic unit 25, a driver unit 26, and a second low voltage lock. Out section 27 (hereinafter referred to as second UVLO section 27), overcurrent detection section (overcurrent detection comparator) 28, OCP [Over Current Protection] timer 29, and P-channel MOS field effect transistors P1 and P2 And N-channel MOS field effect transistors N1 to N3 and an SR flip-flop FF.

  The third semiconductor chip 30 includes a first transformer 31, a second transformer 32, a third transformer 33, and a fourth transformer 34.

  The first transmission unit 11 is means for transmitting the switch control signal S <b> 1 input from the logic unit 15 to the third reception unit 21 via the first transformer 31. The second transmission unit 12 is means for transmitting the switch control signal S <b> 2 input from the logic unit 15 to the fourth reception unit 22 via the second transformer 32. The first receiver 13 is means for receiving the watchdog signal S3 input from the third transmitter 23 via the third transformer 33 and transmitting it to the logic unit 15. The fourth receiver 14 is means for receiving the driver abnormality signal S4 input from the fourth transmitter 24 via the fourth transformer 34 and transmitting it to the logic unit 15.

  The logic unit 15 exchanges various signals (IN, RST, FLT, OCPOUT) with the ECU 2, and the first transmission unit 11, the second transmission unit 12, the first reception unit 13, and the second It is means for exchanging various signals (S1 to S4) with the second semiconductor chip 20 using the receiving unit.

  When the input signal IN is at a high level, the logic unit 15 generates the switch control signals S1 and S2 so that the output signal OUT is at a high level. Conversely, when the input signal IN is at a low level, The switch control signals S1 and S2 are generated so that the output signal OUT is at a low level. More specifically, the logic unit 15 detects the positive edge (the rising edge from the low level to the high level) of the input signal IN and pulses the switch control signal S1, while the negative edge ( A falling edge from the high level to the low level) is detected, and a pulse is generated in the switch control signal S2.

  Further, when the reset signal RST is at the low level, the logic unit 15 disables the generation operation of the output signal OUT, that is, the switch control signals S1, S2 so as to fix the output signal OUT at the low level. Conversely, when the reset signal RST is at a high level, the switch control is performed so that the generation operation of the output signal OUT is enabled, that is, the output signal OUT is set to a logic level corresponding to the input signal IN. Signals S1 and S2 are generated. When the reset signal RST is maintained at a low level for a predetermined time (for example, 500 [ns]), the logic unit 15 generates the switch control signals S1 and S2 so that the protection operation by the overcurrent detection unit 28 is restored. To do.

  Further, when the switch control device 1 is normal, the logic unit 15 turns off the transistor Na and opens the first state signal FLT (pull-up state by the resistor R1), and when the switch control device 1 is abnormal (first semiconductor chip). When a low voltage abnormality on the 10 side, a transformer transmission abnormality of the switch control signals S1 and S2, or an ERRIN signal abnormality is detected), the transistor Na is turned on and the first state signal FLT is set to the low level. With such a configuration, the ECU 2 can grasp the state of the switch control device 1 by monitoring the first state signal FLT. The low voltage abnormality on the first semiconductor chip 10 side may be determined based on the detection result of the first UVLO unit 16, and the transformer transmission abnormality of the switch control signals S1 and S2 may be determined as the input signal IN. The determination may be made based on the comparison result between the (switch control signals S1, S2) and the watchdog signal S3. Further, the ERRIN signal abnormality may be determined based on the output result of the external error detection unit 17.

  Further, when the switch control device 1 is normal, the logic unit 15 turns off the transistor Nb and opens the second state signal OCPOUT (pull-up state by the resistor R2), and when the switch control device 1 is abnormal (second semiconductor chip). When a low voltage abnormality on the 20 side or an overcurrent of the motor drive current flowing through the high side switch SWH is detected), the transistor Nb is turned on and the second state signal OCPOUT is set to the low level. With such a configuration, the ECU 2 can grasp the state of the switch control device 1 by monitoring the second state signal OCPOUT. Note that the low voltage abnormality on the second semiconductor chip 20 side and the overcurrent of the motor driving current flowing through the high side switch SWH may be determined based on the driver abnormality signal S4.

  The first UVLO unit 16 is means for monitoring whether or not the first power supply voltage VCC1 is in a low voltage state and transmitting the monitoring result to the logic unit 15.

  The external error detection unit 17 compares the voltage (divided voltage obtained by resistance-dividing the analog voltage to be monitored) input from the connection node of the resistors R3 and R4 to the ERRIN terminal with a predetermined threshold voltage. , Means for transmitting the comparison result to the logic unit 15.

  The third receiver 21 is means for receiving the switch control signal S1 input from the first transmitter 11 via the first transformer 31 and transmitting it to the set input terminal (S) of the SR flip-flop FF. The fourth receiver 22 is a means for receiving the switch control signal S2 input from the second transmitter 12 via the second transformer 32 and transmitting it to the reset input terminal (R) of the SR flip-flop FF. The third transmitter 23 is means for transmitting the watchdog signal S2 input from the logic unit 25 to the first receiver 13 via the third transformer 33. The fourth transmitter 24 is means for transmitting the driver abnormality signal S4 input from the logic unit 25 to the second receiver 14 via the fourth transformer 34.

  The SR flip-flop FF sets the output signal to a high level using the pulse edge of the switch control signal S1 input to the set input terminal (S) as a trigger, and the switch control signal S2 input to the reset input terminal (R). The output signal is reset to low level using a pulse edge as a trigger. That is, the output signal is the same signal as the input signal IN input from the ECU 2 to the logic unit 15. The output signal is sent to the logic unit 25 from the output terminal (Q) of the SR flip-flop FF.

  The logic unit 25 generates a drive signal for the driver unit 26 based on the output signal of the SR flip-flop FF (the same signal as the input signal IN).

  Further, when the logic unit 25 determines that a low voltage abnormality or an overcurrent has occurred based on the detection results of the second UVLO unit 27 and the overcurrent detection unit 28, the driver unit 26 uses the abnormality detection signal to indicate that. Is transmitted to the logic unit 15 by the driver abnormality signal S4. With such a configuration, even when an abnormality occurs in the second semiconductor chip 20, the driver unit 26 can quickly perform a protective operation, and the logic unit 15 performs an abnormality notification operation (second operation) to the ECU 2. (Low level transition of the state signal OCPOUT) can be performed. The logic unit 25 has a function of automatically returning from the overcurrent protection operation when a predetermined time has elapsed after the overcurrent protection operation.

  In addition, the logic unit 25 outputs the output signal of the SR flip-flop FF as it is to the third transmission unit 23 as the watchdog signal S3. As described above, in the configuration in which the watchdog signal S3 is returned from the second semiconductor chip 20 toward the first semiconductor chip 10, in the logic unit 15, the input signal IN input to the first semiconductor chip 10 and this On the other hand, by comparing the watchdog signal S3 returned from the second semiconductor chip 20, it is possible to determine the presence or absence of transformer transmission abnormality.

  The driver unit 26 is means for performing on / off control of the transistor P1 and the transistor N1 based on the drive signal input from the logic unit 25, and outputting an output signal OUT from a connection node between the transistor P1 and the transistor N1. . The output signal OUT is input to the high side switch SWH via a drive circuit composed of transistors Q1 and Q2. When the output signal OUT is at a high level, the high side switch SWH is turned on. Conversely, when the output signal OUT is at a low level, the high side switch SWH is turned off.

  Note that the driver unit 26 causes the transistor N2 to absorb the charge (mirror current) from the gate of the high-side switch SWH via the CLAMP terminal when the voltage level (GND2 reference) of the output signal OUT becomes low level. It has a function to turn on (active mirror clamp function). With such a configuration, the transistor N2 is turned on after the high-side switch SWH is turned off, so that when the low-side switch SWL is turned on, the high-side switch SWH is turned on by the inflow current from the collector-gate capacitance. It is possible to suppress an increase in the gate potential of the side switch SWH.

  Further, the driver unit 26 turns on the transistor P2 so that the gate of the high-side switch SWH is clamped to the power supply voltage VCC2 via the CLAMP terminal when the voltage level (GND2 reference) of the output signal OUT becomes high level. (Short circuit clamp function). With this configuration, when the high side switch SWH is turned on, the gate potential of the high side switch SWH does not rise to a potential higher than the power supply voltage VCC2.

  When the driver unit 26 determines that the protection operation needs to be performed based on the abnormality detection signal input from the logic unit 25, the driver unit 26 turns off the transistors P1 and P2 and the transistors N1 and N2. It has a function to turn on N3 (soft turn-off function). By such switch control, charge can be more slowly extracted from the gate of the high-side switch SWH via the resistor R5 during protection operation than during normal operation. By adopting such a configuration, it is possible to prevent the motor current from being momentarily interrupted during the protective operation, so that it is possible to suppress surges caused by the back electromotive force of the motor coil, as well as internal cables, bus bars, etc. It is also possible to suppress surge due to parasitic inductance. Note that the fall time during the protection operation can be arbitrarily adjusted by appropriately selecting the resistance value of the resistor R5.

  The second UVLO unit 27 is means for monitoring whether or not the second power supply voltage VCC2 is in a low voltage state and transmitting the monitoring result to the logic unit 25.

  The overcurrent detection unit 28 compares a voltage (divided voltage obtained by resistance-dividing the anode voltage of the diode D1) from the connection node of the resistors R7 and R8 to the OCP / DESATIN terminal and a predetermined threshold voltage. The comparison result is transmitted to the logic unit 25. Note that the greater the motor drive current flowing through the high side switch SWH, the greater the collector-emitter voltage of the insulated gate bipolar transistor used as the high side switch SWH. Therefore, as the motor drive current flowing through the high side switch SWH increases, the anode voltage of the diode D1 increases, and as a result, the voltage input to the OCP / DESATIN terminal increases. Therefore, the overcurrent detection unit 28 detects that the motor drive current flowing through the high side switch SWH is excessive when the voltage (GND2 reference) input to the OCP / DESATIN reaches a predetermined threshold (for example, 0.5 [V]). It is determined that the current state.

  In this configuration example, a configuration (voltage detection method) is adopted in which the motor drive current is detected by detecting the collector-emitter voltage of the insulated gate bipolar transistor used as the high-side switch SWH. Although the description has been given by way of example, the detection method of the motor drive current is not limited to this, for example, the motor drive current flowing in the high-side switch SWH (or a mirror current that exhibits equivalent behavior). May be applied to the sense resistor to generate a voltage signal and input it to the OCP / DESATIN terminal (current detection method).

  The OCP timer 29 is means for counting the elapsed time after the overcurrent protection operation.

  The first transformer 31 is a DC insulation element for transmitting the switch control signal S <b> 1 from the first semiconductor chip 10 to the second semiconductor chip 20. The second transformer 32 is a DC insulation element for transmitting the switch control signal S <b> 2 from the first semiconductor chip 10 to the second semiconductor chip 20. The third transformer 33 is a DC insulation element for transmitting the watchdog signal S3 from the second semiconductor chip 20 to the first semiconductor chip 10. The fourth transformer 34 is a DC insulation element for transmitting the driver abnormality signal S4 from the second semiconductor chip 20 to the first semiconductor chip 10.

  In this way, if the configuration is such that not only the switch control signals S1 and S2 but also the watchdog signal S3 and the driver abnormality signal S4 are exchanged between the first semiconductor chip 10 and the second semiconductor chip 20, the high-side switch In addition to the SWH on / off control, various protection functions can be appropriately realized.

  FIG. 2 is a detailed diagram of a transmission / reception circuit portion through the transformers 31-34. As shown in the figure, the first transmitter 11, the second transmitter 12, the first receiver 13, and the second receiver 14 provided on the first semiconductor chip 10 side are all, for example, between VCC1 and GND1. The third receiving unit 21, the fourth receiving unit 22, the third transmitting unit 23, and the fourth transmitting unit 24 provided on the second semiconductor chip 20 side are all, for example, It is driven by a power supply voltage between VCC2 and GND2.

  With such a configuration, as described above, the first semiconductor chip 10 and the second semiconductor chip 20 both have a general low breakdown voltage process (several [V] breakdown voltage to several tens [V]. Therefore, it is not necessary to use a dedicated high withstand voltage process (several hundreds [V] withstand voltage), and the manufacturing cost can be reduced.

  In FIG. 2, a configuration using a comparator having hysteresis characteristics is depicted for each of the first receiver 13, the second receiver 14, the third receiver 21, and the fourth receiver 22. However, the presence or absence of hysteresis characteristics is arbitrary.

  Next, details of various functions of the switch control device 1 will be described in a comprehensive manner.

<UVLO1 (Controller side malfunction prevention function at low voltage)>
When the controller side power supply voltage (voltage between VCC1 and GND1) becomes equal to or lower than a predetermined lower threshold voltage _VUVLO1L , the switch control device 1 turns off the high side switch SWH and _sets the FLT terminal to a low level. On the other hand, when the controller-side power supply voltage (voltage between VCC1 and GND1) becomes _{equal to} or higher than the predetermined upper threshold voltage _VUVLO1H , the switch control device 1 starts normal operation and opens the FLT terminal (high level).

<UVLO2 (driver side malfunction prevention function at low voltage)>
When the driver side power supply voltage (voltage between VCC2 and GND2) becomes equal to or lower than a predetermined lower threshold voltage _VUVLO2L , the switch control device 1 turns off the high side switch SWH and sets the OCPOUT terminal to a low level. On the other hand, the switch control device 1 starts normal operation when the driver-side power supply voltage (voltage between VCC2 and GND2) becomes _{equal to} or higher than a predetermined upper threshold voltage _VUVLO2H , and opens the OCPOUT terminal (high level).

<Analog error input>
When the input voltage to the ERRIN terminal becomes _{equal to} or higher than a predetermined threshold voltage V _ERRDET , the switch control device 1 turns off the high side switch SWH and _sets the FLT terminal to a low level. By adopting such a configuration, an abnormality occurring in the peripheral circuit of the switch control device 1 can be monitored and an appropriate protection operation can be performed. For example, it can be used for an overvoltage protection operation of a motor power supply. Is possible. The threshold voltage _ERRDET may have a predetermined hysteresis ( _VERRYSS ).

<Overcurrent protection>
When the input voltage to the OCP / DESATIN terminal becomes _equal to or higher than a predetermined threshold voltage V _OCDET (vs. GND2), the switch control device 1 turns off the high side switch SWH and sets the OCPOUT terminal to a low level.

<Overcurrent protection automatic recovery>
The switch control device 1 automatically recovers after a predetermined time (t _OCPRLS ) has elapsed after the overcurrent protection operation, and opens the OCPOUT terminal (high level). The return time may be fixedly set inside the switch control device 1 or may be adjustable from the outside of the device.

<Watchdog timer>
The switch control device 1 compares the input signal IN input from the ECU 2 to the first semiconductor chip 10 with the watchdog signal S3 fed back from the second semiconductor chip 20 to the first semiconductor chip 10, and determines the logic of both signals. Is inconsistent, self-correction is performed in the switch control device 1 so that the input signal IN and the watchdog signal S3 match, and the FLT terminal is set to low level.

<Soft turn-off during protection operation>
In the overcurrent protection operation, the switch control device 1 sets the PROOUT terminal to a low level and opens the OUT terminal. By such control, the high side switch SWH can be slowly turned off. The off-time slew rate can be arbitrarily adjusted by appropriately selecting the resistance value of the external resistor R5.

<Active mirror clamp>
The switch control device 1 sets the CLAMP terminal to L when the gate potential of the high side switch SWH becomes equal to or lower than a predetermined threshold voltage V _AMC . Such control makes it possible to reliably turn off the high-side switch SWH.

<Short circuit clamp>
When the applied voltage at the CLAMP terminal becomes equal to or higher than VCC2-V _SCC , the switch control device 1 sets the CLAMP terminal to a high level. Such control prevents the gate potential of the high-side switch SWH from rising above the second power supply voltage VCC2.

  FIG. 3 is a schematic diagram showing an example of the terminal arrangement and the chip arrangement in the package. As shown in FIG. 3, in the switch control device 1 of this configuration example, the package has a plurality of pins arranged on two opposite sides, and the first semiconductor chip 10, the second semiconductor chip 20, and The third semiconductor chips 30 are arranged perpendicular to the arrangement direction of the plurality of pins (lateral direction of the paper).

  By adopting such a chip arrangement, the pins 11 to 20 connected to the first semiconductor chip 10 and the pins 1 to 10 connected to the second semiconductor chip 20 are distributed and arranged on two opposite sides. Therefore, it is possible to prevent a short circuit between the pins 11 to 20 and the pins 1 to 10 while keeping the pin interval to a minimum. Moreover, since the creeping distance between the pins 11 to 20 and the pins 1 to 10 can be secured, it is possible to prevent air discharge from the pins 11 to 20 to the pins 1 to 10.

  Further, as shown in FIG. 3, in the switch control device 1 of this configuration example, the first semiconductor chip 10 and the third semiconductor chip 30 are mounted on the first island 40, and the second semiconductor chip 20 is It is mounted on the second island 50. With such a configuration, the first island 40 can be used as a low-voltage side island (GND1 fixed) and the second island 50 can be used as a high-voltage side island (VEE2 fixed). Become. The first island 40 and the second island 50 are both made of a non-magnetic material (for example, copper), but a magnetic material (for example, iron) may be used.

  FIG. 4 is an explanatory table of external terminals. Pin 1 (NC) is a non-connection terminal. Pin 2 (VEE2) is a negative power supply terminal (for example, minimum: −15V). Pin 3 (GND2) is a GND terminal and is connected to the emitter of the insulated gate bipolar transistor Tr1 outside the switch control device 1. Pin 4 (OCP / DESATIN) is an overcurrent detection terminal. Pin 5 (OUT) is an output terminal. Pin 6 (VCC2) is a positive power supply terminal (for example, maximum: 30V). Pin 7 (CLAMP) is a clamp terminal. Pin 8 (PROOUT) is a soft turn-off output terminal. Pin 9 (VEE2) is a negative power supply terminal. Pin 10 (NC) is a non-connection terminal. Pin 11 (GND1) is a GND terminal. Pin 12 (IN) is a control input terminal. Pin 13 (RST) is a reset input terminal. Pin 14 (FLT) is an output terminal for the first state signal (abnormal state detection signal on the controller chip side). Pin 15 (OCPOUT) is an output terminal for the second state signal (driver chip side abnormal state detection signal). Pin 16 (ERRIN) is an error detection terminal. Pin 17 (VCC1) is a power supply terminal (for example, 5V). Both the pin 18 (NC) and the pin 19 (NC) are non-connection terminals. Pin 20 (GND1) is a GND terminal.

  Next, a circuit configuration for transmitting a driver abnormality signal from the driver chip to the controller chip will be described more specifically.

  FIG. 5 is a block diagram showing a first embodiment of a signal transmission device according to the present invention. The signal transmission device 100 according to the first embodiment includes a controller chip 110 (corresponding to the first semiconductor chip 10 in FIG. 1), a driver chip 120 (corresponding to the second semiconductor chip 20 in FIG. 1), and a transformer chip 130 (FIG. 1 corresponding to the third semiconductor chip 30), and these are sealed in one package.

  In the controller chip 110, an abnormality determination unit 111 and an abnormality signal output unit 112 are integrated as components of the first circuit. The first circuit monitors the abnormal pulse signal Sb (corresponding to the driver abnormal signal S4 in FIG. 1) transmitted from the driver chip 120, and determines whether the driver chip 120 is abnormal.

  The abnormality determination unit 111 determines that an abnormality has occurred in the driver chip 120 if the pulse of the abnormal pulse signal Sb cannot be detected over a predetermined abnormality determination period T2.

  The abnormality signal output unit 112 outputs an abnormality signal Sc (corresponding to the second state signal OCPOUT in FIG. 1) according to the determination result in the abnormality determination unit 111 to the outside of the signal transmission device 100. The abnormality signal Sc is at a high level if the abnormality determination unit 111 determines that the driver chip 120 has no abnormality, and is at a low level if it is determined that the driver chip 120 has an abnormality. However, the relationship between the determination result in the abnormality determination unit 111 and the logic level of the abnormality signal Sc may be reversed.

  In the driver chip 120, an output unit 121, an abnormality detection unit 122, a clock signal oscillation unit 123, an abnormal pulse signal generation unit 124, and a latch unit 125 are integrated as components of the second circuit. Yes. The second circuit is characterized in that the abnormal pulse signal Sb is held in an abnormal state from when the abnormality is detected by the driver chip 120 until at least the controller chip 110 determines whether the driver chip 120 is abnormal. Have.

  The output unit 121 corresponds to the output signal So (corresponding to the output signal OUT in FIG. 1) in response to the switch control signal (corresponding to the switch control signals S1 and S2 in FIG. 1, not shown in FIG. 5) transmitted from the controller chip 110. ) Is generated. By using this output signal So to turn on / off the switch element connected to one end of the motor coil, it is possible to control the supply of motor drive current.

  In the output unit 121, the generation operation of the output signal So is permitted / prohibited based on the abnormality detection latch signal Sa '. More specifically, when the abnormality detection latch signal Sa ′ is at the low level (normal logic level), the generation operation of the output signal So is permitted, and the abnormality detection latch signal Sa ′ is at the high level (at the time of abnormality). (Logical level), the generation operation of the output signal So is prohibited. With such a configuration, when the driver chip 120 is abnormal, the operation of the output unit 121 can be forcibly stopped without waiting for a protection signal from the outside.

  The abnormality detection unit 122 monitors the operation state of the driver chip 120 (for example, whether or not there is an overcurrent flowing through the output unit 121) and generates an abnormality detection signal Sa. The abnormality detection signal Sa is at a low level (normal logic level) if no abnormality has occurred in the driver chip 120, and is at a high level (logical level at abnormality) if an abnormality has occurred. However, the relationship between the presence / absence of an abnormality of the driver chip 120 and the logic level of the abnormality detection signal Sa may be reversed.

  The clock signal oscillator 123 generates a clock signal Sx having a predetermined frequency and supplies it to the abnormal pulse signal generator 124.

  The abnormal pulse signal generation unit 124 generates an abnormal pulse signal Sb based on the clock signal Sx. In the abnormal pulse signal generation unit 124, the pulse generation operation of the abnormal pulse signal Sb is permitted / prohibited based on the abnormality detection latch signal Sa '. More specifically, when the driver chip 120 is normal and the abnormality detection latch signal Sa ′ is low level (normal logic level), the abnormal pulse signal Sb is pulsed at a constant pulse period T1. Generated. The pulse period T1 is determined according to the pulse period of the clock signal Sx. On the other hand, when the driver chip 120 is abnormal and the abnormality detection latch signal Sa 'is at a high level (logical level at the time of abnormality), the generation of the pulse of the abnormal pulse signal Sb is stopped.

  When the abnormality detection signal Sa rises from a low level (normal logic level) to a high level (abnormal logic level), the latch unit 125 sets the abnormality detection latch signal Sa ′ low. After rising from the level to the high level, the abnormality detection latch signal Sa ′ is latched at the high level (the logic level at the time of abnormality) without depending on the logic level of the abnormality detection signal Sa. In addition, the latch unit 125 synchronizes with the abnormality detection latch signal when a pulse is raised to the latch release signal Sd input from the outside of the signal transmission device 100 via the controller chip 110 and the transformer chip 120. Sa ′ is returned from the high level (logical level at the time of abnormality) to the low level (logic level at the time of normality).

  The transformer chip 130 includes insulating elements 131 and 132, and performs bidirectional transmission of various signals while insulating between the controller chip 110 and the driver chip 120. An insulating element 131 for transmitting the abnormal pulse signal Sb from the driver chip 120 to the controller chip 110 and an insulating element 132 for transmitting the latch release signal Sd from the controller chip 110 to the driver chip 120. In either case, a transformer can be used.

  FIG. 6 is a timing chart showing the output abnormality transmission operation of the first embodiment. In order from the top, the clock signal Sx, the abnormality detection signal Sa, the abnormality detection latch signal Sa ′, the abnormal pulse signal Sb, the abnormal signal Sc, And the latch release signal Sd is depicted.

  When the driver chip 120 is normal, the abnormality detection signal Sa and the abnormality detection latch signal Sa ′ are both maintained at a low level (normal logic level). Therefore, a pulse is generated in the abnormal pulse signal Sb at a constant pulse period T1, and the abnormality determination unit 111 determines that there is no driver abnormality. As a result, the abnormality signal Sc is maintained at a high level (normal logic level).

  On the other hand, when an abnormality occurs in the driver chip 120, both the abnormality detection signal Sa and the abnormality detection latch signal Sa ′ rise from a low level (normal logic level) to a high level (abnormal logic level). It is done. Thereafter, the abnormality detection latch signal Sa 'is latched at the high level (the logic level at the time of abnormality) until the pulse is raised to the latch release signal Sd without depending on the logic level of the abnormality detection signal Sa. Therefore, the pulse generation operation of the abnormal pulse signal Sb is stopped for at least the abnormality determination period T2, and the abnormality determination unit 111 determines that there is a driver abnormality. As a result, the abnormal signal Sc falls from a high level (normal logic level) to a low level (abnormal logic level).

  Thereafter, when a pulse rises in the latch release signal Sd, the abnormality detection latch signal Sa 'is restored from the high level (logical level at the time of abnormality) to the low level (logical level at the time of normality) in synchronization with this. Therefore, the pulse generation operation of the abnormal pulse signal Sb is resumed, and the abnormality determination unit 111 determines that there is no driver abnormality. As a result, the abnormal signal Sc is raised from a low level (logic level at the time of abnormality) to a high level (logic level at the time of normal).

  As described above, in the case of the signal transmission device 100 according to the first embodiment, even if the abnormality detection period of the driver chip 120 (the high level period of the abnormality detection signal Sa) is short, The abnormal pulse signal Sb can be held in an abnormal state (pulse stop state) until the presence / absence of the abnormality of the chip 120 is determined, so that the abnormality of the driver chip 120 can be reliably transmitted to the controller chip 110. .

  Note that there is a delay time T3 depending on the generation timing of the clock signal Sx and the latch release signal Sd after the pulse is raised to the latch release signal Sd and before the pulse generation operation of the abnormal pulse signal Sb is restarted. . For example, as shown in FIG. 6, when the pulse of the abnormal pulse signal Sb is generated at the timing when the pulse of the clock signal Sx rises, the pulse of the latch release signal Sd rises immediately after the pulse of the clock signal Sx rises. When the pulse of the latch release signal Sd rises immediately before the rise of the clock signal Sx, the delay time T3 becomes short. On the contrary, when the pulse of the abnormal pulse signal Sb is generated at the timing when the pulse of the clock signal Sx falls, a delay occurs when the pulse of the latch release signal Sd rises immediately after the pulse of the clock signal Sx falls. The time T3 becomes longer, and the delay time T3 becomes shorter if the pulse of the latch release signal Sd rises immediately before the pulse of the clock signal Sx falls.

  FIG. 7 is a block diagram showing a second embodiment of the signal transmission device according to the present invention. The signal transmission device 100 of the second embodiment has substantially the same configuration as that of the first embodiment described above, and is characterized in that a timer unit 126 is added to the driver chip 120. Therefore, the same components as those in the first embodiment are denoted by the same reference numerals as those in FIG. 5, and redundant descriptions are omitted. In the following, the characteristic portions of the second embodiment are mainly described.

  The timer unit 126 generates a pulse of the latch release signal Sd after a predetermined latch period T4 has elapsed after the latch unit 125 latches the abnormality detection signal Sa. Specifically, when the abnormality detection signal Sa is raised from a low level (normal logic level) to a high level (abnormal logic level), the timer unit 126 uses the rising edge as a trigger to trigger a latch period. The count of T4 is started, and when the count of the latch period T4 is completed (when the number of pulses of the clock signal Sx reaches a predetermined value n), a one-shot pulse is generated for the latch release signal Sd (see FIG. 8A). ).

  Thus, unlike the first embodiment, the signal transmission device 100 according to the second embodiment does not need to receive the latch release signal Sd from the outside. Accordingly, in the signal transmission device 100 of the second embodiment, the external terminal that receives the input of the latch release signal Sd and the insulating element 132 that transmits the latch release signal Sd between the controller chip 110 and the driver chip 120 are provided. Omitting this makes it possible to achieve scale reduction and cost reduction.

  The timer unit 126 is configured to count the latch period T4 by receiving the supply of the clock signal Sx generated by the clock signal oscillating unit 123 and counting the number of pulses of the clock signal Sx. . With such a configuration, it is possible to easily and reliably adjust the pulse period T1, the abnormality determination period T2, and the latch period T4.

  The latch period T4 varies depending on the generation timing of the clock signal Sx and the abnormality detection signal Sa. For example, as shown in FIG. 8A, the pulse count of the clock signal Sx is started when the abnormality detection signal Sa rises from a low level (normal logic level) to a high level (abnormal logic level). In this case, if the abnormality detection signal Sa rises to a high level immediately after the pulse of the clock signal Sx rises, the latch period T4 becomes long, and the abnormality detection signal Sa rises to a high level immediately before the pulse of the clock signal Sx rises. When this is done, the latch period T4 becomes shorter. Conversely, as shown in FIG. 8B, the pulse count of the clock signal Sx is started when the abnormality detection signal Sa falls from the high level (logical level at the time of abnormality) to the low level (logical level at the time of normality). When the abnormality detection signal Sa falls to the low level immediately after the pulse of the clock signal Sx rises, the latch period T4 becomes longer, and the abnormality detection signal Sa rises to the low level just before the pulse of the clock signal Sx rises. When lowered, the latch period T4 becomes shorter.

  On the other hand, the first operation example shown in FIG. 8A (configuration in which counting of the latch period T4 is started at the rising edge of the abnormality detection signal Sa) and the second operation example (falling edge of the abnormality detection signal Sa) shown in FIG. 8B. In any of the configurations in which the counting of the latch period T4 is started), the pulse of the latch release signal Sd and the pulse of the clock signal Sx rise simultaneously, so the delay time T3 shown in FIG. 6 becomes zero.

  In the above embodiment, the motor drive device using the signal transmission device according to the present invention has been described as an example. However, the application target of the present invention is not limited to this, and a transformer is used. The present invention can be applied to all signal transmission apparatuses (for example, transformer couplers).

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  INDUSTRIAL APPLICABILITY The present invention is suitably used to increase the reliability of motor drive ICs (gate driver ICs) widely mounted on home appliances such as hybrid vehicles, electric vehicles, and air conditioners that use high voltage, and industrial machines, for example. It is a possible technology.

1 Switch control device 2 Engine control unit (ECU)
10 First semiconductor chip (controller chip)
DESCRIPTION OF SYMBOLS 11 1st transmission part 12 2nd transmission part 13 1st receiving part 14 2nd receiving part 15 Logic part (transformer drive signal production | generation part)
16 1st low voltage lockout part (1st UVLO part)
17 External error detector (comparator)
20 Second semiconductor chip (driver chip)
21 3rd receiving part 22 4th receiving part 23 3rd transmitting part 24 4th transmitting part 25 Logic part 26 Driver part 27 2nd low voltage lockout part (2nd UVLO part)
28 Overcurrent detector (comparator)
29 OCP timer 30 Third semiconductor chip (transformer chip)
31 1st transformer 32 2nd transformer 33 3rd transformer 34 4th transformer 40 1st island (low voltage side island)
50 2nd island (high-pressure side island)
100 signal transmission device 110 controller chip (first circuit)
111 Abnormality determination unit 112 Abnormal signal output unit 120 Driver chip (second circuit)
121 Output Unit 122 Abnormality Detection Unit 123 Clock Signal Oscillation Unit 124 Abnormal Pulse Signal Generation Unit 125 Latch Unit 126 Timer Unit 130 Transchip (Third Circuit)
131, 132 Insulating element (transformer)
FF SR flip-flop SWH High side switch (IGBT, SiC-MOS)
SWL Low-side switch (IGBT, SiC-MOS)
Na, Nb, N1 to N3 N channel type MOS field effect transistor P1, P2 P channel type MOS field effect transistor E1, E2 DC voltage source Q1 npn type bipolar transistor Q2 pnp type bipolar transistor C1 to C3 capacitor R1 to R8 resistor D1 diode

Claims (13)

A signal transmission device that performs signal transmission while insulating between the first circuit and the second circuit via an insulating element,
The first circuit monitors the abnormal pulse signal transmitted from the second circuit via the insulating element, and if the pulse of the abnormal pulse signal cannot be detected over a predetermined abnormality determination period, the second circuit Including an abnormality determination unit that determines that an abnormality has occurred in the circuit;
The second circuit holds the abnormal pulse signal in an abnormal state by stopping the pulse generation operation of the abnormal pulse signal for at least the abnormality determination period after the abnormality is detected in the second circuit. A characteristic signal transmission device. The second circuit includes:
An anomaly detector that generates an anomaly detection signal;
A latch unit that latches the abnormality detection signal and generates an abnormality detection latch signal;
An abnormal pulse signal generation unit in which a pulse generation operation of the abnormal pulse signal is permitted / prohibited based on the abnormality detection latch signal;
The signal transmission device according to claim 1, comprising:   3. The signal transmission device according to claim 2, wherein the second circuit includes an output unit in which an output signal generation operation is permitted / prohibited based on the abnormality detection latch signal.   The first circuit includes an abnormality signal output unit that outputs an abnormality signal according to a determination result of the abnormality determination unit to the outside of the signal transmission device. The signal transmission device according to one item. The latch unit, the signal transmission device according to claim 2 or claim 3, characterized in that unlatching of said abnormality detection signal in response to the latch release signal.   6. The signal transmission device according to claim 5, wherein the latch release signal is input from the outside of the signal transmission device.   The signal according to claim 5, wherein the second circuit includes a timer unit that generates the latch release signal after a predetermined latch period has elapsed since the abnormality detection signal was latched by the latch unit. Transmission device.   6. The signal according to claim 5, wherein the second circuit includes a timer unit that generates the latch release signal after a predetermined latch period has elapsed since the abnormality detection unit detected the cancellation of the abnormality. Transmission device.   9. The signal transmission device according to claim 7, wherein the second circuit includes a clock signal oscillation unit that supplies a clock signal to both the abnormal pulse signal generation unit and the timer unit.   A first semiconductor chip in which the first circuit is integrated; a second semiconductor chip in which the second circuit is integrated; and a third chip in which the insulating element is integrated. The signal transmission device according to any one of claims 1 to 9, wherein the signal is sealed in a single package.   The first semiconductor chip in which the first circuit is integrated and the second semiconductor chip in which the second circuit is integrated are independently provided, and these are sealed in one package, and the insulation 10. The signal transmission device according to claim 1, wherein an element is built in at least one of the first semiconductor chip and the second semiconductor chip. 11.   The signal transmission device according to claim 1, wherein the insulating element is a transformer. The signal transmission device according to any one of claims 1 to 12, wherein the switch control signal is transmitted while insulating between the input and output;
A switch element that performs supply control of a motor drive current in accordance with the switch control signal output from the signal transmission device;
A motor drive device comprising:

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