JP6591637B2 - Semiconductor device and semiconductor module - Google Patents

Description

  The present invention relates to a semiconductor device including a transformer and a semiconductor module including the semiconductor device.

For example, in the field of power electronics, the development of a transformer having a pair of coils arranged opposite to each other is underway.
Patent Document 1 discloses a transformer having a pair of inductors. One inductor rotates 180 ° about the central axis as a rotation axis and is disposed opposite to the other inductor.

JP 2013-115131 A

Generally, the withstand voltage portion of a transformer is an insulating film between a pair of coils. This is because a large voltage between the coils of the transformer is applied to the insulating film, and a thin insulating film cannot withstand the voltage.
On the other hand, a low voltage region (for example, a region where wiring for a low voltage coil is formed) may be provided in a region away from the transformer in the in-plane direction (lateral direction) of the insulating film. Usually, the distance between the low voltage region and the transformer is set to be several tens of times or more than the distance between the coils of the transformer. For this reason, little investigation has been made to date about the occurrence of dielectric breakdown in the region between the low voltage region and the transformer.

However, as a result of intensive studies by the inventors of this application, when a surge breakdown test is performed between the coils of the transformer, the insulating film may be broken along the lateral direction even if there is no breakdown between the coils. I understood it.
One embodiment of the present invention provides a semiconductor device capable of improving the withstand voltage between a high voltage coil and a low potential portion in a low voltage region around the high voltage coil.

  Moreover, one embodiment of the present invention provides a semiconductor module that can improve the breakdown voltage between a high voltage coil and a low potential portion in a low voltage region around the high voltage coil.

  In order to achieve the above object, a semiconductor device is formed of an insulating layer stacked structure including a plurality of insulating layers stacked in order and the insulating layers different from each other in the insulating layer stacked structure, and sandwiches one or more insulating layers. A high voltage coil and a low voltage coil that are opposed to each other, and a conductive material that is formed in an outer region on the side of the high voltage region where the high voltage coil is disposed and is electrically connected to a potential lower than that of the high voltage coil. The insulating layer in contact with the high voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high voltage coil.

According to this configuration, the portion of the insulating layer that comes into contact with the high voltage coil is formed of the compressive stress film, so that a leakage current flows from the high voltage coil to the conductor along the surface direction (lateral direction) of the insulating layer. Flowing can be suppressed. Thereby, even if a large potential difference occurs between the high voltage coil and the conductor, it is possible to prevent dielectric breakdown due to the potential difference.
In the semiconductor device, the high voltage coil includes an embedded coil embedded in a coil groove penetrating from the upper surface to the lower surface of one insulating layer, and the insulating layer in contact with the high voltage coil includes the high voltage coil. It may include an embedded insulating layer and insulating layers that are disposed above and below the insulating layer and are in contact with the upper surface and the lower surface of the high voltage coil, respectively.

In the semiconductor device, the compressive stress film may include a SiO _x (0 <x <2) film having a larger Si ratio than SiO ₂ .
According to this configuration, since the compressive stress film is a SiO _x (0 <x <2) film, it is possible to realize a good leakage current reduction effect.
In the semiconductor device, the compressive stress film may include a compressive stress SiN film.

In the semiconductor device, the compressive stress film may have a compressive stress of 400 MPa to 800 MPa as an internal stress.
In the semiconductor device, each insulating layer has a laminated structure of a thin film and an interlayer insulating film made of SiO ₂ formed on the thin film, and the thin film of the insulating layer in contact with the high voltage coil is selected. The thin film of the other insulating layer excluding the insulating layer in contact with the high voltage coil may be formed of a tensile stress film having a tensile stress as an internal stress. .

According to this configuration, it is only necessary to selectively change the thin film of the insulating layer in contact with the high voltage coil to the compressive stress film. Thereby, with respect to a plurality of insulating layers excluding the insulating layer, an interlayer insulating film made of SiO ₂ having a compressive stress and a thin film made of a tensile stress film can be alternately arranged, so that stress is canceled at the laminated interface. An insulating layer can be stacked. As a result, when the insulating layer laminated structure is formed on the semiconductor substrate (wafer), it is possible to prevent the semiconductor substrate from being greatly warped.

In the semiconductor device, the conductor may include a conductor layer formed on the same insulating layer as the high voltage coil.
The semiconductor device further includes a high voltage pad formed on the surface of the insulating layer stacked structure in the high voltage region, and a low voltage pad formed on the surface of the insulating layer stacked structure in the outer region, The high voltage coil is an upper coil disposed on the side relatively closer to the surface of the insulating layer laminated structure, the low voltage coil is a lower coil disposed below the upper coil, and the conductor is The low voltage pad may include a low voltage wiring that penetrates the plurality of insulating layers downward in the thickness direction and is electrically connected to the lower coil.

According to this configuration, since the breakdown voltage structure (dielectric breakdown prevention structure) is formed, a low-voltage wiring for contacting the lower coil can be formed through the insulating layer laminated structure. Accordingly, both the high voltage pad and the low voltage pad can be formed on the surface of the insulating layer laminated structure, and wire bonding to the pad can be easily performed.
In the semiconductor device, the low-voltage wiring may include a lead-out wiring led out from a coil end inside the lower coil to the outer region via the insulating layer below the lower coil.

In the semiconductor device, the high voltage pad is disposed above a central portion of the upper coil, penetrates the insulating layer upward in the thickness direction from a coil end inside the upper coil, and the high voltage pad It may further include a high voltage wiring connected to the.
In the semiconductor device, the conductor includes a shield layer formed by penetrating a plurality of the insulating layers downward in the thickness direction so as to surround the high voltage region further outside the low voltage wiring. May be.

In the semiconductor device, the distance L0 between the high voltage coil and the conductor may be larger than the thickness L2 of the insulating layer between the high voltage coil and the low voltage coil. .
In the semiconductor device, the ratio of the thickness L2 to the distance L0 (distance L0 / thickness L2) may be 6/1 to 40/1.
In the semiconductor device, the thickness L2 may be 12.0 μm to 16.8 μm, and the distance L0 may be 100 μm to 450 μm.

A semiconductor module for achieving the above object is electrically connected to the semiconductor device, a low voltage element electrically connected to the low voltage coil of the semiconductor device, and the high voltage coil of the semiconductor device. A high voltage element, and the semiconductor device, the low voltage element, and a resin package for collectively sealing the high voltage element.
According to this configuration, since the semiconductor device of the present invention is provided, it is possible to realize a highly reliable transformer module that hardly causes dielectric breakdown.

FIG. 1 is a schematic plan view of a semiconductor module showing Reference Example 1. FIG. FIG. 2 is a diagram showing the connection form of the semiconductor module and the potential of each part. FIG. 3 is a schematic diagram for explaining the planar structure of the transformer chip. FIG. 4 is a schematic diagram for explaining the planar structure of the lower coil of the transformer chip. FIG. 5 is a schematic diagram for explaining a planar structure of the upper coil of the transformer chip. 6 is a sectional view of the transformer chip (a sectional view taken along line VI-VI in FIG. 3). FIG. 7 is an enlarged view of a main part of the transformer chip of FIG. FIG. 8 is a diagram showing the relationship between the thickness of the interlayer film and the breakdown voltage in a semiconductor chip including a transformer. FIG. 9 shows a modification relating to the capacitor pattern in the transformer chip. FIG. 10 shows a modification relating to the capacitor pattern in the transformer chip. FIG. 11 shows a modification relating to the capacitor pattern in the transformer chip. FIG. 12 shows a modification relating to the pattern of capacitors in the transformer chip. FIG. 13 shows a modification relating to the pattern of capacitors in the transformer chip. FIG. 14 is a view for explaining the structure of an electrode plate as an example of an electric field shield portion instead of the capacitor. FIG. 15 shows a modification regarding the pattern of the electrode plate. FIG. 16 shows a modification regarding the pattern of the electrode plate. FIG. 17 shows a modification regarding the connection state of the substrate of the transformer chip. FIG. 18 shows a modification regarding the connection state of the substrate of the transformer chip. FIG. 19 shows a modification regarding the connection state of the substrate of the transformer chip. FIG. 20 is a schematic plan view of a transformer chip according to an embodiment of the present invention. FIG. 21 is a schematic plan view of a layer in which the lower coil according to the embodiment of the present invention is disposed. FIG. 22 is a schematic plan view of a layer in which the upper coil according to the embodiment of the present invention is arranged. 23 is a cross-sectional view that appears when the transformer chip is cut along the cutting line XXIII-XXIII in FIG. FIG. 24 is an enlarged view of the upper coil and its periphery in FIG. FIG. 25 is a schematic plan view of a transformer chip according to Reference Example 2. FIG. 26 is a schematic plan view of a layer in which the lower coil according to Reference Example 2 is disposed. FIG. 27 is a schematic plan view of a layer in which the upper coil according to Reference Example 2 is disposed. FIG. 28 is a cross-sectional view that appears when the transchip is cut along the cutting line XXVIII-XXVIII in FIG. FIG. 29 is an enlarged view of the upper coil and its periphery in FIG. FIG. 30A is a cross-sectional view for explaining a process related to formation of the homogeneous interface structure. FIG. 30B is a diagram showing a step subsequent to that in FIG. 30A. FIG. 30C is a diagram showing a step subsequent to that in FIG. 30B. FIG. 30D is a diagram showing a step subsequent to that in FIG. 30C. FIG. 30E is a diagram showing a step subsequent to that in FIG. 30D. FIG. 30F is a diagram showing a step subsequent to that in FIG. 30E. FIG. 30G is a diagram showing a step subsequent to that in FIG. 30F. FIG. 30H is a diagram showing a step subsequent to that in FIG. 30G. FIG. 31 is a diagram showing a modification of the same kind of interface structure. FIG. 32 is a diagram showing a modification of the same kind of interface structure. FIG. 33 is a diagram showing a modified example of the same kind of interface structure. FIG. 34 is a diagram showing a modification of the same kind of interface structure.

Hereinafter, embodiments and reference examples of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor module 1 showing Reference Example 1. FIG. In FIG. 1, the central portion of the module 1 is shown through to clarify the internal structure of the semiconductor module 1.
The semiconductor module 1 is a module in which a plurality of chips are packaged, and includes a resin package 2, a plurality of leads 3, and a plurality of chips 4.

The resin package 2 is formed in a square (square) plate shape using, for example, an epoxy resin.
In the first reference example, the plurality of leads 3 are provided across the inside and outside of the resin package 2 via a pair of opposite end surfaces of the resin package 2. Thereby, the package type of the semiconductor module 1 is SOP (Small Outline Package). The semiconductor module 1 is not limited to SOP, and various types of packages such as QFP (Quad Flat Package) and SOJ (Small Outline J-lead Package) can be employed.

The plurality of chips 4 includes a controller chip 5 (controller IC) as an example of the low voltage element of the present invention, a transformer chip 6 as an example of the semiconductor device of the present invention, and an example of the high voltage element of the present invention. And a driver chip 7 (driver IC).
The transformer chip 6 is disposed at the substantially central portion of the resin package 2, and the controller chip 5 and the driver chip 7 are disposed on one lead 3 side and the opposite lead 3 side with respect to the transformer chip 6, respectively. That is, the controller chip 5 and the driver chip 7 are arranged so as to sandwich the transformer chip 6 therebetween, and are adjacent to the plurality of leads 3, respectively.

  Each of the chips 5 to 7 is formed in a square (rectangular) plate shape. In this reference example 1, the transformer chip 6 is formed smaller than the controller chip 5 and the driver chip 7 having substantially the same size. Yes. Further, the controller chip 5 and the transformer chip 6 are disposed on a common first die pad 8, and the driver chip 7 is disposed on a second die pad 9 provided at a distance from the first die pad 8.

  A plurality of pads 10 and pads 11 are formed on the surface of the controller chip 5. The plurality of pads 10 are arranged along the long side of the controller chip 5 on the side close to the leads 3, and are connected to the leads 3 by bonding wires 12. The plurality of pads 11 are arranged along the long side on the opposite side of the lead 3 of the controller chip 5 (the side close to the transformer chip 6).

  A plurality of low voltage pads 13 and high voltage pads 14 are formed on the surface of the transformer chip 6. The plurality of low voltage pads 13 are arranged along the long side of the transformer chip 6 on the side close to the controller chip 5, and are connected to the pads 11 of the controller chip 5 by bonding wires 15. That is, in Reference Example 1, the pad 11 of the controller chip 5 is connected to the primary side of the transformer chip 6. The plurality of high voltage pads 14 are arranged along the long side of the transformer chip 6 at the center in the width direction of the transformer chip 6.

  A plurality of pads 16 and pads 17 are formed on the surface of the driver chip 7. The plurality of pads 16 are arranged along the long side of the driver chip 7 on the side close to the transformer chip 6 and are connected to the high voltage pads 14 of the transformer chip 6 by bonding wires 18. That is, in Reference Example 1, the pad 16 of the driver chip 7 is connected to the secondary side of the transformer chip 6. The plurality of pads 17 are arranged along the long side of the driver chip 7 opposite to the transformer chip 6 (the side close to the leads 3), and are connected to the leads 3 by bonding wires 19.

1 is merely an example, and can be appropriately changed according to the package type and the arrangement form of the chips 4.
FIG. 2 is a diagram showing the connection configuration of the semiconductor module 1 of FIG.
As shown in FIG. 2, in the semiconductor module 1, in the transformer chip 6, the lower coil 20 on the primary side (low voltage side) as an example of the low voltage coil of the present invention and the secondary coil as an example of the high voltage coil of the present invention. The upper coil 21 on the side (high voltage side) is opposed to the upper coil 21 in the vertical direction. The lower coil 20 and the upper coil 21 are each formed in a spiral shape.

A low voltage wiring 24 and a low voltage wiring 93 are connected to the inner coil end 22 (inner end of the spiral) and the outer coil end 92 (outer end of the spiral) of the lower coil 20, respectively. The ends of the low voltage wirings 24 and 93 are exposed as the low voltage pad 13.
A high voltage wiring 25 (inner coil end wiring) and a high voltage wiring 95 (outer coil end wiring) are connected to the inner coil end 23 and the outer coil end 94 of the upper coil 21, respectively. The ends of the high voltage wirings 25 and 95 are exposed as high voltage pads 14.

  In the controller chip 5, a transistor Tr <b> 1 is provided in the middle of a wiring 90 that connects a certain pad 10 and a certain pad 11. A transistor Tr2 is provided in the middle of the wiring 91 that connects the other pad 10 and the other pad 11. The transistors Tr1 and Tr2 are switching elements for conducting / interrupting the wirings 90 and 91, respectively. The pads 10 and 11 on the wiring 90 side are connected to the input voltage and the low voltage pad 13 on the outer coil end 92 side through bonding wires 12 and 15, respectively. The pads 10 and 11 on the wiring 91 side are connected to the ground voltage and the low voltage pad 13 on the inner coil end 22 side through bonding wires 12 and 15, respectively.

By controlling the controller chip 5 so that the first application state (Tr1: ON, Tr2: OFF) and the second application state (Tr1: OFF, Tr2: ON) are alternately repeated, the lower coil 20 of the transformer chip 6 is obtained. A periodic pulse voltage is generated. For example, in FIG. 2, a pulse voltage of 5 V is generated in the lower coil 20 with respect to the reference voltage = 0 V (ground voltage).
In the transformer chip 6, only the AC signal based on the pulse voltage generated in the lower coil 20 by the electromagnetic induction is selectively selectively transmitted to the high voltage side (upper coil 21) while the DC signal is blocked between the lower coil 20 and the upper coil 21. ). The transmitted AC signal is boosted according to the transformation ratio between the lower coil 20 and the upper coil 21, and taken out to the driver chip 7 through the bonding wire 18. For example, in FIG. 2, a pulse voltage of 5V is extracted to the driver chip 7 as a pulse voltage of 15V with respect to the reference voltage = 1200V. The driver chip 7 performs the switching operation of the MOSFET by applying the input 15V pulse voltage to a gate electrode (not shown) of a SiC power MOSFET (for example, source-drain voltage = 1200 V).

The specific voltage values shown in FIG. 2 are only examples used for explaining the operation of the semiconductor module 1. The reference voltage of the driver chip 7 (HV region) may be a value exceeding 1200V (for example, 3750V).
FIG. 3 is a schematic diagram for explaining the planar structure of the transformer chip 6 of FIG. FIG. 4 is a schematic diagram for explaining a planar structure of a layer in which the lower coil 20 of the transformer chip 6 is disposed. FIG. 5 is a schematic diagram for explaining a planar structure of a layer in which the upper coil 21 of the transformer chip 6 is disposed. FIG. 6 is a cross-sectional view of the transformer chip 6 (a cross-sectional view taken along line VI-VI in FIG. 3). FIG. 7 is an enlarged view of the upper coil 21 and its periphery in FIG. In FIG. 6, only the metal part is shown by hatching for the sake of clarity.

Next, the internal structure of the transformer chip 6 will be described more specifically.
As illustrated in FIG. 6, the transformer chip 6 includes a semiconductor substrate 26 and an insulating layer stacked structure 27 formed on the semiconductor substrate 26. As the semiconductor substrate 26, a Si (silicon) substrate, a SiC (silicon carbide) substrate, or the like can be applied.
The insulating layer stacked structure 27 includes a plurality (12 layers in FIG. 6) of insulating layers 28 stacked in order from the surface of the semiconductor substrate 26. The plurality of insulating layers 28 each have a laminated structure of a lower etching stopper film 29 and an upper interlayer insulating film 30 except for the lowermost insulating layer 28 in contact with the surface of the semiconductor substrate 26. The lowermost insulating layer 28 includes only the interlayer insulating film 30. As the etching stopper film 29, for example, a SiN film, a SiC film, a SiCN film, or the like can be used. As the interlayer insulating film 30, for example, a SiO ₂ film can be used.

  The lower coil 20 and the upper coil 21 are formed in different insulating layers 28 in the insulating layer laminated structure 27 and face each other with one or more insulating layers 28 interposed therebetween. In this reference example 1, the lower coil 20 is formed on the fourth insulating layer 28 from the semiconductor substrate 26, and the upper coil 21 has the sixteen insulating layers 28 sandwiched between the lower coil 20 and the eleventh layer. The insulating layer 28 is formed.

As shown in FIGS. 3 to 5, the lower coil 20 and the upper coil 21 are arranged around the inner regions 31 and 32 so that the inner regions 31 and 32 having an elliptical shape in plan view are partitioned in the center. Is formed in an elliptical annular region surrounding the.
The structure of the lower coil 20 and the upper coil 21 in the region surrounding each of the inner regions 31 and 32 can be described with reference to the upper coil 21 shown in FIG. That is, as shown in FIG. 7, an elliptic spiral coil groove 33 is formed in the insulating layer 28 in a region surrounding the inner region 32. The coil groove 33 is formed through the interlayer insulating film 30 and the etching stopper film 29 below the interlayer insulating film 30. Thereby, the upper end and the lower end of the coil groove 33 are surfaces opened to the etching stopper film 29 of the upper insulating layer 28 and the interlayer insulating film 30 of the lower insulating layer 28, respectively.

  A barrier metal 34 is formed on the inner surface (side surface and bottom surface) of the coil groove 33. The barrier metal 34 is formed in a film shape following the side surface and the bottom surface so that a space having an open top is formed in the coil groove 33. In Reference Example 1, the barrier metal 34 is formed by laminating a Ta (tantalum) film, a TaN (tantalum nitride) film, and a Ta film in this order from the side close to the inner surface of the coil groove 33. Then, by embedding a Cu (copper) wiring material 35 inside the barrier metal 34 in the coil groove 33, the upper coil 21 as an example of an embedded coil made of the barrier metal 34 and the Cu wiring material 35 is formed.

  The upper coil 21 is formed so that the upper surface thereof is flush with the upper surface of the insulating layer 28. Thus, the upper coil 21 is in contact with different insulating layers 28 on the side surface, the upper surface, and the lower surface. Specifically, in the insulating layer 28 in which the upper coil 21 is embedded, the etching stopper film 29 and the interlayer insulating film 30 are in contact with the side surface of the upper coil 21, and the insulating layer 28 formed on the upper side of the insulating layer 28. Only the lower etching stopper film 29 is in contact with the upper surface of the upper coil 21. In the lower insulating layer 28, only the upper interlayer insulating film 30 is in contact with the lower surface of the upper coil 21.

Although not described here, the lower coil 20 is formed by embedding a barrier metal and a Cu wiring material in the coil groove in the same manner as the upper coil 21.
As shown in FIGS. 3, 6 and 7, the high voltage pad 14 is formed on the surface of the insulating layer stacked structure 27 (on the interlayer insulating film 30 of the uppermost insulating layer 28). The high voltage pad 14 is disposed in a central high voltage region (HV region) 36 in which the upper coil 21 is disposed in a plan view of the transformer chip 6 viewed from above along the stacking direction of the insulating layer stacked structure 27. Yes.

  Here, the high voltage region 36 includes a region where the upper coil 21 and a wiring having the same potential as the upper coil 21 are formed in the insulating layer 28 in which the upper coil 21 is embedded, and a peripheral portion of the formation region. In the first reference example, as shown in FIG. 5, a total of four upper coils 21 are formed in pairs of two at intervals in the longitudinal direction of the transformer chip 6. An inner coil end wiring 37 and an outer coil end wiring 96 are formed between the inner region 32 of each pair of the upper coils 21 and the adjacent upper coils 21, respectively. Thus, in each pair, one upper coil 21 and the other upper coil 21 are electrically connected to each other by a common outer coil end wiring 96 therebetween, and both the upper coil 21 and the outer coil therebetween. The end wiring 96 and the inner coil end wiring 37 in each upper coil 21 are all at the same potential. Therefore, in the insulating layer 28, the inner region 32 of each upper coil 21 and the region between the upper coils 21 in each pair are also covered by the electric field from the upper coil 21, the inner coil end wiring 37, or the outer coil end wiring 96. It is included in the high voltage region 36 as the inside. The region where the lower coil 21 (low voltage coil) is arranged coincides with the high voltage region 36 in a plan view, but is isolated from the high voltage coil 21 by a plurality of insulating layers 28, and is separated from the upper coil 21. Since it is hardly affected by the electric field, it is not included in the high voltage region 36 referred to in the first reference example.

More specifically, as shown in FIG. 3, the high voltage pad 14 has a total of six, one above the inner region 32 of each upper coil 21 and one above the region between the upper coils 21 in each pair. Are arranged.
For example, as shown in FIGS. 6 and 7, a certain high voltage pad 14 is connected to an inner coil end wiring 37 embedded in the same insulating layer 28 as the upper coil 21 through a via 38. Although not shown, the other high voltage pads 14 are connected to the outer coil end wiring 96 embedded in the same insulating layer 28 as the upper coil 21 through vias by the same structure. As a result, the AC signal transmitted to the upper coil 21 can be output from the high voltage pad 14 via the inner coil end wiring 37 and via 38 and the outer coil end wiring 96 and via (not shown). . That is, the inner coil end wiring 37 and the via 38 connected thereto, and the outer coil end wiring 96 and the via connected thereto become the high voltage wiring 25 and the high voltage wiring 95 shown in FIG.

  The inner coil end wiring 37 and the via 38 are formed by embedding barrier metals 41 and 42 and Cu wiring materials 43 and 44 in the wiring grooves 39 and 40 as shown in FIG. (The same applies to the outer coil end wiring 96 and vias connected thereto). The same material as that of the above-described barrier metal 34 can be applied to the barrier metals 41 and 42.

On the other hand, the insulating layer laminated structure 27 includes a low voltage region 46 (FIGS. 4 and 6) and an outer low voltage region 47 (see FIG. 4 and FIG. 6) as a low potential region (LV region) electrically separated from the high voltage region 36. 3 to 7) and the intermediate region 48 (FIGS. 3 to 7) are set.
The low voltage region 46 includes a region where the lower coil 20 and a wiring having the same potential as the lower coil 20 are formed in the insulating layer 28 in which the lower coil 20 is embedded, and a peripheral portion of the formation region. Similar to the relationship between the lower coil 20 and the upper coil 21, the low voltage region 46 faces the high voltage region 36 with one or more insulating layers 28 interposed therebetween. In the first reference example, as shown in FIG. 4, the lower coil 20 is formed in pairs of two at a position facing the upper coil 21, i.e., in the longitudinal direction of the transformer chip 6. . An inner coil end wiring 49 and an outer coil end wiring 97 are formed between the inner region 31 of the lower coil 20 of each pair and the adjacent lower coils 20, respectively. Thus, in each pair, one lower coil 20 and the other lower coil 20 are electrically connected to each other by a common outer coil end wiring 97 therebetween, and both the lower coil 20 and the outer coil therebetween. The end wiring 97 and the inner coil end wiring 49 in each lower coil 20 are all at the same potential. Therefore, in the insulating layer 28, the inner region 31 of each lower coil 20 and the region between the lower coils 20 in each pair are also within the range covered by the electric field from the lower coil 20, the inner coil end wiring 49 or the outer coil end wiring 97. It is included in the low voltage region 46 as the inside. As shown in FIG. 5, the inner coil end wiring 49 is arranged at a position shifted from the inner coil end wiring 37 on the high voltage side in plan view.

3 to 5, the outer low voltage region 47 is set so as to surround the high voltage region 36 and the low voltage region 46, and the intermediate region 48 is connected to the high voltage region 36 and the low voltage region 46 and the outer low voltage region 46. It is set between the voltage region 47.
As shown in FIGS. 3, 6 and 7, the low voltage pad 13 is formed on the surface of the insulating layer laminated structure 27 (on the interlayer insulating film 30 of the uppermost insulating layer 28) in the outer low voltage region 47. Yes. In the first reference example, six low voltage pads 13 are arranged, one on each side of the six high voltage pads 14 spaced apart from each other in the longitudinal direction of the transformer chip 6. . Each low voltage pad 13 is connected to the lower coil 20 by low voltage wirings 24 and 93 routed in the insulating layer laminated structure 27.

The low voltage wiring 24 includes a through wiring 51 and a lead wiring 52.
The through wiring 51 is formed in a columnar shape that penetrates at least the insulating layer 28 in which the lower coil 20 is formed from each low voltage pad 13 in the outer low voltage region 47 and reaches the insulating layer 28 below the lower coil 20. Yes. More specifically, the through wiring 51 includes island-shaped (rectangular) low-voltage layer wirings 53 and 54 embedded in the same insulating layer 28 as the upper coil 21 and the lower coil 20, respectively, and between them. A plurality of vias 55 to be connected, a via 56 for connecting the upper low-voltage layer wiring 53 and the low-voltage pad 13, and a via 57 for connecting the lower low-voltage layer wiring 54 and the lead-out wiring 52 are included.

  The lead wiring 52 is formed in a linear shape drawn from the low voltage region 46 to the outer low voltage region 47 through the insulating layer 28 below the lower coil 20. More specifically, the lead-out wiring 52 is embedded in the above-described inner coil end wiring 49, the insulating layer 28 below the lower coil 20, and a linear lead-out layer wiring 58 that crosses the lower coil 20 below, A via 59 connecting the lead layer wiring 58 and the inner coil end wiring 49 is included. The lead layer wiring 58 is connected to the semiconductor substrate 26 through a via 86. Thereby, the low voltage wiring 24 is fixed to the substrate voltage (for example, ground voltage).

  The wirings 49, 53, 54, 58 and the vias 55 to 57, 59 are formed by embedding a barrier metal and a Cu wiring material in the wiring groove, like the upper coil 21. As an example, as shown in FIG. 7, the low voltage layer wiring 53 and the vias 55 and 56 are formed by embedding barrier metals 63 to 65 and Cu wiring materials 66 to 68 in the wiring grooves 60 to 62, respectively. . The same material as that of the above-described barrier metal 34 can be applied to the barrier metals 63 to 65.

Although not described in detail, the low voltage wiring 93 is also configured by a wiring including a through wiring (not shown) and a lead wiring 98 (FIGS. 3 to 5), like the low voltage wiring 24. .
With the above configuration, a certain low voltage pad 13 is connected to the inner coil end wiring 49 of the lower coil 20 through the through wiring 51 and the lead wiring 52 as shown in FIGS. Further, the other low voltage pad 13 is connected to the outer coil end wiring 96 of the lower coil 20 through the through wiring and the lead wiring 98 as shown in FIGS. Thereby, a signal input to the low voltage pad 13 can be transmitted to the lower coil 21 through the through wiring 51 and the lead wiring 52.

In the insulating layer laminated structure 27, a shield layer 69 is formed further outside the low voltage wiring 24. This shield layer 69 prevents moisture from entering the device from the outside and cracking of the end face from spreading inside.
As shown in FIGS. 3 to 6, the shield layer 69 is formed in a wall shape along the end face of the transformer chip 6, and is connected to the semiconductor substrate 26 at the bottom thereof. Thereby, shield layer 69 is fixed to the substrate voltage (for example, ground voltage). More specifically, as shown in FIG. 6, the shield layer 69 includes shield layer wirings 70 to 72 embedded in the same insulating layer 28 as the upper coil 21, the lower coil 20, and the lead layer wiring 58, respectively. A plurality of vias 73 connecting them, and a via 74 connecting the lowermost shield layer wiring 72 and the semiconductor substrate 26 are included. The shield layer wirings 70 to 72 and the vias 73 and 74 are formed by embedding a barrier metal and a Cu wiring material in the wiring groove, like the upper coil 21.

  Further, a protective film 75 and a passivation film 76 are sequentially stacked on the entire surface of the insulating layer stacked structure 27 on the insulating layer stacked structure 27. On the passivation film 76, an elliptical annular coil protective film 77 that selectively covers a region immediately above the upper coil 21 is formed. In these films 75 to 77, pad openings 78 and 79 for exposing the low voltage pad 13 and the high voltage pad 14 are formed.

The protective film 75 is made of, for example, SiO ₂ and has a thickness of about 150 nm. The passivation film 76 is made of SiN, for example, and has a thickness of about 1000 nm. The coil protective film 77 is made of polyimide, for example, and has a thickness of about 4000 nm.
Next, details of each part of the transformer chip 6 will be described below.

As described with reference to FIG. 2, a large potential difference (for example, about 1200 V) is generated between the lower coil 20 and the upper coil 21 of the transformer chip 6. Therefore, the insulating layer 28 disposed between the lower coil 20 and the upper coil 21 must have a thickness capable of realizing a withstand voltage that does not cause dielectric breakdown due to the potential difference.
Therefore, in this reference example 1, as shown in FIG. 6, an insulating layer 28 having a laminated structure of an etching stopper film 29 of about 300 nm and an interlayer insulating film 30 of about 2100 nm is provided with a plurality of layers (for example, six layers) between the coils. By interposing them, the total thickness L2 of the insulating layer 28 is set to 12.0 μm to 16.8 μm, thereby realizing vertical DC insulation between the lower coil 20 and the upper coil 21.

  However, when the inventors of this application experimented on the relationship between the thickness of the interlayer film and the surge breakdown voltage in a semiconductor chip including a transformer, the result shown in FIG. 8 was obtained. In FIG. 8, an interlayer film is a film having a structure similar to that of the insulating layer 28 in the first reference example. According to FIG. 8, as the number of interlayer films between the coils is increased and the film thickness is increased, for example, the upper coil 21 and the lower voltage can be reduced despite the fact that the vertical DC insulation is better realized. It can be seen that lateral destruction such as between the pad 13 (between the coil and the pad) and between the upper coil 21 and the shield layer 26 (between the coil and the shield) is dominant.

  Usually, compared to the total thickness L2 of the insulating layer 28 between the lower coil 20 and the upper coil 21, the distance L0 between the upper coil 21 and the outer low voltage region 47 (in this reference example 1, the width of the intermediate region 48). ) Is larger. For example, the distance L0 is generally 100 μm to 450 μm, and is expressed as 6/1 to 40/1 when expressed by the ratio (distance L0 / thickness L2) to the thickness L2. Therefore, for example, a potential difference equivalent to the potential difference between the lower coil 20 and the upper coil 21 (between the high voltage region 36 and the low voltage region 46) is generated between the high voltage region 36 and the outer low voltage region 47. However, if only the distances between these regions are considered, theoretically, the distance L0> the thickness L2, and therefore dielectric breakdown does not occur. However, as evidenced in FIG. 8, the lateral breakdown becomes dominant as the interlayer film between the coils becomes thicker. In FIG. 6, the thickness L2 is shown to be larger than the distance L0, but in reality, the relationship is the distance L0 >> thickness L2.

In this regard, if the inventors of this application provide a shield made of an electrically floating metal member between the high voltage region 36 and the outer low voltage region 47, a specific portion of the outer low voltage region 47 will be described. It was found that the electric field concentration with respect to can be relaxed to prevent lateral breakdown.
Therefore, in the first reference example, as shown in FIGS. 3 and 5, a capacitor 80 that surrounds the high voltage region 36 in a plan view is provided in the intermediate region 48. 3 and 5, the plurality of high voltage regions 36 are surrounded by the common capacitor 80, but each high voltage region 36 may be individually surrounded.

The cross-sectional structure of the capacitor 80 is shown in FIGS. That is, the capacitor 80 is embedded in each of the insulating layer 28 in which the upper coil 21 is embedded, the insulating layer 28 in which the lower coil 20 is embedded, and the insulating layer 28 therebetween, and the coil of the insulating layer 28 as a whole. It is formed in a wall shape surrounding the forming region.
Each capacitor 80 includes a plurality of electrode plates 87 embedded in each insulating layer 28. Three or more electrode plates 87 are provided at equal intervals (five in FIG. 6 and FIG. 7), and each is electrically floating. The electrode plates 87 embedded in each insulating layer 28 are arranged in a row in the vertical direction. That is, when the insulating layer laminated structure 27 is viewed in cross section, the electrode plates 87 constituting a certain capacitor 80 overlap with the upper and lower electrode plates 87. Thus, the plurality of electrode plates 87 embedded in different insulating layers 28 constitute a shield plate without a gap along the stacking direction of the insulating layer stacked structure 27.

As with the upper coil 21, each electrode plate 87 is formed by embedding a barrier metal 82 and a Cu wiring material 83 in the wiring groove 81 as shown in FIG. The same material as that of the barrier metal 34 described above can be applied to the barrier metal 82.
Further, the lateral distance L1 between the upper coil 21 and the capacitor 80 is larger than the total thickness L2 of the insulating layer 28 between the upper coil 21 and the lower coil 20. For example, the distance L1 is 25 μm to 400 μm. In FIG. 6, the thickness L2 is shown to be larger than the distance L1, but in reality, there is a relationship of distance L1 >> thickness L2.

  When a high voltage is applied between the upper coil 21 and the lower coil 20 by the capacitor 80, a low potential conductive portion (for example, the low voltage pad 13, the low voltage layer wiring 53, and the like) disposed in the outer low voltage region 47. The concentration of the electric field on the via 55, the low voltage layer wiring 54, the shield layer 69, etc.) can be mitigated. In particular, the rectangular low-voltage pad 13 and the low-voltage layer wiring 53 arranged in the same layer as the upper coil 21 (high-voltage coil) and in the vicinity of the upper coil 21 are concentrated at the corners, causing surge breakdown. It is easy to happen. However, by arranging the capacitor 80, it is possible to effectively prevent such surge destruction. Moreover, in Reference Example 1, since the capacitor 80 surrounds the high voltage region 36, the electric field emitted from the upper coil 21 is relaxed regardless of the direction. As a result, the breakdown voltage between the high voltage region 36 and the outer low voltage region 37 can be improved.

Further, since the electrode plate 87 constituting the capacitor 80 is embedded in the same insulating layer 28 as the element constituting the shield layer 69, the capacitor 80 and the shield layer 69 can be formed in the same process.
<Modification>
(1) Modifications Regarding Pattern of Capacitor 80 FIGS. 9 to 13 show modifications regarding the pattern of the capacitor 80.

In the configuration of FIG. 9, three or more electrode plates 87 constituting each capacitor 80 are provided at unequal intervals. For example, the plurality of electrode plates 87 are arranged so that the interval increases as the distance from the high voltage region 36 increases.
In the configuration of FIG. 10, the electrode plates 87 embedded in each insulating layer 28 are intermittently arranged along the stacking direction of the insulating layer stacked structure 27. That is, when the insulating layer laminated structure 27 is viewed in cross section, the electrode plate 87 constituting a certain capacitor 80 does not overlap the upper and lower electrode plates 87. For example, as shown in FIG. 10, an electrode plate 87 constituting a certain capacitor 80 may be arranged in a gap region between a plurality of electrode plates 87 constituting the upper and lower capacitors 80.

In the configuration of FIG. 11, the capacitor 80 is selectively embedded in the insulating layer 28 for the upper coil 21 and the insulating layer 28 for the lower coil 20. In other words, the capacitor 80 is embedded only in the insulating layer 28 for the upper coil 21 and the lower coil 20 and may not be embedded in the insulating layer 28 therebetween.
In the configuration of FIG. 12, the capacitor 80 is selectively formed in the intermediate region 48 between the high voltage region 36 and the region (pad region) where the low voltage pad 13 is disposed, and is a region opposite to the pad region. Is not formed. On the other hand, the configuration of FIG. 13 is the opposite, and the capacitor 80 is selectively formed in a region opposite to the pad region and is not formed on the pad region side.
(2) Modified Example Showing Structure Replacing Capacitor 80 FIGS. 14 to 16 are modified examples showing a structure replacing the capacitor 80. Specifically, the case where the electrode plates 87 are provided independently so as not to overlap in the lateral direction in the same insulating layer 28 and the capacitor structure is not provided in each insulating layer 28 is shown.

In the configuration of FIG. 14, the electrode plates 87 embedded in each insulating layer 28 are arranged in a row vertically. On the other hand, in the configuration of FIG. 15, the electrode plates 87 embedded in each insulating layer 28 are intermittently arranged along the stacking direction of the insulating layer stacked structure 27.
Note that the modification shown in this section indicates that the capacitor structure is not formed. Therefore, even if a plurality of electrode plates 87 are provided on the same insulating layer 28, they do not have to overlap in the lateral direction. For example, as shown in FIG. 16, a plurality of electrode plates 87 forming a broken-line ellipse 84 surrounding the high-voltage region 36 are arranged, and a plurality of electrodes constituting the broken-line ellipse 84 are formed in the inner region of the broken-line ellipse 84. The electrode plate 87 may be disposed so as to face the gap area of the plate 87.
(3) Modifications Related to Connection State of Semiconductor Substrate 26 FIGS. 17 to 19 show modification examples related to the connection state of the semiconductor substrate 26.

In the configuration of FIG. 17, the via 86 of FIG. 6 is omitted, and the low voltage wiring 24 is not fixed to the substrate voltage.
In the configuration of FIG. 18, the via 74 of FIG. 6 is omitted, and the shield layer 69 is not fixed to the substrate voltage.
In the configuration of FIG. 19, both the via 86 and the via 74 of FIG. 6 are omitted, and the low voltage wiring 24 and the shield layer 69 are not fixed to the substrate voltage.

Although the first reference example of the present invention has been described above, the present invention can be modified in various ways within the scope of the matters described in the claims.
For example, in Reference Example 1 described above, the case where the high voltage coil is the upper coil 21 and the low voltage coil is the lower coil 20 is shown. However, the high voltage coil is the lower coil 20 and the low voltage coil is the upper coil 21. Also good.

  Further, in the above-described reference example 1, the conductor (low potential portion) that is electrically connected to a potential lower than that of the high voltage coil (upper coil 21) is the same as the low voltage wiring 24 and the shield layer 69. Although only the case where the coil 21 is necessarily formed on the same insulating layer 28 as the embedded insulating layer 28 is taken up, the conductor may not be provided on the same insulating layer 28. For example, the present invention can sufficiently exhibit the effect of reducing the surge breakdown in the lateral direction even for a conductor formed in several layers above or below the insulating layer 28 in which the upper coil 21 is embedded. .

In addition, various design changes can be made within the scope of matters described in the claims.
In addition to the invention described in the claims, the following features can be extracted from the contents of Reference Example 1.
The semiconductor device is disposed around an insulating layer, a high voltage coil and a low voltage coil that are spaced apart from each other in the insulating layer, and a high voltage region for the high voltage coil in a plan view. A low potential portion provided in a low voltage region and connected to a potential lower than that of the high voltage coil, and a metal member disposed between the high voltage coil and the low voltage region and electrically floating. Electric field shield part.

Since the electric field shield portion is provided between the high voltage coil and the low voltage region, the electric field concentration on the low potential portion can be reduced. Thereby, the withstand voltage between the high voltage coil and the low voltage region can be improved.
In the semiconductor device, the electric field shield part includes a capacitor composed of a plurality of electrode plates facing each other at intervals in the lateral direction. In this case, three or more electrode plates may be provided at equal intervals, or three or more electrode plates may be provided at non-equal intervals.

In the semiconductor device, the low potential portion includes a low voltage wiring connected to the low voltage coil.
In the semiconductor device, the low potential portion includes a low voltage pad exposed on a surface of the insulating layer and connected to the low voltage wiring, and the electric field shield portion includes the high voltage coil and the low voltage pad. It is arranged between.

When the low voltage pad has a corner, an electric field concentrates on the corner and the surge breakdown is likely to occur. By arranging the electric field shield part between the high voltage coil and the low voltage pad, it is possible to effectively prevent such surge destruction.
In the semiconductor device, the insulating layer has an insulating film stacked structure including a plurality of insulating films stacked in order, and the high-voltage coil and the low-voltage coil are each embedded in separate insulating films. The one or more insulating films are interposed between the high-voltage coil and the low-voltage coil, and the electric field shield part is composed of an electrode plate embedded in at least one layer of the insulating film.

In this case, a plurality of the electrode plates may be opposed to the same insulating film at intervals, and the plurality of electrode plates may constitute a capacitor. And three or more said electrode plates may be provided at equal intervals, and three or more may be provided at non-equal intervals.
The electrode plates may be provided independently so as not to overlap in the lateral direction in the same insulating film.

  In the semiconductor device, the electrode plate is embedded in the insulating film for the high voltage coil, the insulating film for the low voltage coil, and the insulating film therebetween. In this case, the insulating film between the high voltage coil insulating film and the low voltage coil insulating film may be a plurality of films or a single film. In the case of a plurality of films, the electrode plate may be embedded in all the films, or may be selectively embedded in only a part of the films.

In the semiconductor device, the electrode plates embedded in the insulating films are arranged in a row in the vertical direction.
In the semiconductor device, the electrode plate is selectively embedded in the insulating film for the high voltage coil and the insulating film for the low voltage. That is, the electrode plate is embedded only in the insulating film for the high voltage coil and the low voltage coil, and may not be embedded in the insulating film between them.

In the semiconductor device, the low potential portion includes a shield layer embedded in a plurality of the insulating films so as to surround the high voltage region, and the electrode plate is embedded in the same insulating film as the shield layer. ing. In this configuration, the shield layer and the electric field shield part (electrode plate) can be formed in the same process.
In the semiconductor device, the high voltage coil is an upper coil disposed on the side relatively closer to the surface of the insulating film stack structure, and the low voltage coil is a lower coil disposed below the upper coil. The low potential portion includes a low voltage wiring connected to the lower coil and penetrating through the insulating film stacked structure in the stacking direction.

In the semiconductor device, the low potential portion includes a low voltage pad exposed on a surface of the insulating layer stacked structure and connected to the low voltage wiring.
When the low voltage pad has a corner, an electric field concentrates on the corner and the surge breakdown is likely to occur. By arranging the electric field shield part between the high voltage coil and the low voltage pad, it is possible to effectively prevent such surge destruction.

In the semiconductor device, a lateral distance L1 between the high voltage coil and the electric field shield portion is larger than a vertical distance L2 between the high voltage coil and the low voltage coil.
In the semiconductor device, the electric field shield portion surrounds the high voltage coil. Thereby, the electric field emitted from the high voltage coil is relaxed regardless of the direction.
The semiconductor device includes a substrate that supports the insulating layer, and the low-voltage coil is connected to the substrate.

The semiconductor module includes: the semiconductor device; a low voltage element electrically connected to the low voltage coil of the semiconductor device; a high voltage element electrically connected to the high voltage coil of the semiconductor device; A semiconductor device, a low voltage element, and a resin package for collectively sealing the high voltage element.
The problem (see FIG. 8) that breakdown occurs in the lateral direction when a large potential difference (for example, several thousand volts) occurs between the high voltage region 36 and the outer low voltage region 47 is the following embodiment of the present invention. It can also be solved by the configuration shown in Reference Example 2.
(1) Embodiment of the Invention The embodiment of the present invention is different from the above-described Reference Example 1 in that the capacitor 80 is not provided in the intermediate region 48 as shown in FIGS.

With respect to the problem described with reference to FIG. 8, the inventors of this application have found that the cause of the leakage current that causes the lateral breakdown is related to the constituent material of the insulating film in contact with the upper coil 21.
Therefore, in the embodiment of the present invention, most of the insulating layers 28 are composed of an etching stopper film 29 made of a tensile stress SiN film (Tensile-SiN), and an interlayer insulating film 30 made of a SiO ₂ film having a compressive stress as an internal stress. As for the insulating layer 28 in which the upper coil 21 is embedded and the insulating layer 28 on the upper layer, a compressive stress film having a compressive stress as an internal stress is selectively used as the etching stopper film 29. Adopted. Such a compressive stress film preferably has a compressive stress of 400 MPa to 800 MPa as an internal stress, for example. Specifically, a SiO _x (0 <x <2) film having a larger Si ratio than SiO ₂ is preferable, and a SiN film having a compressive stress (Compressive-SiN) may be used. The SiO _x film can be manufactured by the same manufacturing method as the SiO ₂ film except that the composition ratio of Si is changed by adjusting the flow rate of the source gas. On the other hand, the compressive stress SiN film can be produced by adjusting the conditions such as the SiH ₄ flow rate and the N ₂ flow rate in the manufacturing process of the tensile stress SiN film.

Thereby, it is possible to suppress the leakage current from flowing from the upper coil 21 to the low voltage wiring 24 and the shield layer 69 along the surface direction (lateral direction) of the insulating layer 28. As a result, even if a large potential difference occurs between the upper coil 21, the low voltage wiring 24, and the shield layer 69, dielectric breakdown due to the potential difference can be prevented.
In addition, with respect to the plurality of insulating layers 28 excluding the insulating layer 28 in which a compressive stress film is employed as the etching stopper film 29, an interlayer insulating film 30 made of SiO ₂ having compressive stress and an etching stopper film made of tensile stress SiN film. 29 can be arranged alternately, so that the insulating layer 28 can be laminated while canceling the stress at the lamination interface of the insulating layer laminated structure 27. As a result, in the manufacturing process of the transformer chip 6, it is possible to prevent a large warp deformation from occurring in the semiconductor wafer that is the base of the semiconductor substrate 26 that supports the insulating layer stacked structure 27.

As the etching stopper film 29 for the insulating layer 28 excluding the insulating layer 28 in which the upper coil 21 is embedded, for example, a SiC film, a SiCN film, or the like may be used.
While the embodiments of the present invention have been described above, various design changes can be made in the embodiments of the present invention.
(2) Reference example 2
Regarding the problem described with reference to FIG. 8, the inventors of the present application described that the cause of the leakage current causing lateral breakdown is (1) formation of a heterogeneous interface by contact of different insulating materials on the side of the upper coil 21. And (2) In the manufacturing process of the insulating layer laminated structure 27, the present inventors have found that it is related to the existence of a processing interface damaged by film formation such as CVD.

  Therefore, in Reference Example 2, as shown in FIGS. 25, 27, 28, and 29, the insulating layer 28 in which the upper coil 21 is embedded and the intermediate region 48 in the insulating layer 28 on the upper layer 21 are selectively used. A removal region 110 from which the etching stopper film 29 has been removed is formed. As shown in FIGS. 25 and 27, the removal region 110 is formed in one band shape (for example, 50 μm to 100 μm width) surrounding each high voltage region 36. In particular, as shown in FIGS. 25 and 27, if the shape does not have rounded corners as a whole (substantially elliptical in Reference Example 2), the electric field may not easily concentrate.

Due to the formation of the removal region 110, an interlayer insulating film 30 (SiO ₂ ) on the upper side of the stacked interface 111 in the intermediate region 48 is formed in the stacked interface 111 in contact with the upper coil 21 among the stacked interfaces of the insulating layer stacked structure 27. However, the same kind of interface structure 112 is formed in contact with the lower interlayer insulating film 30 (SiO ₂ ).
Thereby, even if a leakage current flows from the upper coil 21 to the low voltage wiring 24 or the shield layer 69 along the surface direction (lateral direction) of the insulating layer 28, it can be reduced by the homogeneous interface structure 112. That is, the leakage current can be reduced by eliminating a heterogeneous interface due to contact between different insulating materials at least in the intermediate region 48 (contact between SiO ₂ and SiN in Reference Example 2). As a result, even if a large potential difference occurs between the upper coil 21, the low voltage wiring 24, and the shield layer 69, dielectric breakdown due to the potential difference can be prevented.

  Moreover, in Reference Example 2, a trench 113 having the same pattern as the removal region 110 is formed partway in the thickness direction of the interlayer insulating film 30 in the interlayer insulating film 30 on the lower side with respect to the stacked interface 111, and the upper side. The interlayer insulating film 30 is buried in the trench 113 through the removal region 110. Thereby, the distance of the laminated interface 111 from the upper coil 21 to the outer low voltage region 47 can be extended by the depth d of the trench 113. As a result, the leakage current path can be lengthened, so that the leakage current can be satisfactorily reduced even if the processing interface exists at the laminated interface 111.

30A to 30H are cross-sectional views for explaining a process related to the formation of the homogeneous interface structure 112.
In order to form the buried type homogeneous interface structure 112 shown in FIG. 29, for example, as shown in FIG. 30A, a via 55 is formed in the insulating layer 28 below the insulating layer 28 in which the upper coil 21 is buried.

Next, as shown in FIG. 30B, an etching stopper film 29 and a USG film 114 made of SiN are sequentially formed by, eg, plasma CVD.
Next, as shown in FIG. 30C, a photoresist (not shown) is formed on the USG film 114, and the USG film 114, the etching stopper film 29, and the interlayer insulating film 30 are etched in order. Thereby, the removal region 110 and the trench 113 are formed simultaneously.

Next, as shown in FIG. 30D, after the trench 113 is backfilled with SiO ₂ by high density plasma CVD (HDP), SiO ₂ is further deposited by plasma CVD. Thereafter, the surface of SiO ₂ is planarized by CMP. As a result, the insulating layer 28 having the same kind of interface structure 112 is formed in the trench 113.
Next, as shown in FIG. 30E, the upper coil 21, the low voltage layer wiring 53, and the inner coil end wiring 37 are formed in the insulating layer 28 having the same kind of interface structure 112 with the lower insulating layer 28.

Next, as shown in FIG. 30F, an etching stopper film 29 and a USG film 115 made of SiN are sequentially formed by, eg, plasma CVD.
Next, as shown in FIG. 30G, a photoresist (not shown) is formed on the USG film 115, and the USG film 115, the etching stopper film 29, and the interlayer insulating film 30 are sequentially etched. Thereby, the removal region 110 and the trench 113 are formed simultaneously.

Next, as shown in FIG. 30H, after the trench 113 is backfilled with SiO ₂ by high density plasma CVD (HDP), SiO ₂ is further deposited by plasma CVD. Thereafter, the surface of SiO ₂ is planarized by CMP. As a result, the insulating layer 28 having the same kind of interface structure 112 is formed in the trench 113.
Although the reference example 2 has been described above, various design changes can be made in the reference example 2.

For example, as shown in FIG. 31, the same kind of interface structure 112 may be selectively formed only on the lower laminated interface 111 in contact with the lower surface of the upper coil 21, or as shown in FIG. 21 may be selectively formed only on the upper laminated interface 111 in contact with the upper surface of 21.
Further, as shown in FIG. 33, the removal regions 110 may be formed in stripes with a space therebetween. It is preferable that the trench 30 is also formed in a stripe shape in accordance with the striped removal region 110. In this case, the line and space (L / S) of the striped removal region 110 is preferably 1 μm / 1 μm to 10 μm / 10 μm. The striped removed region 110 can be formed by forming a photoresist pattern for etching into a stripe shape in the process shown in FIGS. 30C and 30G.

Further, as shown in FIG. 34, when the upper coil 21 is formed by patterning an Al (aluminum) film instead of the embedded coil of the Cu wiring material 35, the etching stopper 29 is omitted and the insulating layer 28 is made of SiO. _The interlayer insulating film 30 can be formed of only _two . In this configuration, since the same kind of interface structure 112 is formed at all the stacked interfaces of the insulating layer stacked structure 27, the above-described trench 113 is formed to lengthen the path of the leakage current, thereby further reducing the leakage current. Can be obtained effectively.

In addition to the invention described in the claims, the following features can be extracted from the contents of Reference Example 2.
[Claim 1]
An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
Among the plurality of stacked interfaces of the insulating layer stacked structure, the stacked interface where the high-voltage coil is in contact is the same as the insulating layer through the stacked interface in the intermediate region between the high-voltage region and the outer region. A semiconductor device in which a homogeneous interface structure is formed by contact with an insulating material.

According to this configuration, since the homogeneous interface structure is formed at least in the intermediate region, even if a leakage current flows from the high voltage coil toward the conductor, it can be reduced by the homogeneous interface structure. That is, the leakage current can be reduced by eliminating the heterogeneous interface caused by the contact between different insulating materials at least in the intermediate region. Thereby, even if a large potential difference occurs between the high voltage coil and the conductor, it is possible to prevent dielectric breakdown due to the potential difference.
[Section 2]
The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the upper surface to the lower surface of one insulating layer,
The laminated interface in contact with the high voltage coil is formed by an insulating layer in which the high voltage coil is embedded, and an insulating layer that is disposed above and below the upper layer and in contact with the upper surface and the lower surface of the high voltage coil, respectively. Item 2. The semiconductor device according to Item 1, comprising an interface.
[Section 3]
In the homogeneous interface structure, a trench is formed in a relatively lower insulating layer, and an upper insulating layer in contact with an upper surface of the lower insulating layer is formed so as to be embedded in the trench. 3. The semiconductor device according to 1 or 2.

According to this configuration, the interface distance from the high voltage coil to the outer region can be extended by the depth of the trench. As a result, the leakage current path can be lengthened, so that the leakage current can be further reduced.
[Claim 4]
Each insulating layer of the insulating layer laminated structure has a laminated structure of a thin film made of a first insulating material and an interlayer insulating film made of a second insulating material formed on the thin film,
The insulating layer on the upper side of the laminated interface with which the high voltage coil is in contact has a removal region in which the thin film is selectively removed in the intermediate region,
The interlayer insulating film of the upper insulating layer is in contact with the interlayer insulating film of the lower insulating layer with respect to the stack interface through the removal region to form the same kind of interface structure, or 2. The semiconductor device according to 2.
[Section 5]
In the homogeneous interface structure, a trench having the same pattern as the removal region is formed in the interlayer insulating film of the lower insulating layer, and the interlayer insulating film of the upper insulating layer is interposed through the removal region. Item 5. The semiconductor device according to Item 4, which is formed so as to be embedded in the trench.

According to this configuration, the interface distance from the high voltage coil to the outer region can be extended by the depth of the trench. As a result, the leakage current path can be lengthened, so that the leakage current can be further reduced.
[Claim 6]
Item 6. The semiconductor device according to Item 4 or 5, wherein the removal region is formed in a single band shape.
[Claim 7]
Item 7. The semiconductor device according to Item 6, wherein a width of the strip-shaped removal region is 50 μm to 100 μm.
[Section 8]
Item 6. The semiconductor device according to Item 4 or 5, wherein the removal region is formed in a stripe shape with a space between each other.

Particularly, in item 8, in the homogeneous interface structure, a stripe trench having the same pattern as the stripe-shaped removal region is formed in the interlayer insulating film of the lower insulating layer, and the interlayer of the upper insulating layer is formed. It is preferable that an insulating film is formed so as to be embedded in the stripe trench through the removal region. As a result, the interface distance from the high voltage coil to the outer region can be further increased, so that the leakage current can be further reduced.
[Claim 9]
Item 9. The semiconductor device according to Item 8, wherein a line and space (L / S) of the striped removal region is 1 μm / 1 μm to 10 μm / 10 μm.
[Section 10]
Item 10. The semiconductor device according to any one of Items 4 to 9, wherein the thin film is made of a SiN film, and the interlayer insulating film is made of a SiO ₂ film.
[Section 11]
Item 11. The semiconductor device according to any one of Items 1 to 10, wherein the conductor includes a conductor layer formed on the same insulating layer as the high-voltage coil.
[Claim 12]
A high-voltage pad formed on the surface of the insulating layer stacked structure in the high-voltage region;
A low voltage pad formed on the surface of the insulating layer stack structure in the outer region,
The high voltage coil is an upper coil disposed on a side relatively closer to the surface of the insulating layer laminated structure, and the low voltage coil is a lower coil disposed below the upper coil,
Item 12. The electrical conductor according to any one of Items 1 to 11, wherein the conductor includes a low voltage wiring that penetrates the plurality of insulating layers downward from the low voltage pad in a thickness direction and is electrically connected to the lower coil. The semiconductor device described.

According to this configuration, since the breakdown voltage structure (dielectric breakdown prevention structure) is formed, a low-voltage wiring for contacting the lower coil can be formed through the insulating layer laminated structure. Accordingly, both the high voltage pad and the low voltage pad can be formed on the surface of the insulating layer laminated structure, and wire bonding to the pad can be easily performed.
[Claim 13]
Item 13. The semiconductor device according to Item 12, wherein the low-voltage wiring further includes a lead-out wire led out from the coil end inside the lower coil to the outer region via the insulating layer below the lower coil.
[Section 14]
The high voltage pad is disposed above a central portion of the upper coil,
Item 14. The semiconductor device according to Item 12 or 13, further comprising a high-voltage wiring that penetrates the insulating layer upward in the thickness direction from a coil end inside the upper coil and is connected to the high-voltage pad.
[Section 15]
The electrical conductor includes a shield layer formed so as to penetrate the plurality of insulating layers downward in the thickness direction so as to surround the high voltage region, further outside the low voltage wiring. The semiconductor device as described in any one.
[Section 16]
Any one of Items 1 to 15, wherein a distance L0 between the high voltage coil and the conductor is larger than a thickness L2 of the insulating layer between the high voltage coil and the low voltage coil. The semiconductor device according to one item.
[Section 17]
Item 18. The semiconductor device according to Item 16, wherein a ratio of the thickness L2 to the distance L0 (distance L0 / thickness L2) is 6/1 to 40/1.
[Section 18]
Item 18. The semiconductor device according to Item 16 or 17, wherein the thickness L2 is 12.0 μm to 16.8 μm, and the distance L0 is 100 μm to 450 μm.
[Section 19]
The semiconductor device according to any one of Items 1 to 18,
A low voltage element electrically connected to the low voltage coil of the semiconductor device;
A high voltage element electrically connected to the high voltage coil of the semiconductor device;
A semiconductor module comprising: the semiconductor device; a resin package that collectively seals the low-voltage element and the high-voltage element.

According to this configuration, since the semiconductor device according to any one of Items 1 to 18 is provided, a highly reliable transformer module that hardly causes dielectric breakdown can be realized.
As described above, the embodiment of the present invention, Reference Example 1 and Reference Example 2 are provided between the high voltage region and the low voltage region that are spaced apart in the direction along the surface of the insulating layer (lateral direction). This is common in that it is an issue to prevent dielectric breakdown. These forms each solve the problem by providing structures A to C for preventing breakdown between the high voltage region and the low voltage region.

Reference Example 1 shows a structure A: an electric field shield part made of an electrically floating metal member (preferably, the electric field shield part is a capacitor made up of a plurality of electrode plates facing each other at intervals in the lateral direction). As an example, a capacitor 80 is disclosed. Embodiments of the present invention, the structure B: provided in contact with the high voltage region, as an example of the compressive stress film having a compressive stress as the internal stress, SiO x ₍₀ ratio of Si is larger than the SiO _{2 <x} <2) Disclose the insulating layer 28 made of a SiN film having a compressive stress. Reference Example 2 discloses structure C: homogeneous interface structure 112 made of SiO ₂ / SiO ₂ as an example of homogeneous interface structure formed by contacting insulating layers made of the same insulating material.

  These structures A to C may be employed alone, but can be further increased in pressure resistance by being combined with each other. For example, all of the structures A to C may be provided between the high voltage region and the low voltage region, or a combination of the structures A and B, a combination of the structures A and C, and a combination of the structures A and C are provided. It may be. As an example of the combination of the structures A and B, in FIG. 6, an etching stopper film 29 (compressive stress film) having compressive stress selectively with respect to the insulating layer 28 in which the upper coil 21 is embedded and the insulating layer 28 on the upper layer. ). As an example of the combination of the structures A and C, in FIG. 6, the same kind of interface structure 112 is provided between the capacitor 80 and the high voltage region 36 or between the outer low voltage region 47 and the capacitor 80. Good.

  Moreover, the components grasped | ascertained from the indication of each above-mentioned figure can be mutually combined also in a different figure.

DESCRIPTION OF SYMBOLS 1 Semiconductor module 2 Resin package 5 Controller chip 6 Transformer chip 7 Driver chip 13 Low voltage pad 14 High voltage pad 20 Lower coil 21 Upper coil 22 Inner coil end 23 Inner coil end 24 Low voltage wiring 25 High voltage wiring 26 Semiconductor substrate 27 Insulation Layer laminated structure 28 Insulating layer 29 Etching stopper film 30 Interlayer insulating film 31 Inner region 32 Inner region 33 Coil groove 35 Cu wiring material 36 High voltage region 37 Inner coil end wiring 46 Low voltage region 47 Outer low voltage region 48 Intermediate region 49 Inner coil end wiring 51 Through wiring 52 Lead-out wiring 69 Shield layer 80 Capacitor 87 Electrode plate 110 Removal region 111 Laminated interface 112 Similar interface structure 113 Trench

Claims (29)

An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
The insulating layer in contact with the high voltage coil, viewed including the compressive stress film having a compressive stress as the internal stress in the contact portion between the high-voltage coil,
The compressive stress film, _SiO x ratio of Si is larger than the _{SiO 2 (0 <x <2} ) film including a semiconductor device. The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the upper surface to the lower surface of one insulating layer,
The insulating layer in contact with the high voltage coil includes an insulating layer in which the high voltage coil is embedded, and insulating layers that are disposed above and below the insulating layer and in contact with the upper surface and the lower surface of the high voltage coil, respectively. Item 14. The semiconductor device according to Item 1. The compressive stress film has a compressive stress of 400MPa~800MPa as internal stress, the semiconductor device according to claim 1 or 2. Each of the insulating layers has a laminated structure of a thin film and an interlayer insulating film made of SiO ₂ formed on the thin film,
The thin film of the insulating layer in contact with the high voltage coil is selectively formed of the compressive stress film;
The thin film of the other of the insulating layer except for the insulating layer in contact with the high voltage coil is formed by the tensile stress film having a tensile stress as the internal stress, according to any one of claims 1 to 3 Semiconductor device.   An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
  A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
  A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
  The insulating layer in contact with the high voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high voltage coil,
The compressive stress film is a semiconductor device including a compressive stress SiN film.   The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the upper surface to the lower surface of one insulating layer,
  The insulating layer in contact with the high voltage coil includes an insulating layer in which the high voltage coil is embedded, and insulating layers that are disposed above and below the insulating layer and in contact with the upper surface and the lower surface of the high voltage coil, respectively. Item 6. The semiconductor device according to Item 5.   The semiconductor device according to claim 5, wherein the compressive stress film has a compressive stress of 400 MPa to 800 MPa as an internal stress.   Each of the insulating layers includes a thin film and SiO formed on the thin film. ₂ It consists of a laminated structure with an interlayer insulating film consisting of
  The thin film of the insulating layer in contact with the high voltage coil is selectively formed of the compressive stress film;
  The thin film of the said other insulating layer except the said insulating layer which contact | connects the said high voltage coil is formed with the tensile stress film | membrane which has a tensile stress as an internal stress, It is any one of Claims 5-7. Semiconductor device.   An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
  A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
  A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
  The insulating layer in contact with the high voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high voltage coil,
  The compressive stress film is a semiconductor device having a compressive stress of 400 MPa to 800 MPa as an internal stress.   The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the upper surface to the lower surface of one insulating layer,
  The insulating layer in contact with the high voltage coil includes an insulating layer in which the high voltage coil is embedded, and insulating layers that are disposed above and below the insulating layer and in contact with the upper surface and the lower surface of the high voltage coil, respectively. Item 10. The semiconductor device according to Item 9.   Each of the insulating layers includes a thin film and SiO formed on the thin film. ₂ It consists of a laminated structure with an interlayer insulating film consisting of
  The thin film of the insulating layer in contact with the high voltage coil is selectively formed of the compressive stress film;
  11. The semiconductor device according to claim 9, wherein the thin film of the insulating layer other than the insulating layer in contact with the high voltage coil is formed of a tensile stress film having a tensile stress as an internal stress.   An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
  A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
  A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
  The insulating layer in contact with the high voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high voltage coil,
  Each of the insulating layers includes a thin film and SiO formed on the thin film. ₂ It consists of a laminated structure with an interlayer insulating film consisting of
  The thin film of the insulating layer in contact with the high voltage coil is selectively formed of the compressive stress film;
  The semiconductor device, wherein the thin film of the insulating layer other than the insulating layer in contact with the high voltage coil is formed of a tensile stress film having a tensile stress as an internal stress.   The high voltage coil includes an embedded coil embedded in a coil groove penetrating from the upper surface to the lower surface of one insulating layer,
  The insulating layer in contact with the high voltage coil includes an insulating layer in which the high voltage coil is embedded, and insulating layers that are disposed above and below the insulating layer and in contact with the upper surface and the lower surface of the high voltage coil, respectively. Item 13. A semiconductor device according to Item 12. The conductor comprises said high voltage conductor layer formed on the same said insulating layer and the coil, the semiconductor device according to any one of claims 1 to 13. A high-voltage pad formed on the surface of the insulating layer stacked structure in the high-voltage region;
A low voltage pad formed on the surface of the insulating layer stack structure in the outer region,
The high voltage coil is an upper coil disposed on a side relatively closer to the surface of the insulating layer laminated structure, and the low voltage coil is a lower coil disposed below the upper coil,
The conductor, the passing from the low voltage pad a plurality of the insulating layer in the thickness direction downwards, including low voltage wiring electrically connected to the lower coil, any one of claims 1 to 14 A semiconductor device according to 1. The semiconductor device according to claim 15 , wherein the low-voltage wiring includes a lead-out wiring led out from a coil end inside the lower coil to the outer region via the insulating layer below the lower coil. The high voltage pad is disposed above a central portion of the upper coil,
17. The semiconductor device according to claim 15 , further comprising a high-voltage wiring that penetrates the insulating layer upward in the thickness direction from a coil end inside the upper coil and is connected to the high-voltage pad. The conductor, the at further outside than the low voltage lines, comprising a shield layer formed through a plurality of the insulating layer in the thickness direction downwards so as to surround the high-voltage region, claim 15 to 17 The semiconductor device according to any one of the above.   An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
  A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
  A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
  The insulating layer in contact with the high voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high voltage coil,
  A high-voltage pad formed on the surface of the insulating layer stacked structure in the high-voltage region;
  A low voltage pad formed on the surface of the insulating layer stack structure in the outer region,
  The high voltage coil is an upper coil disposed on a side relatively closer to the surface of the insulating layer laminated structure, and the low voltage coil is a lower coil disposed below the upper coil,
  The semiconductor device includes a low voltage wiring that penetrates the plurality of insulating layers downward in the thickness direction from the low voltage pad and is electrically connected to the lower coil.   The semiconductor device according to claim 19, wherein the low-voltage wiring includes a lead-out wiring led out from a coil end inside the lower coil to the outer region via the insulating layer below the lower coil.   The high voltage pad is disposed above a central portion of the upper coil,
  21. The semiconductor device according to claim 19, further comprising a high-voltage wiring that penetrates the insulating layer upward in the thickness direction from a coil end inside the upper coil and is connected to the high-voltage pad.   The conductor includes a shield layer formed so as to penetrate the plurality of insulating layers downward in the thickness direction so as to surround the high voltage region on the outer side of the low voltage wiring. The semiconductor device according to any one of the above. Wherein relative to the thickness L2 of the insulating layer between the low voltage coil and the high voltage coil, the larger the distance L0 between the conductor and the high voltage coil, any claim 1 to 22 The semiconductor device according to claim 1. 24. The semiconductor device according to claim 23 , wherein a ratio of the thickness L2 to the distance L0 (distance L0 / thickness L2) is 6/1 to 40/1. 25. The semiconductor device according to claim 23 , wherein the thickness L2 is 12.0 μm to 16.8 μm, and the distance L0 is 100 μm to 450 μm.   An insulating layer laminated structure composed of a plurality of insulating layers laminated in order;
  A high-voltage coil and a low-voltage coil that are formed in the insulating layers different from each other in the insulating layer stacked structure and face each other with one or more insulating layers interposed therebetween;
  A conductor formed on a lateral outer region of the high voltage region where the high voltage coil is disposed, and electrically connected to a lower potential than the high voltage coil;
  The insulating layer in contact with the high voltage coil includes a compressive stress film having a compressive stress as an internal stress at a contact portion with the high voltage coil,
  The semiconductor device, wherein a distance L0 between the high voltage coil and the conductor is larger than a thickness L2 of the insulating layer between the high voltage coil and the low voltage coil.   27. The semiconductor device according to claim 26, wherein a ratio of the thickness L2 to the distance L0 (distance L0 / thickness L2) is 6/1 to 40/1.   28. The semiconductor device according to claim 26, wherein the thickness L2 is 12.0 μm to 16.8 μm, and the distance L0 is 100 μm to 450 μm. A semiconductor device according to any one of claims 1 to 28 ;
A low voltage element electrically connected to the low voltage coil of the semiconductor device;
A high voltage element electrically connected to the high voltage coil of the semiconductor device;
A semiconductor module comprising: the semiconductor device; a resin package that collectively seals the low-voltage element and the high-voltage element.

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