JP2014022600A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve creeping dielectric strength voltage without increasing an occupied area of the whole isolator including an insulation region.SOLUTION: A semiconductor integrated circuit 10 comprises: a first voltage operation circuit 30 which operates at a first voltage; a second voltage operation circuit 40 which operates at a second voltage different from the first voltage; insulators 18 through 22 for insulating the first voltage operation circuit 30 and the second voltage operation circuit 40 from each other. On the insulators 20 through 22, a plurality of odd-shaped patterns 25 are formed.

Description

  The present invention relates to a semiconductor integrated circuit, and can be suitably used for, for example, a semiconductor integrated circuit including an isolator element for performing data communication between circuits having greatly different operating voltages.

  In an isolator that performs data communication between circuits with significantly different voltage levels, it is necessary to simultaneously secure both the withstand voltage between insulating elements and the withstand voltage through the surface of the insulating film (creeping withstand voltage). is there. In order to ensure the creeping withstand voltage, it is necessary to increase the creeping distance between the insulating elements. Therefore, downsizing of a device incorporating an insulating element has been hindered.

  When an isolator is configured in a semiconductor integrated circuit, insulating elements formed of metal wiring are isolated by an insulating film. Generally, a transformer inductor or a capacitor plate is used as an insulating element. A signal is transmitted between the insulating elements while being electrically insulated (that is, not connected in a direct current) between the insulating elements by magnetic coupling or capacitive coupling between the insulating elements. In general, the insulating element faces the stacking direction of the semiconductor integrated circuit. The isolation voltage of the isolator is determined by the breakdown voltage per unit size of the insulating film and the isolation distance between the insulating elements. Isolation distances include spatial distances and creepage distances. Dielectric breakdown may occur in paths corresponding to the clearance distance and creepage distance, respectively. The spatial distance is the shortest distance between insulating elements via an insulating film. The withstand voltage in the path corresponding to the spatial distance is the product of the withstand voltage per unit thickness of the insulating film and the spatial distance. The creepage distance is the shortest distance between the insulating elements along the surface of the insulating film (the surface facing the space or the bonding interface with another insulating film). In the vicinity of the surface of the insulating film, the density of the insulating material is low, or a low-resistance path is formed by impurities or process residues. Therefore, the withstand voltage in the path corresponding to the creepage distance is the product of the withstand voltage per unit length of the surface of the insulating film and the creepage distance. The withstand voltage per unit length of the surface of the insulating film is much lower and the variation is larger than the withstand voltage per unit thickness of the insulating film.

  As an example, consider a semiconductor chip in which a first electrode plate of a capacitor is provided under a polyimide film, and a second electrode plate of the capacitor and a pad connected to the first electrode plate are provided on the polyimide film. In this case, the spatial distance is the film thickness of the polyimide film, and the creepage distance is the shortest distance between the second electrode plate and the pad along the upper surface of the polyimide film. When the withstand voltage required for the capacitor is 5 kV, the typical withstand voltage of polyimide is 0.25 kV / μm, so the required spatial distance is 20 μm. On the other hand, assuming that the withstand voltage per unit length of the laminated interface of the polyimide film is 1/10 of the withstand voltage of polyimide, the necessary creepage distance is 200 μm. Therefore, it is difficult to reduce the size of the device incorporating the first electrode plate and the second electrode plate while ensuring the creeping withstand voltage between the pad connected to the first electrode plate and the second electrode plate.

  Patent document 1 (Japanese translations of PCT publication No. 2010-536180) is disclosing the device by which adhesion | attachment and fracture toughness are improved. The device includes a first dielectric layer having a corrugated top surface and a second dielectric layer disposed on the first dielectric layer and having a complementary corrugated surface.

  Japanese Patent Application Laid-Open No. 2007-123779 discloses a Cu wiring film structure in which a barrier insulating film is provided on a Cu wiring film, a barrier metal film, and an inter-wiring insulating film. A step is formed between the lower surface of the barrier insulating film on the Cu wiring film and / or the barrier metal film and the lower surface of the barrier insulating film on the inter-wiring insulating film.

  Patent Document 3 (Japanese Patent Laid-Open No. 2003-303939) discloses a power semiconductor device. A prescribed insulating creepage distance is secured by the convex wall and the concave portion provided between the terminals of the power semiconductor device.

  Patent Document 4 (Japanese Patent Laid-Open No. 2001-358321) discloses a two-dimensional image detector. The two-dimensional image detector includes a pixel electrode, a conversion layer formed on the pixel electrode, a common electrode provided on the conversion layer, and a power source that applies a voltage between the common electrode and the ground. The conversion layer absorbs light or radiation and generates electron-hole pairs. An uneven surface that increases the creeping distance between the common electrode and the ground to improve the withstand voltage is formed on the conversion layer.

Special table 2010-536180 gazette JP 2007-123779 A JP 2003-303939 A JP 2001-358321 A

  There is a need to improve the creeping withstand voltage without increasing the occupied area of the entire isolator including the insulating region.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In a semiconductor integrated circuit according to an embodiment, a plurality of uneven patterns are formed on an insulator that insulates circuits that operate at different voltages.

  In a method for manufacturing a semiconductor integrated circuit according to another embodiment, a plurality of concave and convex patterns are formed on an insulator that insulates circuits that operate at different voltages.

  According to the embodiment, the creeping withstand voltage between circuits operating at different voltages can be improved without increasing the occupied area of the entire isolator including the insulating region.

FIG. 1 is a circuit diagram of the motor control device according to the first embodiment. FIG. 2 is a schematic diagram illustrating an example of the semiconductor package according to the first embodiment. FIG. 3 is a schematic diagram illustrating another example of the semiconductor package according to the first embodiment. FIG. 4 is a schematic diagram illustrating an example of a printed wiring board assembly according to the first embodiment. FIG. 5 is a schematic view showing another example of the printed wiring board assembly according to the first embodiment. FIG. 6 is a cross-sectional view of the semiconductor chip according to the first embodiment. FIG. 7 is a conceptual diagram showing the distance T, distance L, groove depth H, and groove pitch P in the semiconductor chip according to the first embodiment. FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor chip according to the first embodiment. FIG. 9 is a top view of the semiconductor chip according to the first embodiment. FIG. 10 is a top view of the semiconductor chip according to the first embodiment when the insulating element is an inductor. FIG. 11 is a top view of the semiconductor chip according to the second embodiment. FIG. 12 is a top view of a semiconductor chip according to another example of the second embodiment. FIG. 13 is a cross-sectional view of a semiconductor chip according to the third embodiment. FIG. 14 is a conceptual diagram showing the distance T, the distance x, and the groove depth H (x) in the semiconductor chip according to the third embodiment. FIG. 15A is a cross-sectional view showing the manufacturing process of the semiconductor chip according to the third embodiment. FIG. 15B is a cross-sectional view showing the manufacturing process of the semiconductor chip according to the third embodiment. FIG. 15C is a cross-sectional view showing the manufacturing process of the semiconductor chip according to the third embodiment. FIG. 16 is a cross-sectional view of a semiconductor chip according to the fourth embodiment. FIG. 17 is a schematic diagram illustrating an example of a printed wiring board assembly according to the fifth embodiment. FIG. 18 is a cross-sectional view of a semiconductor chip according to the fifth embodiment. FIG. 19 is a top view of the semiconductor chip according to the sixth embodiment. FIG. 20 is a cross-sectional view of a semiconductor chip according to the seventh embodiment.

  With reference to the attached drawings, embodiments for carrying out a semiconductor integrated circuit and a method for manufacturing the semiconductor integrated circuit will be described below.

(First embodiment)
FIG. 1 is a circuit diagram of a motor control device to which the semiconductor integrated circuit according to the first embodiment is applied. The motor control device includes a microcontroller 1, an isolator 2, a gate driver 6, and a transistor 7. The motor 8 controlled by the motor control device includes three coils connected in a loop and a rotor (not shown). Two transistors 7 are provided corresponding to nodes between adjacent coils. The transistor 7 is, for example, an IGBT (Insulated Gate Bipolar Transistor). One transistor 7 is used to supply a power supply potential to the node, and the other transistor 7 is used to supply a ground potential to the node. One gate driver 6 and one isolator 2 are provided corresponding to one transistor 7. The isolator 2 includes a transmission circuit 3, an isolator element 4, and a reception circuit 5. The isolator element 4 is, for example, a capacitor or a transformer. The transmission circuit 3 is connected to the microcontroller 1. The transmission circuit 3 is connected to the reception circuit 5 via the isolator element 4. The receiving circuit 5 is connected to the gate driver 6. The gate driver 6 is connected to the gate of the transistor 7. The microcontroller 1, the transmission circuit 3, and a part of the isolator element 4 form a circuit that operates at a low voltage (for example, 5V). The other part of the isolator element 4, the receiving circuit 5, the gate driver 6, the transistor 7, and the motor 8 form a circuit that operates at a high voltage (for example, 1 kV). The isolator 2 electrically isolates a circuit that operates at a low voltage from a circuit that operates at a high voltage (without connecting these circuits in a direct current manner), and outputs a control signal output from the microcontroller 1 to the gate driver 6. introduce. The gate driver 6 controls on / off of the transistor 7 based on the control signal. By turning on / off a total of six transistors 7, the three coils of the motor 8 generate a rotating magnetic field, and the rotor rotates by the rotating magnetic field. The microcontroller 1 may be connected to a peripheral device (not shown) or a console (not shown).

  FIG. 2 shows an example of a semiconductor package according to this embodiment. The semiconductor package 121 includes a semiconductor chip 101, a semiconductor chip 102, and a resin 22 that molds the semiconductor chips 101 and 102. The semiconductor chip 101 includes a transmission circuit 3 and an isolator element 4. The semiconductor chip 102 includes a receiving circuit 5. The isolator element 4 and the receiving circuit 5 are connected via a bonding wire.

  FIG. 3 shows another example of the semiconductor package according to the present embodiment. The semiconductor package 122 includes a semiconductor chip 103, a semiconductor chip 104, and a resin 22 that molds the semiconductor chips 103 and 104. The semiconductor chip 103 includes a transmission circuit 3. The semiconductor chip 104 includes an isolator element 4 and a receiving circuit 5. The transmission circuit 3 and the isolator element 4 are connected via a bonding wire.

  FIG. 4 shows an example of a printed wiring board assembly according to the present embodiment. The printed wiring board assembly 141 includes a semiconductor package 123, a semiconductor package 124, and a printed wiring board 131 on which the semiconductor packages 123 and 124 are mounted. The semiconductor package 123 includes a semiconductor chip 105, a semiconductor chip 102, and a resin 22 that molds the semiconductor chips 105 and 102. The semiconductor chip 105 includes a microcontroller 1, a transmission circuit 3, and an isolator element 4. The receiving circuit 5 of the semiconductor chip 102 and the isolator element 4 are connected via a bonding wire. The semiconductor package 124 includes a semiconductor chip 106 and a resin 22 that molds the semiconductor chip 106. The semiconductor chip 106 includes a gate driver 6.

  FIG. 5 shows another example of the printed wiring board assembly according to the present embodiment. The printed wiring board assembly 142 includes a semiconductor package 125, a semiconductor package 126, and a printed wiring board 132 on which the semiconductor packages 125 and 126 are mounted. The semiconductor package 125 includes a semiconductor chip 107 and a resin 22 that molds the semiconductor chip 107. The semiconductor chip 107 includes the microcontroller 1 and the transmission circuit 3. The semiconductor package 126 includes a semiconductor chip 108 and a resin 22 that molds the semiconductor chip 108. The semiconductor chip 108 includes the isolator element 4, the receiving circuit 5, and the gate driver 6. The transmission circuit 3 and the isolator element 4 are connected via a bonding wire.

  FIG. 6 shows a cross-sectional view of the semiconductor chip 10. The semiconductor chip 10 is a semiconductor chip 101, 104, 105, or 108. The first voltage operation circuit 30 that operates at the first voltage includes an insulating element 31, a pad 32, a bonding wire 33, and a circuit 34. The insulating element 31 is connected to the pad 32 via the circuit 34. The bonding wire 33 is connected to the pad 32. The second voltage operation circuit 40 that operates at a second voltage different from the first voltage includes an insulating element 41, a pad 42, and a bonding wire 43. The pad 42 is connected to the insulating element 41. The bonding wire 43 is connected to the pad 42.

  The semiconductor chip 10 includes a substrate 11, interlayer insulating films 12 to 17, insulating films 20 to 21, an insulating element 31, a pad 32, a circuit 34, an insulating element 41, and a pad 42. The interlayer insulating films 12 to 17 and the insulating films 20 to 21 are sequentially stacked on the substrate 11. The insulating element 31 and the circuit 34 are formed in the interlayer insulating films 13 to 17 as internal wiring. The pad 32, the insulating element 41, and the pad 42 are formed on the insulating films 20 to 21 as additional wiring (rewiring). The interlayer insulating films 12 to 17 are, for example, silicon oxide films (SiO2 films). The interlayer insulating films 12 to 17 are insulating films. The insulating films 20 to 21 are, for example, polyimide films. The insulating elements 31 and 41 form a transformer or a capacitor as the isolator element 4. The insulating elements 31 and 41 are, for example, a pair of electrode plates or inductors (coils). The circuit 34 includes the transmission circuit 3, the reception circuit 5, both the microcontroller 1 and the transmission circuit 3, or both the reception circuit 5 and the gate driver 6.

  The insulating element 31 is formed in the interlayer insulating film 17. An insulating film 20 is formed on the insulating element 31 and the interlayer insulating film 17. A pad 32, an insulating element 41, and a pad 42 are formed on the insulating film 20. The insulating element 41 is provided so as to face the insulating element 31 with the insulating film 20 interposed therebetween. An insulating film 21 is formed on the pad 32, the insulating element 41, the pad 42, and the insulating film 20. The portion of the pad 32 not covered with the insulating film 21, the portion of the pad 42 not covered with the insulating film 21, the insulating film 21, the bonding wire 33, and the bonding wire 43 are covered with the resin 22.

  A plurality of concavo-convex patterns parallel to each other are formed on the insulators 20 to 22 that insulate the first voltage operation circuit 30 and the second voltage operation circuit 40 from each other. On the upper surface 20a of the insulating film 20, a plurality of concavo-convex patterns 25 parallel to each other are formed. A plurality of concavo-convex patterns complementary to the plurality of concavo-convex patterns 25 are formed on the lower surface of the insulating film 21. A plurality of concavo-convex patterns are also formed at positions above the plurality of concavo-convex patterns 25 at the interface between the insulating film 21 and the resin 22.

Referring to FIG. 7, the plurality of concavo-convex patterns 25 parallel to each other are formed as a plurality of groove patterns 25 parallel to each other. A symbol L indicates a distance between the insulating element 41 and the pad 32. A symbol T indicates the film thickness of the insulating film 20. The symbol H indicates the groove depth of the plurality of groove patterns 25. The symbol P indicates the groove pitch of the plurality of groove patterns 25. When the number of groove patterns included in the plurality of groove patterns 25 is N, the creepage distance CD between the first voltage operation circuit 30 and the second voltage operation circuit 40 is expressed by the following formula:
CD = L + 2NH (1)
It is represented by When the plurality of groove patterns 25 are provided in the entire region between the insulating element 41 and the pad 32, the creeping distance CD is expressed by the following formula:
CD = L (1 + 2H / P) (2)
It is represented by When the groove depth H is 1 μm and the groove pitch P is 2 μm, the creepage distance CD is twice the distance L from the equation (2).

  As described above, according to the present embodiment, the creeping distance between the first voltage operation circuit 30 and the second voltage operation circuit 40 is increased by a plurality of uneven patterns parallel to each other. Therefore, the creeping withstand voltage between circuits operating at different voltages can be improved without increasing the occupied area of the entire isolator including the insulating region. In other words, the size of the semiconductor chip 10 can be reduced while ensuring the creeping withstand voltage.

According to equation (1), the creepage distance CD increases as the groove depth H increases and the number N of groove patterns increases. However, when the groove depth H is increased, the effective film thickness ET of the insulating film 20 is decreased, and conversely, the withstand voltage via the insulating film 20 may be deteriorated. The effective film thickness ET is:
ET = TH (3)
It is represented by Therefore, it is preferable to provide a large number of groove patterns having a small groove depth H.

  A method for manufacturing a semiconductor integrated circuit will be described. A first voltage operation circuit 30 is formed. A second voltage operation circuit 40 is formed. Insulators 20 to 22 that insulate the first voltage operation circuit 30 and the second voltage operation circuit 40 from each other are formed. A plurality of concavo-convex patterns parallel to each other are formed on the insulators 20 to 22.

  Referring to FIG. 8, after forming insulating element 31 and circuit 34, insulating film 20 is formed. A pad 32, an insulating element 41, and a pad 42 are formed on the insulating film 20. A plurality of groove patterns 25 parallel to each other are formed on the upper surface 20 a of the insulating film 20. The plurality of groove patterns 25 are formed above the circuit 34, for example. The plurality of groove patterns 25 can be formed by etching or exposure. Thereafter, when the insulating film 21 is formed on the insulating film 20, a plurality of concave and convex patterns are formed on the upper surface of the plurality of groove patterns 25 on the upper surface of the insulating film 21. When the insulating film 21 is covered with the resin 22, a complementary uneven pattern is formed on the joint surface with the resin 22. The plurality of groove patterns 25 can be confirmed by observing the cross section of the semiconductor chip 10 with an optical microscope. When the compositions of the insulating film 20 and the insulating film 21 are the same, it may be difficult to directly confirm the plurality of groove patterns 25. Presence can be inferred. Although the case where the plurality of groove patterns 25 on the upper surface 20a of the insulating film 20 are reflected on the upper surface of the insulating film 21 has been described here, an uneven pattern may be formed on the upper surface of the insulating film 21 by etching or the like. In this case, the positions of the concave / convex pattern on the upper surface 20a of the insulating film 20 and the concave / convex pattern on the upper surface of the insulating film 21 may be shifted.

  Referring to FIG. 9, the plurality of groove patterns 25 are formed in a region between pad 32 and insulating element 41 on upper surface 20 a of insulating film 20. The plurality of groove patterns 25 are formed so as to intersect with the line segment connecting the pad 32 and the insulating element 41 when viewed from the thickness direction of the insulating film 20 (viewed from the opposing direction of the insulating elements 31 and 41). .

In FIG. 9, the insulating element 41 is shown as an electrode plate. When the insulating element 41 is an electrode plate, the insulating element 31 is also an electrode plate.
As shown in FIG. 10, the insulating element 41 may be an inductor (coil). When the insulating element 41 is an inductor (coil), the insulating element 31 is also an inductor (coil). One pad 42 is disposed inside the insulating element 41, and the other pad 42 is disposed outside the insulating element 41. Both pads 42 may be disposed outside the insulating element 41.

  Although not shown, the transmission circuit 3, the isolator element 4, and the reception circuit 5 can be mounted on the same semiconductor chip.

(Second Embodiment)
The semiconductor integrated circuit and the manufacturing method thereof according to the second embodiment are the same as the semiconductor integrated circuit and the manufacturing method thereof according to the first embodiment except for the following description.

  Referring to FIG. 11, the plurality of groove patterns 25 are formed on the insulating element 41 when viewed from the upper surface of the semiconductor chip 10 (as viewed from the film thickness direction of the insulating film 20 and as viewed from the opposing direction of the insulating elements 31 and 41). It is a closed loop that surrounds several layers. The insulating element 41 and the pad 42 are disposed inside the plurality of groove patterns 25 forming the closed loop, and the pad 32 is disposed outside the plurality of groove patterns 25 forming the closed loop.

Assuming that the resistivity at the interface between the insulating films 20 and 21 is uniform, the creeping withstand voltage is determined by the length of the path having the shortest creepage distance. Therefore, the creeping withstand voltage can be reliably improved by the plurality of groove patterns 25 forming a closed loop.
The pads 32 may be disposed inside the plurality of groove patterns 25 forming the closed loop, and the insulating elements 41 and the pads 42 may be disposed outside. By arranging the pad 32 and the insulating element 41 having the smaller outer shape inside the plurality of groove patterns 25, the occupied area of the plurality of groove patterns 25 can be reduced.

The plurality of groove patterns 25 surrounding the insulating element 41 may be open on the opposite side of the pad 32.
For example, as shown in FIG. 12, the plurality of groove patterns 25 are seen from the upper surface of the semiconductor chip 10 (viewed from the film thickness direction of the insulating film 20 and viewed from the opposing direction of the insulating elements 31 and 41). A right-angled U-shape that surrounds 41 is formed. Here, in the plurality of groove patterns 25 forming a right-angled U-shape, the opposite side of the pad 32 is open. When viewed from the top surface of the semiconductor chip 10, at least a part of the plurality of groove patterns 25 forming a right-angled U shape is disposed between the pad 32 and the insulating element 41. According to the plurality of right-angle U-shaped groove patterns 25, the creeping withstand voltage improvement effect intermediate between the plurality of linear groove patterns 25 shown in FIG. 9 and the plurality of groove patterns 25 forming the closed loop shown in FIG. Can be obtained.
Pads 32 may be arranged inside the plurality of right-angled U-shaped groove patterns 25, and insulating elements 41 may be arranged outside.

(Third embodiment)
The semiconductor integrated circuit and the manufacturing method thereof according to the third embodiment are the same as the semiconductor integrated circuit and the manufacturing method thereof according to the first or second embodiment except for the following description.

  Referring to FIG. 13, the groove depth of the plurality of groove patterns 25 formed on the upper surface 20 a of the insulating film 20 increases as the distance from the insulating element 41 increases. That is, the groove depth of the (K + 1) th groove pattern in the direction away from the insulating element 41 is equal to or greater than the groove depth of the Kth groove pattern. The plurality of groove patterns 25 include groove patterns 26 and 27. The distance from the insulating element 41 to the groove pattern 27 is longer than the distance from the insulating element 41 to the groove pattern 26, and the groove depth of the groove pattern 27 is larger than the groove depth of the groove pattern 26.

The effect of this embodiment is demonstrated with reference to FIG. Increasing the groove depth increases the creepage distance as shown by the equation (1), but the effective film thickness of the insulating film 20 may decrease as the equation (3) shows and the withstand voltage may deteriorate. The groove depth of the groove located at a distance x from the end of the insulating element 41 is defined as H (x). There is no problem as long as the withstand voltage between the first voltage operating circuit 30 and the second voltage operating circuit 40 in the path through the groove is equal to or higher than the withstand voltage between the insulating elements 31 and 41. This relationship is expressed by the following equation, where A is the breakdown voltage per unit film thickness of the insulating film 20 and a is the breakdown voltage per unit length of the interface between the insulating films 20 and 21:
ax + A {TH (x)} ≧ AT (4)
It is represented by That is, the following formula:
H (x) ≦ (a / A) x (5)
As long as the relationship is satisfied. In other words, the greater the distance from the insulating element 41, the greater the groove depth. According to the present embodiment, the creepage distance between the first voltage operation circuit 30 and the second voltage operation circuit 40 can be maximized without deteriorating the withstand voltage through the insulating film 20.

  A plurality of groove patterns 25 with a gradient in groove depth can be easily formed by increasing the number of steps. A method of giving a gradient to the groove depth of the plurality of groove patterns 25 will be described below.

As shown in FIG. 8, a plurality of groove patterns 25 parallel to each other are formed on the upper surface 20 a of the insulating film 20. At this stage, the groove depth of the plurality of groove patterns 25 is uniform.
As shown in FIG. 15A, a portion 25 a far from the insulating element 41 is dug out of the plurality of groove patterns 25. For example, only the portion 25a can be dug down by performing etching or exposure in a state where the portion other than the portion 25a is masked.
As shown in FIG. 15B, a portion 25 b far from the insulating element 41 among the plurality of groove patterns 25 is further dug down.
FIG. 15C shows a state in which the process of applying a gradient to the groove depth of the plurality of groove patterns 25 has been completed. The groove depth of the plurality of groove patterns 25 increases as the distance from the insulating element 41 increases.

(Fourth embodiment)
The semiconductor integrated circuit and the manufacturing method thereof according to the fourth embodiment are the same as the semiconductor integrated circuit and the manufacturing method thereof according to the first embodiment except for the following description.

  Referring to FIG. 16, in this embodiment, interlayer insulating films 18 and 19 are provided in place of insulating films 20 and 21. The interlayer insulating films 18 and 19 are, for example, silicon oxide films (SiO 2 films). The pad 32, the insulating element 41, and the pad 42 are formed in the interlayer insulating film 19 as internal wiring.

  The insulating element 31 is formed in the interlayer insulating film 13. Interlayer insulating films 14 to 18 are formed on the insulating element 31 and the interlayer insulating film 13. A pad 32, an insulating element 41, a pad 42, and an interlayer insulating film 19 are formed on the interlayer insulating film 18. The insulating element 41 is provided so as to face the insulating element 31 through the interlayer insulating films 14 to 18. The pad 32, the insulating element 41, the pad 42, the interlayer insulating film 19, the bonding wire 33, and the bonding wire 43 are covered with the resin 22.

  A plurality of concavo-convex patterns parallel to each other are formed on the insulators 18, 19, and 22 that insulate the first voltage operation circuit 30 and the second voltage operation circuit 40 from each other. On the upper surface 18 a of the interlayer insulating film 18, a plurality of concavo-convex patterns 25 that are parallel to each other are formed. A plurality of concavo-convex patterns complementary to the plurality of concavo-convex patterns 25 are formed on the lower surface of the interlayer insulating film 19. A plurality of concavo-convex patterns are also formed above the plurality of concavo-convex patterns 25 at the interface between the interlayer insulating film 19 and the resin 22.

Note that the plurality of uneven patterns parallel to each other may be formed not only at the bonding interface between the uppermost interlayer insulating films but also at the bonding interfaces between interlayer insulating films at various locations. For example, a plurality of concavo-convex patterns parallel to each other may be formed at the bonding interface between the interlayer insulating films 15 and 16.
In addition, this embodiment can be combined with the second embodiment or the third embodiment.

(Fifth embodiment)
The semiconductor integrated circuit and the manufacturing method thereof according to the fifth embodiment are the same as the semiconductor integrated circuit and the manufacturing method thereof according to the first embodiment except for the following description.

  FIG. 17 shows an example of a printed wiring board assembly according to the present embodiment. The printed wiring board assembly 143 includes a semiconductor package 127, a semiconductor package 128, a semiconductor package 124, and a printed wiring board 133 on which the semiconductor packages 127, 128, and 124 are mounted. The semiconductor package 127 includes a semiconductor chip 109 and a resin 22 that molds the semiconductor chip 109. The semiconductor chip 109 includes the microcontroller 1. The semiconductor package 128 includes a semiconductor chip 103, a semiconductor chip 110, a semiconductor chip 102, and a resin 22 that molds the semiconductor chips 103, 110, and 102. The semiconductor chip 110 includes an isolator element 4. The transmission circuit 3 and the isolator element 4 of the semiconductor chip 103 are connected via a bonding wire. The isolator element 4 and the receiving circuit 5 of the semiconductor chip 102 are connected via a bonding wire.

With reference to FIG. 18, the semiconductor chip 10 is a semiconductor chip 110. The first voltage operation circuit 30 includes an insulating element 31, a pad 32, a bonding wire 33, and a lead wiring 35. The insulating element 31 is connected to the pad 32 through the lead wiring 35. The lead-out wiring 35 is formed in the interlayer insulating film 13 as an internal wiring.
Moreover, it is possible to combine this embodiment and the several uneven | corrugated pattern 25 which concerns on 2nd and 3rd embodiment.

(Sixth embodiment)
The semiconductor integrated circuit and the manufacturing method thereof according to the sixth embodiment are the same as the semiconductor integrated circuit and the manufacturing method thereof according to the fifth embodiment except for the following description.

  Referring to FIG. 19, when viewed from the top surface of semiconductor chip 10, a plurality of groove patterns 25 are formed only in a region between pad 32 and insulating element 41 so as to bypass the region where a plurality of groove patterns 25 are formed. A lead-out wiring 35 is provided. Therefore, when viewed from the top surface of the semiconductor chip 10, the plurality of groove patterns 25 do not overlap the first voltage operation circuit 30.

  Therefore, even if the groove depth of the plurality of groove patterns 25 is increased, dielectric breakdown occurs between the lower end of the groove pattern 25 and the first voltage operation circuit 30 (for example, the lead wiring 35) via the insulating film 20. It is prevented.

  Note that also in the first embodiment, the third embodiment, and the fourth embodiment, when viewed from the top surface of the semiconductor chip 10, the plurality of groove patterns 25 form the first voltage operation circuit 30 (for example, the circuit 34). You may make it not overlap.

(Seventh embodiment)
The semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method according to the seventh embodiment are the same as the semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method according to the fourth embodiment except for the following description.

  Referring to FIG. 20, the semiconductor chip 10 is a semiconductor chip 110. The first voltage operation circuit 30 includes an insulating element 31, a pad 32, a bonding wire 33, and a lead wiring 35. The insulating element 31 is connected to the pad 32 through the lead wiring 35. The lead-out wiring 35 is formed in the interlayer insulating film 13 as an internal wiring.

  In the present embodiment, as in the sixth embodiment, the plurality of groove patterns 25 may not overlap the first voltage operation circuit 30 when viewed from the upper surface of the semiconductor chip 10.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, it is preferable that the groove pitch P is constant because the number N of groove patterns included in the plurality of groove patterns 25 is large, but the groove pitch P may not be constant. The plurality of groove patterns (uneven patterns) 25 may not be parallel to each other. The shape of the insulating elements 31 and 41 is not limited to a quadrangle, and may be an octagon. The plurality of groove patterns (uneven patterns) 25 may include a portion extending in the X direction, a portion extending in the Y direction perpendicular to the X direction, and a portion extending obliquely with respect to the X direction and the Y direction.

DESCRIPTION OF SYMBOLS 1 ... Microcontroller 2 ... Isolator 3 ... Transmission circuit 4 ... Isolator element 5 ... Reception circuit 6 ... Gate driver 7 ... Transistor 8 ... Motor 10 ... Semiconductor chip 11 ... Substrate 12-19 ... Interlayer insulation film 18a ... Upper surface 20, 21 ... Insulating film 20a ... Upper surface 22 ... Resin 25 ... Uneven pattern 25a, 25b ... Parts 26, 27 far from insulating element ... Groove pattern 30 ... First voltage operating circuit 40 ... Second voltage operating circuit 31, 41 ... Insulating elements 32, 42 ... Pad 33, 43 ... Bonding wire 34 ... Circuit 35 ... Lead wiring 101-110 ... Semiconductor chips 121-128 ... Semiconductor packages 131-133 ... Printed wiring boards 141-143 ... Printed wiring board assembly

Claims (8)

A first circuit operating at a first voltage;
A second circuit operating at a second voltage different from the first voltage;
An insulator for insulating the first circuit and the second circuit from each other;
A semiconductor integrated circuit in which a plurality of uneven patterns are formed on the insulator. The semiconductor integrated circuit according to claim 1,
The insulator includes an insulating film;
The first circuit includes:
A first insulating element;
A first pad connected to the first insulating element;
The second circuit includes a second insulating element provided to face the first insulating element through the insulating film,
The first insulating element and the second insulating element are a pair of plates or inductors forming a capacitor or a transformer,
The plurality of concavo-convex patterns are formed in the insulating film so as to intersect with a line segment connecting the first pad and the second insulating element when viewed in a facing direction of the first insulating element and the second insulating element. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
The plurality of uneven patterns form a closed loop,
The second insulating element is disposed on one of the inside and the outside of the closed loop when viewed in the facing direction, and the first pad is disposed on the other of the inside and the outside. Semiconductor integrated circuit. A semiconductor integrated circuit according to claim 2 or 3,
The first insulating element is disposed under the insulating film,
The second insulating element is disposed on the insulating film;
The plurality of concavo-convex patterns are a plurality of groove patterns formed on the upper surface of the insulating film,
The groove depth of the plurality of groove patterns increases as the distance from the second insulating element increases. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
The semiconductor integrated circuit, wherein the first circuit does not overlap the plurality of uneven patterns when viewed in the facing direction. A first insulating element;
An insulating film formed on the first insulating element;
A second insulating element formed on the insulating film so as to face the first insulating element;
A first pad formed on the insulating film;
The first pad is connected to the first insulating element;
The first insulating element and the second insulating element are a pair of inductors or electrode plates that form a transformer or a capacitor that transmits a signal between circuits having different operating voltages,
A plurality of groove patterns are formed in a region between the first pad and the second insulating element on the upper surface of the insulating film,
The plurality of groove patterns intersect a line segment connecting the first pad and the second insulating element. Forming a first circuit operating at a first voltage;
Forming a second circuit that operates at a second voltage different from the first voltage;
Forming an insulator that insulates the first circuit and the second circuit from each other;
Forming a plurality of concavo-convex patterns on the insulator; and a method of manufacturing a semiconductor integrated circuit. A method of manufacturing a semiconductor integrated circuit according to claim 7,
Forming the insulator includes forming an insulating film;
Forming the first circuit includes:
Forming a first insulating element;
Forming a first pad connected to the first insulating element;
Forming the second circuit includes forming a second insulating element on the insulating film so as to face the first insulating element;
The first insulating element and the second insulating element are a pair of plates or inductors forming a capacitor or a transformer,
Forming the plurality of concavo-convex patterns,
A plurality of groove patterns are formed on the upper surface of the insulating film so as to intersect a line segment connecting the first pad and the second insulating element when viewed in the opposing direction of the first insulating element and the second insulating element. To do
Digging out a portion of the plurality of groove patterns far from the second insulating element so that the groove depth of the plurality of groove patterns increases as the distance from the second insulating element increases. .

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