JP6894859B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and can be suitably used for a semiconductor device provided with a protection circuit for static electricity (ESD: Electro-Static Discharge), for example.

Various proposals have been made conventionally for a method of protecting a semiconductor device from destruction due to static electricity or the like. On the other hand, for the purpose of reducing the size of the semiconductor chip, it is called a finger structure or comb tooth structure in which the gate electrodes of a plurality of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) included in the ESD protection circuit are connected and arranged in parallel. The layout has been applied.

Patent Document 1 below discloses an ESD protection circuit using a finger structure, and of a plurality of drain regions, a contact portion to the drain region farthest from the contact portion to the well region is formed from a gate electrode. The technology to keep away is disclosed.

Japanese Unexamined Patent Publication No. 9-181196

In a circuit using a finger structure, a device structure for improving static electricity resistance is required, and further, it is required to reduce the layout area of the circuit for the purpose of miniaturization of a semiconductor chip.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

A brief overview of typical embodiments disclosed in the present application is as follows.

The semiconductor device according to the embodiment includes a semiconductor substrate, a first conductive type first well region formed on the semiconductor substrate, a first element separation portion formed in the first well region, and a first well. A first feeding region and a first active region, which are a part of the region and are partitioned by the first element separation portion in a plan view, and a plurality of first gate electrodes formed on the first active region. Has. Further, the semiconductor device is electrically connected to a plurality of first impurity regions of the second conductive type formed in the first active region and a plurality of second gate electrodes which are a part of the plurality of first gate electrodes. It has a first gate drive circuit connected to the first gate drive circuit and a second gate drive circuit electrically connected to one or more third gate electrodes which are a part of the plurality of first gate electrodes. Here, the number of the plurality of second gate electrodes is larger than the number of one or more third gate electrodes, and the plurality of second gate electrodes is larger than the number of one or more third gate electrodes. It is located far from the power supply area.

According to one embodiment, the reliability of the semiconductor device can be improved.

It is a circuit diagram of the semiconductor device of Embodiment 1. It is a main part plan view of the semiconductor device of Embodiment 1. FIG. It is sectional drawing of the semiconductor device of Embodiment 1. FIG. It is a main part plan view of the semiconductor device of Embodiment 2. It is a main part plan view of the semiconductor device of Embodiment 3. It is a main part plan view of the semiconductor device of Embodiment 4. It is a main part plan view of the semiconductor device of Embodiment 5. It is a main part plan view of the semiconductor device of Embodiment 6. It is a main part plan view of the semiconductor device of Embodiment 7. It is sectional drawing of the semiconductor device of Embodiment 7. It is a main part plan view of the semiconductor device of Embodiment 8. It is sectional drawing of the semiconductor device of Embodiment 8. It is a main part plan view of the semiconductor device of the study example. It is sectional drawing of the semiconductor device of the study example.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. It is related to some or all of the modified examples, details, supplementary explanations, etc. In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number. Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of a component or the like, the shape is substantially the same unless otherwise specified or when it is considered that it is not apparent in principle. Etc., etc. shall be included. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiment, the members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle except when it is particularly necessary.

Further, in the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand. Further, even when the cross-sectional view corresponds to the plan view, a specific portion may be displayed in a relatively large size in order to make the drawing easy to understand.

Further, in the drawings used in the embodiment, hatching may be omitted in order to make the drawings easier to see.

Further, in the present embodiment, the p-type _{means the conductive type shown when an impurity such as boron (B) or boron difluoride (BF 2} ) is introduced into the semiconductor, and the n-type means the conductive type. , Means the conductive type shown when impurities such as arsenic (As) or phosphorus (P) are introduced into the semiconductor.

(Embodiment 1)
The semiconductor device of this embodiment will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows a circuit diagram of a main part of the semiconductor device of the present embodiment. FIG. 2 shows a plan view of a main part of the output circuit OP1. FIG. 3 is a cross-sectional view taken along the line AA shown in FIG.

As shown in FIG. 1, the semiconductor chip, which is the semiconductor device of the present embodiment, includes a terminal (pad electrode) PAD, a protection circuit PC, an output circuit OP1, an output circuit OP2, and gate drive circuits DRa to DRf. And have. The terminal PAD is connected to the protection circuit PC, the output circuit OP1 and the output circuit OP2. In the present embodiment, the terminal PAD functions as an output terminal for outputting signals from the output circuit OP1 and the output circuit OP2 to the outside of the semiconductor chip. The power supply voltage line VCS is a wiring for supplying the power supply potential Vcc, and the ground voltage line VSS is a wiring for supplying the ground potential Vss.

The protection circuit PC for static electricity has a diode D1, a diode D2, and a clamp element CL. The diode D1 is connected between the terminal PAD and the power supply voltage line VCS, the anode of the diode D1 is connected to the terminal PAD, and the cathode of the diode D1 is connected to the power supply voltage line VCS. The diode D2 is connected between the terminal PAD and the ground voltage line VSS, the cathode of the diode D2 is connected to the terminal PAD, and the anode of the diode D2 is connected to the ground voltage line VSS. A clamp element CL is provided between the power supply voltage line VCS and the ground voltage line VSS. The clamp element CL is provided for the purpose of preventing the diode D2 from breaking down in the reverse direction when a large amount of static electricity is applied to the terminal PAD, for example, so that the static electricity can be safely released. The clamp element CL is composed of a thyristor or the like.

The current path I1 shown in FIG. 1 indicates a path through which the static electricity applied to the terminal PAD is discharged by the protection circuit PC. At this time, a current also flows in the n-type MISFET group 1QA in the output circuit OP1 due to the NPN bipolar operation. The current path I2 shows the path of this current. The description of the current path I2 will be described in detail in the column of the later study example and the column of the main features of the present embodiment.

The output circuit OP1 is composed of n-type MOSFET groups 1QA to 1QC. Each of these MISFET groups 1QA to 1QC is composed of one n-type MISFET or a plurality of n-type MISFETs connected in parallel to each other. As shown in FIG. 1, for example, the MISFET group 1QA of the present embodiment is composed of four n-type MISFETs 1Qa connected in parallel to each other. Similarly, the MISFET group 1QB and the MISFET group 1QC are composed of an n-type MISFET1Qb and an n-type MISFET1Qc as shown in FIG. 2, respectively.

In the present embodiment, when the gate, drain or source of the MISFET group 1QA is expressed, they are the gate electrode Ga, the drain region (impurity region) ND or the source region (of each of the plurality of n-type MISFET 1Qa). Impurity region) NS. The same applies to other MISFET groups with respect to such expressions.

As shown in FIGS. 1 and 2, the drain of the MISFET group 1QA to 1QC is connected to the terminal PAD, the source of the MISFET group 1QA to 1QC is connected to the ground voltage line VSS, and the gate of the MISFET group 1QA to 1QC. Are connected to the gate drive circuits DRa to DRc, respectively. That is, in the n-type MISFETs 1Qa to 1Qc, each drain region ND is electrically connected to the terminal PAD, each source region NS is electrically connected to the ground voltage line VSS, and each gate electrode Ga to The Gc is electrically connected to the gate drive circuits DRa to DRc, respectively. The drain region ND and the source region NS are semiconductor regions in which n-type impurities are introduced into the semiconductor substrate SB.

The output circuit OP2 is composed of p-type MOSFET groups 2QD to 2QF. Each of these MISFET groups 2QD to 2QF is composed of a single p-type MISFET or a plurality of p-type MISFETs connected in parallel to each other.

As shown in FIG. 1, the drains of the MISFET groups 2QD to 2QF are connected to the power supply voltage line VCS, the sources of the MISFET groups 2QD to 2QF are connected to the terminal PAD, and the gates of the MISFET groups 2QD to 2QF are connected to the terminals PAD, respectively. , It is connected to the gate drive circuits DRd to DRf.

The gate drive circuits DRa to DRf are circuits for controlling the voltage supplied to each gate of the MISFET groups 1QA to 1QC and the MISFET groups 2QD to 2QF and their timing, and can be controlled independently of each other. It is a circuit.

Next, the planar structure and the cross-sectional structure of the output circuit OP1 will be described in detail with reference to FIGS. 2 and 3. Although FIG. 2 is a plan view, hatching is provided on the gate electrodes Ga to Gc to make the drawing easier to see. Further, in FIG. 2, the gate drive circuits DRa to DRc, the active region AR1, the feeding region SR1, the element separation unit STI, the gate electrodes Ga to Gc, the drain region ND, and the source, which constitute the main feature portion of the present embodiment, are shown. The region NS and the body region (impurity region) PB are shown, and the other parts are not shown.

The semiconductor substrate SB is preferably made of single crystal silicon having a specific resistance of about 1 to 10 Ωcm, and is made of, for example, p-type single crystal silicon. A p-type well region PW is formed on the surface side of the semiconductor substrate SB, and an element separation portion STI is formed in the well region PW. The element separation portion STI is formed, for example, by forming a groove in the well region PW and embedding an insulating film made of, for example, silicon oxide in the groove. Further, the depth of the well region PW is deeper than the depth of the element separation portion STI. Therefore, the well region PW is formed so as to surround the bottom portion of the element separation portion STI.

As shown in FIG. 2, the active region AR1 and the feeding region SR1 are partitioned by the element separation unit STI in a plan view, but as shown in FIG. 3, the active region AR1 and the feeding region SR1 have a cross section. It is an integrated area in the visual sense. That is, the active region AR1 and the feeding region SR1 are each a part of the well region PW.

The power feeding region SR1 extends in the Y direction in a plan view. That is, the length of the feeding region SR1 in the Y direction is larger than the length of the feeding region SR1 in the X direction. A p-type body region PB is formed on the surface of the well region PW of the power feeding region SR1, and a silicide layer SI made of, for example, cobalt silicide or nickel silicide is formed on the body region PB.

Further, although not shown in FIG. 2, a plurality of plug PGs are formed on the upper surface of the body region PB. The body region PB is electrically connected to the wiring M1 via the VDD layer SI and the plug PG. The wiring M1 is electrically connected to, for example, the ground voltage line VSS, whereby the ground potential Vss is applied to the body region PB and the well region PW.

The active region AR1 is a region in which the MISFETs 1Qa to 1Qc are formed, and is arranged at a position sandwiched between the two feeding regions SR1 in the X direction. The gate electrodes Ga to Gc are formed on the well region PW via the gate insulating films GIa to GIc, respectively, and extend in the Y direction in a plan view.

The gate insulating films GIa to GIc are formed on the well region PW and on the side surface of the groove formed in the interlayer insulating film IL1. The materials constituting the gate insulating films GIa to GIc include, for example, a silicon oxide film and a metal oxide film (high dielectric constant film) such as a hafnium oxide film or a tantalum oxide film formed on the silicon oxide film. It is a laminated film containing.

The gate electrodes Ga to Gc are embedded in the groove formed in the interlayer insulating film IL1 via the gate insulating films GIa to GIc. The material constituting the gate electrodes Ga to Gc is a titanium nitride film, a metal film such as a tungsten film, or a laminated film in which these metal films are appropriately laminated.

As described above, in the present embodiment, the gate insulating films GIa to GIc and the gate electrodes Ga to Gc are formed by a so-called high-k last structure and a gate last structure.

Further, although not shown in FIGS. 2 and 3, a plug PG is formed on the upper surface of each of the gate electrodes Ga to Gc. The gate electrodes Ga to Gc are connected to the wiring M1 via the plug PG, and are electrically connected to the gate drive circuits DRa to DRc via the wiring M1 and other wiring.

Further, since the four gate electrodes Ga are connected to the same gate drive circuit DRa, the same potential is applied to each of the four gate electrodes Ga, and the four gate electrodes Ga are driven at the same timing. Similarly, the same potential is applied to each of the two gate electrodes Gb, and they are driven at the same timing. Further, the same potential is applied to each of the two gate electrodes Gc, and they are driven at the same timing. Such a structure in which a plurality of gate electrodes having the same potential are arranged so as to be adjacent to each other may be referred to as a finger structure or a comb tooth structure.

A sidewall spacer SW is formed on both side surfaces of the gate electrodes Ga to Gc. The sidewall spacer SW is composed of, for example, a laminated film of a silicon oxide film and a silicon nitride film.

An n-type drain region ND and an n-type source region NS are formed on the surface of the well region PW of the active region AR1. The drain region ND and the source region NS are formed in the well region PW beside each gate electrode Ga to Gc, and are alternately arranged for each gate electrode Ga to Gc. That is, two MISFETs adjacent to each other are arranged so as to share one drain region ND or one source region NS.

Similar to the body region PB, the silicide layer SI is formed in a part on the drain region ND and a part on the source region NS. The silicide layer SI formed on the drain region ND and the source region NS is formed at a distance from the ends of the gate electrodes Ga to Gc by the width of the sidewall spacer SW.

Further, although not shown in FIGS. 2 and 3, a plurality of plug PGs are formed on the upper surfaces of the drain region ND and each source region NS. Each drain region ND and each source region NS are connected to the wiring M1 via the VDD layer SI and the plug PG. Through this wiring M1 and other wiring, each drain region ND is electrically connected to the terminal PAD, and each source region NS is electrically connected to the ground voltage line VSS.

An interlayer insulating film IL1 is formed on the semiconductor substrate SB, and gate electrodes Ga to Gc are embedded in the grooves formed in the interlayer insulating film IL1. The interlayer insulating film IL1 is, for example, an insulating film made of silicon oxide. An insulating film serving as an etching stopper film, such as a silicon nitride film, may be provided between the semiconductor substrate SB and the interlayer insulating film IL1. An interlayer insulating film IL2 is formed on the gate electrodes Ga to Gc and on the interlayer insulating film IL1. The interlayer insulating film IL2 is, for example, an insulating film made of silicon oxide. The plurality of plug PGs described above are formed in the interlayer insulating film IL1 and in the interlayer insulating film IL2. The plug PG can be formed by forming contact holes in the interlayer insulating film IL1 and the interlayer insulating film IL2, and embedding a conductive film mainly composed of tungsten or the like in the contact holes.

An interlayer insulating film IL3 is formed on the plug PG and the interlayer insulating film IL2. The interlayer insulating film IL3 is an insulating film having a lower dielectric constant than silicon oxide, such as a SiOC film. The plurality of wirings M1 described above are formed in the interlayer insulating film IL3. The wiring M1 can be formed by forming a groove for wiring in the interlayer insulating film IL3 and then embedding a conductive film containing, for example, copper as a main component in the groove for wiring. The structure of the wiring M1 is called a so-called Damascene wiring structure. After that, the wiring for the second and subsequent layers is formed by the Dual Damascene method or the like, but the illustration and the description thereof are omitted here. The power supply voltage line VCS and the ground voltage line VSS shown in FIG. 1 are a part of these wirings.

Further, the multi-layer wiring including the wiring M1 and the wiring of the second and subsequent layers is not limited to the damascene wiring structure, and may be formed by patterning a conductive film, and may be, for example, tungsten wiring or aluminum wiring.

Further, the terminal PAD shown in FIG. 1 is composed of a part of the wiring of the uppermost layer of the multilayer wiring, and functions as a region for connecting to the outside of the semiconductor chip by wire bonding or bump electrodes.

One of the features of the present embodiment is that the MISFET group 1QA containing a relatively large amount of MISFET1Qa contains a MISFET group 1QB containing a relatively small number of MISFET1Qb or a relatively small number of MISFET1Qc in the active region AR1. It is arranged at a position farther from the feeding region SR1 than the MISFET group 1QC. In other words, in the active region AR1, the four gate electrodes Ga connected to the gate drive circuit DRa are the two gate electrodes Gb connected to the gate drive circuit DRb or the two gate electrodes Gb connected to the gate drive circuit DRc. It is arranged at a position farther from the feeding region SR1 than the gate electrode Gc. The effect of such an arrangement will be described in detail later.

<About study examples>
Hereinafter, the semiconductor device of the study example examined by the inventor of the present application and its problems will be described with reference to FIGS. 13 and 14.

The semiconductor device of the study example has an output terminal PAD, a protection circuit PC, and the like as shown in FIG. 1 of the present embodiment, but has an output circuit OP3 different from the output circuit OP1 of the present embodiment. There is.

FIG. 13 is a plan view of a main part of the output circuit OP3 of the study example, and FIG. 14 is a cross-sectional view taken along the line CC shown in FIG. Although FIG. 13 is a plan view, hatching is provided on the gate electrode Ga to make the drawing easier to see. Further, although FIG. 14 is a cross-sectional view, an equivalent circuit for explaining the problems of the study example is also attached, and in order to facilitate the explanation, hatching is omitted and the configuration other than the configuration necessary for the explanation is omitted. The figure number is also omitted.

The output circuit OP3 of the study example is a circuit corresponding to the output circuit OP1 of the present embodiment, and includes a plurality of n-type MISFET1Qa having a plurality of gate electrodes Ga electrically connected to the gate drive circuit DRa. In the study example, a plurality of MISFET1Qa are formed in the active region AR1, but other MISFETs such as MISFET1Qb and MISFET1Qc are not formed in the active region AR1 as in the present embodiment.

An n-type drain region ND2 and an n-type source region NS are formed on the surface of the well region PW of the active region AR1. The drain region ND2 and the source region NS are formed in a well region PW beside each gate electrode Ga, and are alternately arranged for each gate electrode Ga. Although not shown, plug PGs are formed on the upper surfaces of the drain region ND1, the drain region ND2, and the source region NS, as in the present embodiment. That is, the drain region ND1 and the drain region ND2 are electrically connected to the terminal PAD via the plug PG, and the source region NS is electrically connected to the ground voltage line VSS via the plug PG.

However, in the study example, unlike the present embodiment, the width of the drain region ND1 formed in the central portion of the active region AR1 in the X direction is the width of the drain region ND2 formed in the peripheral portion of the active region AR1. Greater than width. That is, in the X direction, the distance between the plug PG on the drain region ND1 and the gate electrode Ga is made wider than the distance between the plug PG on the drain region ND2 and the gate electrode Ga. The reason why the width of the drain region ND1 is set in this way will be described below.

In the study example as well, as in the present embodiment, when static electricity is applied to the terminal PAD, static electricity is discharged from the current path I1 by the protection circuit PC shown in FIG. At this time, in the output circuit OP3 including a plurality of n-type MISFET1Qa, a current passing through the current path I2 flows due to the NPN bipolar operation. This current is positive generated at the junction between the drain region ND1 and the drain region ND2 and the well region PW when a potential is applied from the terminal PAD to the drain region ND1 and the drain region ND2 via the plug PG. Due to the hole-electron pair. The hole current due to the holes in the hole-electron pair causes a potential difference in the resistance component Rpw of the well region PW. Here, the drain region ND1, the well region PW and the source region NS, and the drain region ND2, the well region PW and the source region NS form a pseudo NPN bipolar. Therefore, the NPN bipolar operation is started by the hole current.

Here, the drain region ND1 of the MISFET1Qa located at a position relatively far from the power supply region SR1 of the well region PW is a location where the resistance component Rpw is relatively high and the NPN bipolar operation starts earliest. Therefore, the drain region ND1 is a place where the current is most concentrated and is the most fragile place.

In response to such a problem, in the study example, the width of the drain region ND1 is relatively widened in the X direction, and the distance between the plug PG on the drain region ND1 and the gate electrode Ga is relatively widened. There is. As a result, in the semiconductor device of the study example, a device is devised to reduce the density of the portion where the current is concentrated and to improve the electrostatic resistance.

However, according to the consideration of the inventor of the present application, it has been found that the semiconductor device of the study example has the following problems.

First, by making the width of the drain region ND1 wider than the width of the drain region ND2, the area of the output circuit OP3 increases. In particular, in the study example, only one type of gate drive circuit DRa is illustrated, but in an output circuit including a plurality of such gate drive circuits and a plurality of MISFETs connected to them, the area of this output circuit is large. It will increase further. Therefore, the semiconductor device of the study example is not suitable for miniaturization of the device.

Next, in the MISFET1Qa using a finger structure such as the gate electrode Ga, analog characteristics are emphasized, but if the width of the drain region ND1 is changed, the symmetry of each MISFET1Qa is disturbed. Therefore, it is difficult to realize high-precision analog characteristics in the semiconductor device of the study example.

<Main features of the semiconductor device of this embodiment>
The main features of the semiconductor device of this embodiment will be described below.

In the output circuit OP1 of the present embodiment, unlike the output circuit OP3 of the study example, the widths of the drain regions ND of the MISFETs 1Qa to 1Qc are the same. Therefore, the area of the output circuit OP1 is not increased, and the symmetry of each MISFET 1Qa to 1Qc is ensured. That is, the semiconductor device of the present embodiment is suitable for miniaturization of elements, and can realize high-precision analog characteristics.

Further, in the present embodiment, in the active region AR1, the MISFET group 1QA containing a relatively large amount of MISFET1Qa is a MISFET group 1QB containing a relatively small number of MISFET1Qb, or a MISFET group 1QC containing a relatively small number of MISFET1Qc. It is arranged at a position farther from the power feeding area SR1. In other words, in the active region AR1, the four gate electrodes Ga connected to the gate drive circuit DRa are the two gate electrodes Gb connected to the gate drive circuit DRb or the two gate electrodes Gb connected to the gate drive circuit DRc. It is arranged at a position farther from the feeding region SR1 than the gate electrode Gc. That is, when the MISFETs 1Qa to 1Qc are arranged in the active region AR1, a plurality of MISFETs having a large number of gate electrodes having the same potential are arranged at a position farther from the feeding region SR1.

As described in the above study example, in the output circuit OP1 including the MISFET1QA to 1QC when static electricity is applied to the terminal PAD, the MISFET group 1QA located at a position relatively far from the feeding region SR1 is the MISFET group 1QB. And the resistance component Rpw is relatively higher than that of the MISFET group 1QC, and the NPN bipolar operation starts earliest. Therefore, the current path I2 of the MISFET group 1QA is the place where the current is most concentrated due to the NPN bipolar operation, and is the most fragile place.

Therefore, in the present embodiment, a plurality of MISFET1Qa having a relatively large number of gate electrodes Ga connected to the gate drive circuit DRa are arranged at a position relatively far from the power feeding region SR1. As a result, it is possible to increase the number of locations where the NPN bipolar operation is performed in the central portion of the active region AR1. That is, since the amount of current that can be passed until the destruction due to static electricity can be increased, the current concentrated in the central portion of the active region AR1 can be dispersed. Therefore, the electrostatic resistance of the semiconductor device can be increased, and the reliability of the semiconductor device is improved.

Further, in the present embodiment, an example in which three MISFET groups 1QA to 1QC are provided in the active region AR1 has been described, but the number of such MISFET groups is not limited to three, and may be four or more. Even in that case, it is important that the number of gate electrodes included in the MISFET group relatively far from the feeding region SR1 is larger than the number of gate electrodes included in the MISFET group relatively close to the feeding region SR1.

(Embodiment 2)
FIG. 4 shows the semiconductor device of the second embodiment. In the following description, the differences from the first embodiment will be mainly described. Although FIG. 4 is a plan view, hatching is provided on the gate electrodes Ga to Gc and G0 to make the drawing easier to see.

In the first embodiment, in the active region AR1, the gate electrode Gb connected to the gate drive circuit DRb and the gate electrode Gc connected to the gate drive circuit DRc are arranged in the region closest to the power supply region SR1. ..

In the second embodiment, as shown in FIG. 4, the gate electrode G0 connected to the ground voltage line VSS is arranged in the region closest to the feeding region SR1 in the active region AR1. That is, the gate electrode G0 is arranged as a dummy gate electrode that does not contribute to any operation of MISFET1Qa to 1Qc.

Although a plurality of gate electrodes Ga to Gc are regularly arranged in the active region AR1, the shapes of the gate electrodes Gb and the gate electrodes Gc closest to the feeding region SR1 are most likely to vary. The gate electrodes Ga to Gc are formed by forming a single-layer or laminated metal film or the like so as to embed the inside of the groove formed in the interlayer insulating film IL1, and then removing the metal film outside the groove by the CMP method. Will be done. At this time, since the other gate electrodes are regularly arranged on both sides of the gate electrode Ga located in the central portion of the active region AR1 in the X direction, the polishing process by the CMP method tends to be uniform. However, since the gate electrode Gb and the gate electrode Gc located at the end of the active region AR1 have only one other gate electrode next to one in the X direction, film slippage of the metal film occurs in the polishing treatment by the CMP method. Cheap. That is, the shapes of the gate electrode Gb and the gate electrode Gc located at the end of the active region AR1 are likely to vary. Therefore, the MISFET1Qb and MISFET1Qc located at the end of the active region AR1 have poor symmetry with other MISFETs, and the analog characteristics of the output circuit OP1 are deteriorated.

In the second embodiment, in consideration of the above-mentioned problems, the gate electrode G0 as a dummy is formed at the end of the active region AR1, so even if the shape of the gate electrode G0 varies, it is actually There is no effect on the MISFETs 1Qa to 1Qc that operate in. Therefore, the semiconductor device of the second embodiment can further improve the analog characteristics of the MISFETs 1Qa to 1Qc as compared with the first embodiment.

(Embodiment 3)
FIG. 5 shows the semiconductor device of the third embodiment. In the following description, the differences from the first embodiment will be mainly described. Although FIG. 5 is a plan view, hatching is provided on the gate electrodes Ga to Gc to make the drawing easier to see.

In the first embodiment, the feeding region SR1 is formed so as to extend in the Y direction, and is arranged adjacent to the active region AR1 in the X direction.

In the third embodiment, as shown in FIG. 5, the power feeding region SR1 extends not only in the Y direction but also in the X direction. That is, the feeding region SR1 is integrally formed so as to surround the active region AR1 in a plan view. The width of the power supply region SR1 extending in the Y direction in the X direction is about the same as the width of the power supply region SR1 extending in the X direction in the Y direction.

In this way, by providing the power feeding region SR1 also in the X direction, the latch-up resistance of the MISFETs 1Qa to 1Qc can be improved. Further, by providing the power feeding region SR1 extending in the X direction, the path of the hole current due to the NPN bipolar operation is increased, so that the electrostatic resistance of the semiconductor device can be improved.

Further, as shown in FIG. 5, in the present embodiment, the distance L2 between the feeding region SR1 extending in the X direction and the active region AR1 is set to the feeding region SR1 extending in the Y direction and the active region AR1. The distance to and from L1 is larger than that of L1.

As described in the first embodiment, by arranging the MISFET group 1QA having the largest number of gate electrodes in the region farthest from the feeding region SR1 extending in the Y direction, the NPN bipolar operation in the active region AR1 can be achieved. The resulting electrostatic resistance can be improved. However, since the distances from the feeding region SR1 extending in the X direction to each MISFET group 1QA to 1QC are about the same, it is possible to improve the electrostatic resistance by devising the planar arrangement of the gate electrodes Ga to Gc. difficult. Therefore, the active region AR1 is arranged so as to be as far away as possible from the feeding region SR1 extending in the X direction, and the electrostatic resistance is taken as a countermeasure between the active region AR1 and the feeding region SR1 extending in the Y direction as much as possible. It is desirable to do. That is, it is desirable that the distance L2 is sufficiently larger than the distance L1.

As described above, the semiconductor device of the third embodiment can obtain the same effect as that of the first embodiment, and can improve the latch-up resistance and the static electricity resistance.

It is also possible to apply the technique disclosed in the third embodiment to the semiconductor device of the second embodiment described above.

(Embodiment 4)
FIG. 6 shows the semiconductor device of the fourth embodiment. In the following description, the differences from the third embodiment will be mainly described. Although FIG. 6 is a plan view, hatching is provided on the gate electrodes Ga to Gc to make the drawing easier to see.

As shown in FIG. 6, in the fourth embodiment as in the third embodiment, the power feeding region SR1 extends not only in the Y direction but also in the X direction. However, in the fourth embodiment, unlike the third embodiment, the distance L3, which is the width of the power supply region SR1 extending in the Y direction in the X direction, is the width of the power supply region SR1 extending in the X direction in the Y direction. It is larger than a certain distance L4.

Therefore, in the fourth embodiment, the influence of the power feeding region SR1 extending in the X direction on the electrostatic resistance is reduced. Therefore, the electrostatic resistance is dominated by a factor controlled between the feeding region SR1 extending in the Y direction and the active region AR1. By controlling the distance L3 and the distance L4 in this way, the degree of freedom in design for static electricity resistance can be increased.

Further, in the fourth embodiment, unlike the third embodiment, the distance L2 does not necessarily have to be larger than the distance L1, but in order to further improve the electrostatic resistance, the distance L2 is changed to the distance L1. It is desirable that the distance L3 is larger than the distance L4.

(Embodiment 5)
FIG. 7 shows the semiconductor device of the fifth embodiment. In the following description, the differences from the first embodiment will be mainly described. Although FIG. 7 is a plan view, hatching is provided on the gate electrodes Ga to Gc to make the drawing easier to see.

In the first embodiment, one active region AR1 is formed between the two feeding regions SR1 extending in the Y direction.

As shown in FIG. 7, in the fifth embodiment, a plurality of active regions AR1 are partitioned by the element separation unit STI in a plan view. That is, a plurality of active regions AR1 are formed between the two feeding regions SR1 extending in the Y direction.

Although each MISFET1Qa to 1Qc is formed in the plurality of active regions AR1, the total number of each MISFET1Qa to 1Qc is larger in the fifth embodiment than in the first embodiment. Specifically, in the fifth embodiment, the MISFET group 1QA connected to the gate drive circuit DRa includes 16 MISFET 1Qa, and the MISFET group 1QB connected to the gate drive circuit DRb includes 8 MISFET 1Qb. The MISFET group 1QC connected to the gate drive circuit DRc includes eight MISFET 1Qc.

The gate electrodes Ga to Gc extend in the Y direction, respectively, but the width of each of the gate electrodes Ga to Gc in the Y direction is shorter in the fifth embodiment than in the first embodiment. The gate electrodes Ga to Gc are arranged so as to be adjacent not only in the X direction but also in the Y direction.

As described above, in the fifth embodiment, since the shapes of the gate electrodes Ga to Gc are reduced and arranged regularly, the shapes of the gate electrodes Ga to Gc are unlikely to vary in the polishing process by the CMP method. That is, in the first embodiment, since the widths of the gate electrodes Ga to Gc in the Y direction were long, for example, the film thickness of the central portion of the gate electrodes Ga to Gc was increased due to the influence of the dishing. There is a problem that the film thickness tends to be slightly thinner than the film thickness at the end of the. On the other hand, in the fifth embodiment, such a problem can be suppressed, so that the accuracy of the analog characteristics can be further improved.

Further, as described above, the MISFET group 1QA includes 16 MISFET1Qa. This means that the number of places where the NPN bipolar operation occurs increases. In the first embodiment, when the shape of one MISFET1Qa is different among the four MISFET1Qa, the fluttering has a great influence on the change of the current flowing by the NPN bipolar operation. On the other hand, in the fifth embodiment, even if the shape of one MISFET1Qa varies, the above influence can be reduced as a whole. Therefore, more stable NPN bipolar operation is performed, and more stable static electricity resistance can be obtained.

It is also possible to apply the technique disclosed in the fifth embodiment to the semiconductor devices of the third and fourth embodiments described above.

(Embodiment 6)
FIG. 8 shows the semiconductor device of the sixth embodiment. In the following description, the differences from the fifth embodiment will be mainly described. Although FIG. 8 is a plan view, hatching is provided on the gate electrodes Ga to Gc and G0 to make the drawing easier to see.

As shown in FIG. 8, also in the sixth embodiment, a plurality of active regions AR1 are formed at positions sandwiched between the two feeding regions SR1 extending in the Y direction, as in the fifth embodiment. In the sixth embodiment, the dummy gate electrodes G0 as described in the second embodiment described above are arranged at the corners of the plurality of active regions AR1.

As described in the fifth embodiment, the layout shown in FIG. 8 is excellent in suppressing the shape variation of the gate electrodes Ga to Gc, but among these, the corners of the plurality of active regions AR1 The gate electrode to be arranged is the place most likely to be affected by the film slip caused by the CMP method. Therefore, in the sixth embodiment, the gate electrodes G0 are arranged at the lower right and lower left of FIG. 8, respectively. The gate electrode G0 may be arranged at the upper right and upper left of FIG. That is, among the plurality of active regions AR1, the gate electrode of the MISFET formed in the active region AR1 located at the most end in the Y direction and closest to the feeding region SR1 in the X direction is electrically connected to the ground voltage line VSS. The gate electrode G0 connected to is used.

As described above, since the gate electrode G0, which is a dummy gate electrode, is formed in the region where the shape of the gate electrode is most likely to vary, even if the shape of the gate electrode G0 varies, it is actually There is no effect on the operating MISFETs 1Qa to 1Qc. Therefore, the accuracy of the analog characteristics can be further improved.

It is also possible to apply the technique disclosed in the sixth embodiment to the semiconductor devices of the third and fourth embodiments described above.

(Embodiment 7)
9 and 10 show the semiconductor device of the seventh embodiment. In the following description, the differences from the first embodiment will be mainly described.

In the seventh embodiment, an example is shown in which the technique applied to the n-type MISFET groups 1QA to 1QC of the control circuit OP1 is applied to the p-type MISFET groups 2QD to 2QF of the control circuit OP2 by the same technical idea.

FIG. 9 shows a plan view of a main part of the output circuit OP1 and the output circuit OP2. Although FIG. 9 is a plan view, hatching is provided on the gate electrodes Ga to Gf to make the drawing easier to see. FIG. 10 is a cross-sectional view taken along the line BB shown in FIG. Since the cross-sectional view taken along the line AA shown in FIG. 9 is the same as that in FIG. 3, the description thereof will be omitted.

As shown in FIG. 1, the output circuit OP2 is composed of p-type MOSFET groups 2QD to 2QF. Each of these MISFET groups 2QD to 2QF is composed of one p-type MISFET or a plurality of p-type MISFETs connected in parallel to each other. For example, as shown in FIG. 9, the MISFET group 2QD is composed of four p-type MISFETs 2Qd connected in parallel to each other. Similarly, the MISFET group 2QE and the MISFET group 2QF are composed of a p-type MISFET2Qe and a p-type MISFET2Qf, respectively.

As shown in FIGS. 1 and 9, the source of the MISFET group 2QD to 2QF is connected to the terminal PAD, the drain of the MISFET group 2QD to 2QF is connected to the power supply voltage line VCC, and the gate of the MISFET group 2QD to 2QF. Are connected to the gate drive circuits DRd to DRf, respectively. That is, in the p-type MISFETs 2Qd to 2Qf, each drain region PD is electrically connected to the power supply voltage line VCS, each source region NS is electrically connected to the terminal PAD, and each gate electrode Gd to. The Gfs are electrically connected to the gate drive circuits DRd to DRf, respectively. The drain region PD and the source region PS are semiconductor regions in which p-type impurities are introduced into the semiconductor substrate SB.

An n-type well region NW is formed on the surface side of the semiconductor substrate SB, and an element separation portion STI is formed in the well region NW. The element separation portion STI is formed by forming a groove in the well region NW and embedding an insulating film made of, for example, silicon oxide in the groove. Further, the depth of the well region NW is deeper than the depth of the element separation portion STI. Therefore, the well region NW is formed so as to surround the bottom portion of the element separation portion STI.

As shown in FIG. 9, the active region AR2 and the feeding region SR2 are partitioned by the element separation unit STI in a plan view, but as shown in FIG. 10, the active region AR2 and the feeding region SR2 have a cross section. It is an integrated area in the visual sense. That is, the active region AR2 and the feeding region SR2 are each a part of the well region NW.

The power feeding region SR2 extends in the Y direction in a plan view. That is, the length of the feeding region SR2 in the Y direction is larger than the length of the feeding region SR2 in the X direction. An n-type body region (impurity region) NB is formed on the surface of the well region NW of the power feeding region SR2, and a silicide layer SI made of, for example, cobalt silicide or nickel silicide is formed on the body region NB. There is.

Further, although not shown in FIG. 9, a plurality of plug PGs are formed on the upper surface of the body region NB. The body region NB is electrically connected to the wiring M1 via the VDD layer SI and the plug PG. The wiring M1 is electrically connected to, for example, the power supply voltage line VCS, whereby the power supply potential Vcc is applied to the body region NB and the well region NW.

The active region AR2 is a region in which MISFET2Qd to 2Qf are formed. The gate electrodes Gd to Gf are formed on the well region NW via the gate insulating films GIF and GIF, respectively, and extend in the Y direction in a plan view.

The gate insulating films GIFd to GIFf are formed on the well region PW and on the side surface of the groove formed in the interlayer insulating film IL1. The materials constituting the gate insulating films GId to GIf include, for example, a silicon oxide film and a metal oxide film (high dielectric constant film) such as a hafnium oxide film or a tantalum oxide film formed on the silicon oxide film. It is a laminated film containing.

The gate electrodes Gd to GIF are embedded in the groove formed in the interlayer insulating film IL1 via the gate insulating films GId to GIF. The materials constituting the gate electrodes Gd to Gf are a titanium nitride film, a metal film such as an aluminum film, or a laminated film in which these metal films are appropriately laminated.

As described above, the gate insulating films GIF to GIF and the gate electrodes Gd to Gf of the seventh embodiment are formed by a so-called high-k last structure and a gate last structure.

Further, although not shown in FIGS. 9 and 10, a plug PG is formed on the upper surface of each of the gate electrodes Gd to Gf. The gate electrodes Gd to Gf are connected to the wiring M1 via the plug PG, and are electrically connected to the gate drive circuits DRd to DRf via the wiring M1 and other wiring.

Further, since the four gate electrodes Gd are connected to the same gate drive circuit DRd, the same potential is applied to each of the four gate electrodes Gd, and the four gate electrodes Gd are driven at the same timing. Similarly, the same potential is applied to each of the two gate electrodes Ge, and they are driven at the same timing. Further, the same potential is applied to each of the two gate electrodes Gf, and they are driven at the same timing.

A sidewall spacer SW is formed on both side surfaces of the gate electrodes Gd to Gf. The sidewall spacer SW is composed of, for example, a laminated film of a silicon oxide film and a silicon nitride film.

A p-type drain region (impurity region) PD and a p-type source region (impurity region) PS are formed on the surface of the well region NW of the active region AR2. The drain region PD and the source region PS are formed in a well region NW beside each gate electrode Gd to Gf, and are alternately arranged for each gate electrode Gd to Gf. That is, two MISFETs adjacent to each other are arranged so as to share one drain region PD or one source region PS.

Similar to the body region NB, the silicide layer SI is formed in a part on the drain region PD and a part on the source region PS. The silicide layer SI formed on the drain region PD and the source region PS is formed at a distance from the ends of the gate electrodes Gd to Gf by the width of the sidewall spacer SW.

Further, although not shown in FIGS. 9 and 10, a plurality of plug PGs are formed on the upper surfaces of the drain region PD and each source region PS. Each drain region PD and each source region PS are connected to the wiring M1 via the VDD layer SI and the plug PG. Through this wiring M1 and other wiring, each drain region PD is electrically connected to the power supply voltage line VCS, and each source region NS is electrically connected to the terminal PAD.

Similar to the output circuit OP1, the output circuit OP2 also has a problem that a current is generated when static electricity is applied to the terminal PAD. The problem that occurs in the output circuit OP2 is caused by the electrons of the hole-electron pairs generated at the junction between the drain region PD and the well region NW, and the output circuit OP2 starts the PNP bipolar operation. , Different from the output circuit OP1.

The PNP bipolar operation in the output circuit OP2 is less likely to occur than the NPN bipolar operation in the output circuit OP1, but in the seventh embodiment, the output circuit OP2 is provided with the same measures as the output circuit OP1 to provide the entire semiconductor device. Improves static electricity resistance.

Specifically, in the seventh embodiment, in the active region AR2, the MISFET group 2QD containing a relatively large amount of MISFET2Qd is a MISFET group 2QE containing a relatively small number of MISFET2Qe, or a MISFET group containing a relatively small number of MISFET2Qf. It is arranged at a position farther from the power feeding area SR2 than the 2QF. In other words, in the active region AR2, the four gate electrodes Gd connected to the gate drive circuit DRd are the two gate electrodes Ge connected to the gate drive circuit DRe or the two gate electrodes Ge connected to the gate drive circuit DRf. It is arranged at a position farther from the feeding region SR2 than the gate electrode Gf. That is, when the MISFETs 2Qd to 2Qf are arranged in the active region AR2, a plurality of MISFETs having a large number of gate electrodes having the same potential are arranged at a position farther from the feeding region SR2.

As described above, in the seventh embodiment, the reliability of the semiconductor device can be further improved as compared with the first embodiment.

Further, it is also possible to apply the technical idea described in the above-described embodiments 2 to 6 to the output circuit OP2 of the seventh embodiment.

(Embodiment 8)
11 and 12 show the semiconductor device of the eighth embodiment. In the following description, the differences from the seventh embodiment will be mainly described.

FIG. 11 shows a plan view of a main part of the output circuit OP1 and the output circuit OP2. Although FIG. 11 is a plan view, hatching is provided on the gate electrodes Ga to Gf, G0, and the insulating film SPF to make the drawing easier to see. FIG. 12 is a cross-sectional view taken along the line AA shown in FIG. Since the cross-sectional view taken along the line BB shown in FIG. 11 is the same as that in FIG. 10, the description thereof will be omitted.

The semiconductor device of the eighth embodiment has a structure in which the technical idea described in the above-described second to sixth embodiments is applied to the semiconductor device of the seventh embodiment. Therefore, the semiconductor device of the eighth embodiment can obtain the effects shown in the above-described first to seventh embodiments.

Further, the eighth embodiment is significantly different from the above-described first to seventh embodiments in that the insulating film SPF for preventing the formation of the VDD layer SI is applied to the output circuit OP1.

As shown in FIGS. 11 and 12, the insulating film SPF is formed on each side surface of the gate electrodes Ga to Gc via the sidewall spacer SW. That is, the insulating film SPF is formed so as to cover a part of the drain region ND and a part of the source region NS in the X direction. Therefore, in the first embodiment and the like, the silicide layer SI is formed so as to be separated from the ends of the gate electrodes Ga to Gc by the width of the sidewall spacer SW, but in the eighth embodiment, the silicide layer SI is formed. The layer SI is formed apart from the ends of the gate electrodes Ga to Gc by the sum of the width of the sidewall spacer SW and the width of the insulating film SPF.

Therefore, in the X direction, the distance from the end of each gate electrode Ga to Gc in the output circuit OP1 to the VDD layer SI is larger than the distance from the end of each gate electrode Gd to Gf in the output circuit OP2 to the silicide layer SI. ,long. In other words, the area of the silicide layer SI formed on the drain region ND and the source region NS in the active region AR1 is the area of the silicide layer SI formed on the drain region PD and the source region PS in the active region AR2. Smaller than the area.

As described in the seventh embodiment, the NPN bipolar operation in the output circuit OP1 is more likely to occur than the PNP bipolar operation in the output circuit OP2. Therefore, in the output circuit OP1, by reducing the area of the silicide layer SI by using the insulating film SPF, the entire drain region ND is made slightly high resistance, and the electric field in the vicinity of the drain region ND is relaxed. As a result, the electrostatic resistance of the output circuit OP1 can be improved as compared with the output circuit OP2.

Further, in the eighth embodiment, the insulating film SPF is applied to the MISFET groups 1QA to 1QC of the output circuit OP1, but the insulating film SPF is applied only to the MISFET group 1QA where the current concentration due to static electricity is the largest. May be good.

Further, the semiconductor device of the eighth embodiment has a structure in which the technical idea described in the above-described second to sixth embodiments is applied to the semiconductor device of the seventh embodiment, but the insulating film SPF has an embodiment. It may be appropriately applied to each of the semiconductor devices of the first to seventh forms.

Although the invention made by the inventor of the present application has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof.

For example, in each embodiment, the gate insulating films GIa to GIF and the gate electrodes Ga to Gf have been described with examples of so-called high-k last structure and gate last structure, but the gist of each embodiment is described in these. Not limited. The gate insulating films GIa to GIF and the gate electrodes Ga to Gf may be formed by patterning, that is, a so-called High-k first structure and a gate first structure. Further, the gate insulating films GIa to GIF may have a High-k first structure, and the gate electrodes Ga to Gf may have a gate last structure.

1Qa to 1Qc n-type MISFET
1QA to 1QC n-type MISFET group 2Qd to 2Qf p-type MISFET
2QD to 2QF p-type MOSFETs AR1, AR2 Active region CL clamp element D1, D2 Diodes DRa to DRf Gate drive circuit G0, Ga to Gf Gate electrodes GIa to GIf Gate insulating film IL1 to IL3 Interlayer insulating film L1 to L4 Distance M1 Wiring NB Body area ND, ND1, ND2 Drain area NS Source area NW Well area OP1 to OP3 Output circuit PAD Output terminal PB Body area PC protection circuit PD Drain area PG plug PS Source area PW Well area Rpw Resistance component SB Semiconductor substrate SI Layer SPF Insulating film SR1, SR2 Power supply area STI Element separation part SW sidewall spacer Vcc Power supply potential VCS Power supply voltage line Vs Grounding potential VSS Grounding voltage line

Claims (16)

With a semiconductor substrate
The first conductive type first well region formed on the semiconductor substrate and
The first element separation portion formed in the first well region and
The first feeding region and the first active region, which are a part of the first well region and are partitioned by the first element separating portion in a plan view,
A plurality of first gate electrodes formed on the first active region,
A plurality of first impurity regions formed in the first active region next to the plurality of first gate electrodes and which are the second conductive type opposite to the first conductive type, and
A first gate drive circuit that is electrically connected to a plurality of second gate electrodes that are a part of the plurality of first gate electrodes.
A second gate drive circuit that is electrically connected to one or more third gate electrodes that are part of the plurality of first gate electrodes.
Have,
In a plan view, the first feeding region extends in the first direction.
In a plan view, the plurality of first gate electrodes extend in the first direction and are arranged adjacent to each other in the second direction orthogonal to the first direction.
The number of the plurality of second gate electrodes is larger than the number of the one or more third gate electrodes.
A semiconductor device in which, in the second direction, the plurality of second gate electrodes are arranged at a position farther from the first feeding region than the one or more third gate electrodes. In the semiconductor device according to claim 1,
The multilayer wiring formed on the semiconductor substrate and
The terminals that are part of the top layer wiring of the multi-layer wiring and
A protection circuit for static electricity electrically connected to the terminal,
With more
A semiconductor device in which the terminals are electrically connected to a part of the plurality of first impurity regions. In the semiconductor device according to claim 1,
The plurality of first gate electrodes include the first gate drive circuit and a dummy gate electrode that is not connected to the second gate drive circuit.
The dummy gate electrode is a semiconductor device arranged between the first feeding region and the one or more third gate electrodes. In the semiconductor device according to claim 3,
The interlayer insulating film formed on the semiconductor substrate and
A plurality of grooves formed in the interlayer insulating film and
With more
A semiconductor device in which the plurality of first gate electrodes and the dummy gate electrodes are each embedded in the plurality of grooves. In the semiconductor device according to claim 1,
A second feeding region that is a part of the first well region, is partitioned from the first active region by the first element separating portion, and extends in the first direction in a plan view.
A third gate drive circuit that is electrically connected to one or more fourth gate electrodes that are part of the plurality of first gate electrodes.
With more
In the second direction, the first active region is arranged at a position sandwiched between the first feeding region and the second feeding region.
The number of the plurality of second gate electrodes is larger than the number of the one or more fourth gate electrodes.
A semiconductor device in which, in the second direction, the plurality of second gate electrodes are arranged at a position farther from the second feeding region than the one or more fourth gate electrodes. In the semiconductor device according to claim 5,
In the second direction, a plurality of the first active regions are arranged at positions sandwiched between the first feeding region and the second feeding region.
A semiconductor device in which the plurality of first gate electrodes and the plurality of first impurity regions are formed in each of the plurality of first active regions. In the semiconductor device according to claim 6,
The plurality of first gate electrodes include a first dummy gate electrode and a second dummy gate electrode that are not connected to the first, second, and third gate drive circuits.
The first dummy gate electrode and the second dummy gate electrode are arranged in the first active region located at the most end in the first direction among the plurality of first active regions.
The first dummy gate electrode is arranged between the first feeding region and the one or more third gate electrodes.
The second dummy gate electrode is a semiconductor device arranged between the second feeding region and the one or more fourth gate electrodes. In the semiconductor device according to claim 7,
The interlayer insulating film formed on the semiconductor substrate and
A plurality of grooves formed in the interlayer insulating film and
With more
A semiconductor device in which the plurality of first gate electrodes, the first dummy gate electrode, and the second dummy gate electrode are each embedded in the plurality of grooves. In the semiconductor device according to claim 1,
A second feeding region that is a part of the first well region, is partitioned from the first active region by the first element separating portion, and extends in the first direction in a plan view.
A third feeding region and a fourth feeding region which are a part of the first well region, are partitioned from the first active region by the first element separating portion, and extend in the second direction in a plan view. When,
With more
In the second direction, the first active region is arranged at a position sandwiched between the first feeding region and the second feeding region.
In the first direction, the first active region is arranged at a position sandwiched between the third feeding region and the fourth feeding region.
A semiconductor device in which the first, second, third, and fourth feeding regions are integrally connected so as to surround the first active region in a plan view. In the semiconductor device according to claim 9,
A semiconductor device in which the distance between the first feeding region and the first active region is shorter than the distance between the third feeding region and the first active region. In the semiconductor device according to claim 9,
A semiconductor device in which the width of the first feeding region in the second direction is larger than the width of the third feeding region in the first direction. In the semiconductor device according to claim 1,
The second well region of the second conductive type formed on the semiconductor substrate and
A second element separating portion formed in the second well region and
The fifth feeding region and the second active region, which are a part of the second well region and are partitioned by the second element separating portion in a plan view,
A plurality of fifth gate electrodes formed on the second active region,
A plurality of second impurity regions formed in the second active region next to the plurality of fifth gate electrodes and being the first conductive type, respectively.
A fourth gate drive circuit that is electrically connected to a plurality of sixth gate electrodes that are a part of the plurality of fifth gate electrodes.
A fifth gate drive circuit that is electrically connected to one or more seventh gate electrodes that are part of the plurality of fifth gate electrodes.
With more
In a plan view, the fifth feeding region extends in the first direction.
In a plan view, the plurality of fifth gate electrodes extend in the first direction and are arranged adjacent to each other in the second direction.
The number of the plurality of sixth gate electrodes is larger than the number of the one or more seventh gate electrodes.
A semiconductor device in which, in the second direction, the plurality of sixth gate electrodes are arranged at a position farther from the fifth feeding region than the one or more seventh gate electrodes. In the semiconductor device according to claim 12,
The multilayer wiring formed on the semiconductor substrate and
The terminals that are part of the top layer wiring of the multi-layer wiring and
A protection circuit for static electricity electrically connected to the terminal,
With more
A semiconductor device in which the terminals are electrically connected to a part of the plurality of first impurity regions and a part of the plurality of second impurity regions. In the semiconductor device according to claim 12,
A plurality of first SiO layers formed on the plurality of first impurity regions, respectively.
A plurality of second silicide layers, each of which is formed on the plurality of second impurity regions,
With more
In the second direction, the distance between each end of the plurality of first gate electrodes and each of the plurality of first silicide layers is determined by the respective ends of the plurality of fifth gate electrodes. A semiconductor device that is longer than the distance between each of the plurality of second VDD layers. In the semiconductor device according to claim 14,
A semiconductor device in which the plurality of first silicide layers and the plurality of second silicide layers are made of cobalt silicide or nickel silicide, respectively. In the semiconductor device according to claim 12,
The first conductive type is a p type and is
The second conductive type is an n-type semiconductor device.

Images