JP6766923B2 - 多層配線構造体 - Google Patents

多層配線構造体 Download PDF

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Publication number
JP6766923B2
JP6766923B2 JP2019114662A JP2019114662A JP6766923B2 JP 6766923 B2 JP6766923 B2 JP 6766923B2 JP 2019114662 A JP2019114662 A JP 2019114662A JP 2019114662 A JP2019114662 A JP 2019114662A JP 6766923 B2 JP6766923 B2 JP 6766923B2
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Prior art keywords
layer
insulating layer
conductive
wiring
substrate
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JP2019114662A
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Japanese (ja)
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JP2019153818A5 (https=
JP2019153818A (ja
Inventor
貴正 高野
貴正 高野
工藤　寛
寛 工藤
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2019114662A 2019-06-20 2019-06-20 多層配線構造体 Active JP6766923B2 (ja)

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JP2019114662A JP6766923B2 (ja) 2019-06-20 2019-06-20 多層配線構造体

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JP2019114662A JP6766923B2 (ja) 2019-06-20 2019-06-20 多層配線構造体

Related Parent Applications (1)

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JP2018085383A Division JP6544462B2 (ja) 2018-04-26 2018-04-26 多層配線構造体

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JP2019153818A JP2019153818A (ja) 2019-09-12
JP2019153818A5 JP2019153818A5 (https=) 2019-10-24
JP6766923B2 true JP6766923B2 (ja) 2020-10-14

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Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002204078A (ja) * 2000-12-28 2002-07-19 Fujitsu Ltd 多層回路基板及び半導体集積回路装置
JP4340729B2 (ja) * 2002-06-10 2009-10-07 富士通マイクロエレクトロニクス株式会社 半導体装置とその製造方法
JP4561235B2 (ja) * 2004-08-20 2010-10-13 富士通株式会社 半導体装置の設計方法
JP5413371B2 (ja) * 2008-10-21 2014-02-12 日本電気株式会社 半導体装置及びその製造方法

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JP2019153818A (ja) 2019-09-12

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