JP6750969B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP6750969B2
JP6750969B2 JP2016124326A JP2016124326A JP6750969B2 JP 6750969 B2 JP6750969 B2 JP 6750969B2 JP 2016124326 A JP2016124326 A JP 2016124326A JP 2016124326 A JP2016124326 A JP 2016124326A JP 6750969 B2 JP6750969 B2 JP 6750969B2
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insulating film
film
trench
gate
semiconductor device
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Japanese (ja)
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JP2017228679A (ja
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泰典 山下
泰典 山下
耕一 新井
耕一 新井
賢一 久田
賢一 久田
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2016124326A priority Critical patent/JP6750969B2/ja
Priority to US15/627,333 priority patent/US10109733B2/en
Priority to CN201710475891.XA priority patent/CN107546270B/zh
Publication of JP2017228679A publication Critical patent/JP2017228679A/ja
Priority to US16/137,279 priority patent/US10256339B2/en
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    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Electrodes Of Semiconductors (AREA)
JP2016124326A 2016-06-23 2016-06-23 半導体装置の製造方法 Active JP6750969B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2016124326A JP6750969B2 (ja) 2016-06-23 2016-06-23 半導体装置の製造方法
US15/627,333 US10109733B2 (en) 2016-06-23 2017-06-19 Semiconductor device for power transistor
CN201710475891.XA CN107546270B (zh) 2016-06-23 2017-06-21 半导体器件及其制造方法
US16/137,279 US10256339B2 (en) 2016-06-23 2018-09-20 Semiconductor device for power transistor

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JP2016124326A JP6750969B2 (ja) 2016-06-23 2016-06-23 半導体装置の製造方法

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US10325982B1 (en) * 2018-05-17 2019-06-18 Northrop Grumman Systems Corporation Drain ledge for self-aligned gate and independent channel region and drain-side ridges for SLCFET
JP7404204B2 (ja) * 2020-09-18 2023-12-25 株式会社東芝 半導体装置の製造方法
CN113745316A (zh) * 2021-08-31 2021-12-03 深圳市威兆半导体有限公司 屏蔽栅mosfet器件、芯片和终端设备
CN113851523B (zh) * 2021-09-02 2022-12-13 深圳市威兆半导体股份有限公司 一种屏蔽栅mosfet及制作方法
US20230197771A1 (en) * 2021-12-16 2023-06-22 Nanya Technology Corporation Memory device having word lines with reduced leakage

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US6455378B1 (en) * 1999-10-26 2002-09-24 Hitachi, Ltd. Method of manufacturing a trench gate power transistor with a thick bottom insulator
JP2001127072A (ja) * 1999-10-26 2001-05-11 Hitachi Ltd 半導体装置
JP2002222950A (ja) * 2001-01-25 2002-08-09 Denso Corp 炭化珪素半導体装置の製造方法
JP4857827B2 (ja) * 2006-03-09 2012-01-18 富士電機株式会社 Mos型半導体装置の製造方法
JP5729331B2 (ja) * 2011-04-12 2015-06-03 株式会社デンソー 半導体装置の製造方法及び半導体装置
JP2013232533A (ja) * 2012-04-27 2013-11-14 Rohm Co Ltd 半導体装置および半導体装置の製造方法

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US10256339B2 (en) 2019-04-09
US20170373183A1 (en) 2017-12-28
CN107546270A (zh) 2018-01-05
US20190027597A1 (en) 2019-01-24
US10109733B2 (en) 2018-10-23
CN107546270B (zh) 2022-05-03
JP2017228679A (ja) 2017-12-28

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